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clk: renesas: r8a7795: Add THS/TSC clock
authorKhiem Nguyen <khiem.nguyen.xt@rvc.renesas.com>
Sun, 19 Jun 2016 02:34:18 +0000 (09:34 +0700)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 21 Jun 2016 07:21:06 +0000 (09:21 +0200)
Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@rvc.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r8a7795-cpg-mssr.c patch | blob | blame | history

diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index b9485ab891a05335e49455608a18b49d3bddbd46..d359c92e13a65c00725f3a1178a1096babc0e226 100644 (file)
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -151,6 +151,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
        DEF_MOD("hscif2",                518,   R8A7795_CLK_S3D1),
        DEF_MOD("hscif1",                519,   R8A7795_CLK_S3D1),
        DEF_MOD("hscif0",                520,   R8A7795_CLK_S3D1),
+       DEF_MOD("thermal",               522,   R8A7795_CLK_CP),
        DEF_MOD("pwm",                   523,   R8A7795_CLK_S3D4),
        DEF_MOD("fcpvd3",                600,   R8A7795_CLK_S2D1),
        DEF_MOD("fcpvd2",                601,   R8A7795_CLK_S2D1),