PCI: rockchip: Control vpcie0v9 for system PM
authorShawn Lin <shawn.lin@rock-chips.com>
Tue, 2 May 2017 07:31:23 +0000 (15:31 +0800)
committerBjorn Helgaas <bhelgaas@google.com>
Sun, 2 Jul 2017 23:45:54 +0000 (18:45 -0500)
vpcie0v9 is used for PHY, so we could disable it as we don't need PHY to
work then in S3 if folks assign it DT.  But we should note that there is a
side effect that we could not support beacon wakeup if we disable vpcie0v9
for aggressive power-saving.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Brian Norris <briannorris@chromium.org>
Cc: Jeffy Chen <jeffy.chen@rock-chips.com>
drivers/pci/host/pcie-rockchip.c

index 29332ba06bc1b4d3deb77a24138b9a5a652c7533..5e4f758044d4ca4031bf84f657dc8a41915f7365 100644 (file)
@@ -1251,6 +1251,9 @@ static int __maybe_unused rockchip_pcie_suspend_noirq(struct device *dev)
        clk_disable_unprepare(rockchip->aclk_perf_pcie);
        clk_disable_unprepare(rockchip->aclk_pcie);
 
+       if (!IS_ERR(rockchip->vpcie0v9))
+               regulator_disable(rockchip->vpcie0v9);
+
        return ret;
 }
 
@@ -1259,6 +1262,14 @@ static int __maybe_unused rockchip_pcie_resume_noirq(struct device *dev)
        struct rockchip_pcie *rockchip = dev_get_drvdata(dev);
        int err;
 
+       if (!IS_ERR(rockchip->vpcie0v9)) {
+               err = regulator_enable(rockchip->vpcie0v9);
+               if (err) {
+                       dev_err(dev, "fail to enable vpcie0v9 regulator\n");
+                       return err;
+               }
+       }
+
        clk_prepare_enable(rockchip->clk_pcie_pm);
        clk_prepare_enable(rockchip->hclk_pcie);
        clk_prepare_enable(rockchip->aclk_perf_pcie);