* 10x4074560=40M(0x28) support 10bit
*/
//size = <0x02800000>;
- size = <0x05800000>;
+ size = <0x0B000000>;
alignment = <0x400000>;
};
/* POST PROCESS MANAGER */
* 10x4736064=45.2M(0x2e) support 12bit
* 10x4074560=40M(0x28) support 10bit
*/
- size = <0x05800000>;
+ size = <0x0B000000>;
alignment = <0x400000>;
};
/* POST PROCESS MANAGER */
* 10x4736064=45.2M(0x2e) support 12bit
* 10x4074560=40M(0x28) support 10bit
*/
- size = <0x05800000>;
+ size = <0x0B000000>;
alignment = <0x400000>;
};
/* POST PROCESS MANAGER */
* 10x4736064=45.2M(0x2e) support 12bit
* 10x4074560=40M(0x28) support 10bit
*/
- size = <0x05800000>;
+ size = <0x0B000000>;
alignment = <0x400000>;
};
/* POST PROCESS MANAGER */
* 10x4736064=45.2M(0x2e) support 12bit
* 10x4074560=40M(0x28) support 10bit
*/
- size = <0x02800000>;
+ size = <0x0B000000>;
alignment = <0x400000>;
};
/* POST PROCESS MANAGER */
* 10x4736064=45.2M(0x2e) support 12bit
* 10x4074560=40M(0x28) support 10bit
*/
- size = <0x05800000>;
+ size = <0x0B000000>;
alignment = <0x400000>;
};
/* POST PROCESS MANAGER */
* 10x4736064=45.2M(0x2e) support 12bit
* 10x4074560=40M(0x28) support 10bit
*/
- size = <0x05800000>;
+ size = <0x0B000000>;
alignment = <0x400000>;
};
/* POST PROCESS MANAGER */
* 10x4736064=45.2M(0x2e) support 12bit
* 10x4074560=40M(0x28) support 10bit
*/
- size = <0x0 0x05800000>;
+ size = <0x0 0x0B000000>;
alignment = <0x0 0x400000>;
};
/* POST PROCESS MANAGER */
* 10x4736064=45.2M(0x2e) support 12bit
* 10x4074560=40M(0x28) support 10bit
*/
- size = <0x0 0x05800000>;
+ size = <0x0 0x0B000000>;
alignment = <0x0 0x400000>;
};
/* POST PROCESS MANAGER */
* 10x4736064=45.2M(0x2e) support 12bit
* 10x4074560=40M(0x28) support 10bit
*/
- size = <0x0 0x05800000>;
+ size = <0x0 0x0B000000>;
alignment = <0x0 0x400000>;
};
/* POST PROCESS MANAGER */
* 10x4736064=45.2M(0x2e) support 12bit
* 10x4074560=40M(0x28) support 10bit
*/
- size = <0x0 0x05800000>;
+ size = <0x0 0x0B000000>;
alignment = <0x0 0x400000>;
};
/* POST PROCESS MANAGER */
* 10x4736064=45.2M(0x2e) support 12bit
* 10x4074560=40M(0x28) support 10bit
*/
- size = <0x0 0x02800000>;
+ size = <0x0 0x0B000000>;
alignment = <0x0 0x400000>;
};
/* POST PROCESS MANAGER */
status = "okay";
};
- deinterlace {
- compatible = "amlogic, deinterlace";
+ multi-di {
+ compatible = "amlogic, dim-sm1";
status = "okay";
/* 0:use reserved; 1:use cma; 2:use cma as reserved */
flag_cma = <1>;
nrds-enable = <1>;
pps-enable = <1>;
};
+
+ deinterlace {
+ compatible = "amlogic, deinterlace";
+ status = "disable";//status = "okay";
+ /* 0:use reserved; 1:use cma; 2:use cma as reserved */
+ flag_cma = <1>;
+ //memory-region = <&di_reserved>;
+ //memory-region = <&di_cma_reserved>;
+ interrupts = <0 46 1
+ 0 40 1>;
+ interrupt-names = "pre_irq", "post_irq";
+ clocks = <&clkc CLKID_VPU_CLKB_TMP_COMP>,
+ <&clkc CLKID_VPU_CLKB_COMP>;
+ clock-names = "vpu_clkb_tmp_composite",
+ "vpu_clkb_composite";
+ clock-range = <334 667>;
+ /* buffer-size = <3621952>;(yuv422 8bit) */
+ buffer-size = <4074560>;/*yuv422 fullpack*/
+ /* reserve-iomap = "true"; */
+ /* if enable nr10bit, set nr10bit-support to 1 */
+ post-wr-support = <1>;
+ nr10bit-support = <1>;
+ nrds-enable = <1>;
+ pps-enable = <1>;
+ };
+
dvb {
compatible = "amlogic, dvb";
dev_name = "dvb";
* 10x4736064=45.2M(0x2e) support 12bit
* 10x4074560=40M(0x28) support 10bit
*/
- size = <0x0 0x05800000>;
+ size = <0x0 0x0B000000>;
alignment = <0x0 0x400000>;
};
/* POST PROCESS MANAGER */
* 10x4736064=45.2M(0x2e) support 12bit
* 10x4074560=40M(0x28) support 10bit
*/
- size = <0x0 0x05800000>;
+ size = <0x0 0x0B000000>;
alignment = <0x0 0x400000>;
};
/* POST PROCESS MANAGER */