clk: tegra: Enable sor1 and sor1_src on Tegra210
authorThierry Reding <treding@nvidia.com>
Thu, 9 Jun 2016 15:47:17 +0000 (17:47 +0200)
committerThierry Reding <treding@nvidia.com>
Fri, 17 Jun 2016 15:24:10 +0000 (17:24 +0200)
Make the sor1 and sor1_src clocks available on Tegra210. They will be
used by the display driver to support HDMI and DP.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-tegra210.c
include/dt-bindings/clock/tegra210-car.h

index c1fabd82aa1aca2325fb640afa88074c4c291868..aab32af77aa22263763278dcfce1a802ea9cc0a4 100644 (file)
@@ -2155,6 +2155,8 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
        [tegra_clk_dpaux1] = { .dt_id = TEGRA210_CLK_DPAUX1, .present = true },
        [tegra_clk_sor0] = { .dt_id = TEGRA210_CLK_SOR0, .present = true },
        [tegra_clk_sor0_lvds] = { .dt_id = TEGRA210_CLK_SOR0_LVDS, .present = true },
+       [tegra_clk_sor1] = { .dt_id = TEGRA210_CLK_SOR1, .present = true },
+       [tegra_clk_sor1_src] = { .dt_id = TEGRA210_CLK_SOR1_SRC, .present = true },
        [tegra_clk_gpu] = { .dt_id = TEGRA210_CLK_GPU, .present = true },
        [tegra_clk_pll_g_ref] = { .dt_id = TEGRA210_CLK_PLL_G_REF, .present = true, },
        [tegra_clk_uartb_8] = { .dt_id = TEGRA210_CLK_UARTB, .present = true },
index bd3530e56d4699e8a9b87f7e3bdb136b648065a6..35288b20f2c9cffcaebdf5075946b25dce6fad4b 100644 (file)
 #define TEGRA210_CLK_CLK_OUT_3 279
 #define TEGRA210_CLK_BLINK 280
 /* 281 */
-/* 282 */
+#define TEGRA210_CLK_SOR1_SRC 282
 /* 283 */
 #define TEGRA210_CLK_XUSB_HOST_SRC 284
 #define TEGRA210_CLK_XUSB_FALCON_SRC 285