drm/bridge/sii8620: fix peer device capabilities read code
authorAndrzej Hajda <a.hajda@samsung.com>
Wed, 1 Feb 2017 07:47:36 +0000 (08:47 +0100)
committerArchit Taneja <architt@codeaurora.org>
Thu, 2 Feb 2017 09:45:24 +0000 (15:15 +0530)
Peer capabilities should be read differently depending on protocol version.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Link: http://patchwork.freedesktop.org/patch/msgid/1485935272-17337-10-git-send-email-a.hajda@samsung.com
drivers/gpu/drm/bridge/sil-sii8620.c

index 384222612005e12b1345a56ea2daf0a111e3028f..be953f3aea9ce05b3999abef07b27a6109afc5b4 100644 (file)
@@ -1412,7 +1412,8 @@ static void sii8620_status_changed_path(struct sii8620 *ctx)
                sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE),
                                      MHL_DST_LM_CLK_MODE_NORMAL
                                      | MHL_DST_LM_PATH_ENABLED);
-               sii8620_mt_read_devcap(ctx, false);
+               if (!sii8620_is_mhl3(ctx))
+                       sii8620_mt_read_devcap(ctx, false);
        } else {
                sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE),
                                      MHL_DST_LM_CLK_MODE_NORMAL);
@@ -1664,6 +1665,14 @@ static void sii8620_irq_infr(struct sii8620 *ctx)
                sii8620_start_video(ctx);
 }
 
+static void sii8620_got_xdevcap(struct sii8620 *ctx, int ret)
+{
+       if (ret < 0)
+               return;
+
+       sii8620_mt_read_devcap(ctx, false);
+}
+
 static void sii8620_irq_tdm(struct sii8620 *ctx)
 {
        u8 stat = sii8620_readb(ctx, REG_TRXINTH);
@@ -1675,6 +1684,7 @@ static void sii8620_irq_tdm(struct sii8620 *ctx)
                ctx->burst.r_size = SII8620_BURST_BUF_LEN;
                sii8620_burst_tx_rbuf_info(ctx, SII8620_BURST_BUF_LEN);
                sii8620_mt_read_devcap(ctx, true);
+               sii8620_mt_set_cont(ctx, sii8620_got_xdevcap);
        } else {
                sii8620_write_seq_static(ctx,
                        REG_MHL_PLL_CTL2, 0,