drm/amdgpu: when dpm disabled, also can enable uvd cg/pg.
authorRex Zhu <Rex.Zhu@amd.com>
Fri, 20 Jan 2017 04:06:05 +0000 (12:06 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 8 Feb 2017 22:20:03 +0000 (17:20 -0500)
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

index 6f62ac473064e1dddde2ee6d4e4617cee962c33f..6d6ab7f11b4c14fd10579c4d276b3cc8ce03a009 100644 (file)
@@ -1113,6 +1113,11 @@ static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
                        amdgpu_dpm_enable_uvd(adev, false);
                } else {
                        amdgpu_asic_set_uvd_clocks(adev, 0, 0);
+                       /* shutdown the UVD block */
+                       amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
+                                                           AMD_PG_STATE_GATE);
+                       amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
+                                                           AMD_CG_STATE_GATE);
                }
        } else {
                schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
@@ -1129,6 +1134,10 @@ void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
                        amdgpu_dpm_enable_uvd(adev, true);
                } else {
                        amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
+                       amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
+                                                           AMD_CG_STATE_UNGATE);
+                       amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
+                                                           AMD_PG_STATE_UNGATE);
                }
        }
 }