drm/nouveau/device: switch to dev_printk macros
authorBen Skeggs <bskeggs@redhat.com>
Thu, 20 Aug 2015 04:54:13 +0000 (14:54 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Fri, 28 Aug 2015 02:40:25 +0000 (12:40 +1000)
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c

index bced8ea58f4551aa7bb8676ad9fd8d8dd96b7a6d..c58ea4f44c7027833f95342d7d150ae5d370dd97 100644 (file)
@@ -414,14 +414,11 @@ nvkm_devobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
                }
 
                if (ret) {
-                       nv_error(device, "unknown chipset, 0x%08x\n", boot0);
+                       nvdev_error(device, "unknown chipset (%08x)\n", boot0);
                        return ret;
                }
 
-               nv_info(device, "BOOT0  : 0x%08x\n", boot0);
-               nv_info(device, "Chipset: %s (NV%02X)\n",
-                       device->cname, device->chipset);
-               nv_info(device, "Family : NV%02X\n", device->card_type);
+               nvdev_info(device, "NVIDIA %s (%08x)\n", device->cname, boot0);
 
                /* determine frequency of timing crystal */
                if ( device->card_type <= NV_10 || device->chipset < 0x17 ||
@@ -436,8 +433,6 @@ nvkm_devobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
                case 0x00400000: device->crystal = 27000; break;
                case 0x00400040: device->crystal = 25000; break;
                }
-
-               nv_debug(device, "crystal freq: %dKHz\n", device->crystal);
        } else
        if ( (args->v0.disable & NV_DEVICE_V0_DISABLE_IDENTIFY)) {
                device->cname = "NULL";
@@ -447,7 +442,7 @@ nvkm_devobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
        if (!(args->v0.disable & NV_DEVICE_V0_DISABLE_MMIO) && !device->pri) {
                device->pri = ioremap(mmio_base, mmio_size);
                if (!device->pri) {
-                       nv_error(device, "unable to map device registers\n");
+                       nvdev_error(device, "unable to map PRI\n");
                        return -ENOMEM;
                }
        }
index 65b151da83178d8399054e70f0a13badbb04fea2..d8ddd228491abcdf3e9a7c99c0b6b8dd50874112 100644 (file)
@@ -350,7 +350,6 @@ gf100_identify(struct nvkm_device *device)
                device->oclass[NVDEV_ENGINE_PM     ] = gf117_pm_oclass;
                break;
        default:
-               nv_fatal(device, "unknown Fermi chipset\n");
                return -EINVAL;
        }
 
index 2b1fce20445b95ed17b4ef5cb7328a553207e07d..4e0d3094435990f27a39fea5a1d83b3ba25de0e5 100644 (file)
@@ -318,7 +318,6 @@ gk104_identify(struct nvkm_device *device)
                device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
                break;
        default:
-               nv_fatal(device, "unknown Kepler chipset\n");
                return -EINVAL;
        }
 
index a51b3ce50f364b31937d4c0e6f4e092a2302cab3..cd979543cdff21a3fc8b7e5f10a965a55c9b3268 100644 (file)
@@ -202,7 +202,6 @@ gm100_identify(struct nvkm_device *device)
                device->oclass[NVDEV_ENGINE_CE2    ] = &gm204_ce2_oclass;
                break;
        default:
-               nv_fatal(device, "unknown Maxwell chipset\n");
                return -EINVAL;
        }
 
index 5a2ae043b478c47b55b65accdcec0fb9684b0842..ec357da766e5dd482d1ed115165d3531567e008f 100644 (file)
@@ -81,7 +81,6 @@ nv04_identify(struct nvkm_device *device)
                device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
                break;
        default:
-               nv_fatal(device, "unknown RIVA chipset\n");
                return -EINVAL;
        }
 
index 94a1ca45e94a797d0d0a296818927b3fb4412c02..37997e848d29547038baf811916d16af4c561ad7 100644 (file)
@@ -196,7 +196,6 @@ nv10_identify(struct nvkm_device *device)
                device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
                break;
        default:
-               nv_fatal(device, "unknown Celsius chipset\n");
                return -EINVAL;
        }
 
index d5ec8937df68d3bafcb0debb3c8ebdf3be6b70f2..a0d414dcc1fd139bdabee8e643ab37889ae05c34 100644 (file)
@@ -123,7 +123,6 @@ nv20_identify(struct nvkm_device *device)
                device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
                break;
        default:
-               nv_fatal(device, "unknown Kelvin chipset\n");
                return -EINVAL;
        }
 
index dda09621e898161277a1b292092776876f1991b0..ea1739739e5f2f1eca8a2b8b929b9d2cd1ef2981 100644 (file)
@@ -145,7 +145,6 @@ nv30_identify(struct nvkm_device *device)
                device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
                break;
        default:
-               nv_fatal(device, "unknown Rankine chipset\n");
                return -EINVAL;
        }
 
index b4ad791b48519a3daef318839f1115c73b60b1f9..9c7aa8d0ebd4cb0dcefdb1982642305440fbf35f 100644 (file)
@@ -419,7 +419,6 @@ nv40_identify(struct nvkm_device *device)
                device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
                break;
        default:
-               nv_fatal(device, "unknown Curie chipset\n");
                return -EINVAL;
        }
 
index a2627ec67c116eb32c730ff99dc9c5f8d46adeb2..3c97dba02fc4ef2f818dce2907bdabd3a6cbe27d 100644 (file)
@@ -470,7 +470,6 @@ nv50_identify(struct nvkm_device *device)
                device->oclass[NVDEV_ENGINE_PM     ] =  gt215_pm_oclass;
                break;
        default:
-               nv_fatal(device, "unknown Tesla chipset\n");
                return -EINVAL;
        }