drm/i915: WaRsUseTimeoutMode

Enable TO mode for RC6 for SKL till D0 and BXT till A0.

Cc: Tom O'Rourke <Tom.O'Rourke@intel.com>
Cc: Akash Goel <akash.goel@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Reviewed-by: Alex Dai <yu.dai@intel.com>
[danvet: Fixup line continuation alignment.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 09be8fc590d5d51db807bcdc7d7acba49ba7dab9..b4e0d1570ec68d7231b8feb2fdea98e2703024fa 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4871,9 +4871,16 @@ static void gen9_enable_rc6(struct drm_device *dev)
                rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
        DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
                        "on" : "off");
-       I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
-                                  GEN6_RC_CTL_EI_MODE(1) |
-                                  rc6_mask);
+
+       if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
+           (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0))
+               I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
+                          GEN7_RC_CTL_TO_MODE |
+                          rc6_mask);
+       else
+               I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
+                          GEN6_RC_CTL_EI_MODE(1) |
+                          rc6_mask);
 
        /*
         * 3b: Enable Coarse Power Gating only when RC6 is enabled.