i386: prepare shared pci/mmconfig.c

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

diff --git a/arch/i386/pci/Makefile b/arch/i386/pci/Makefile
index 44650e03308b0ad6d849abc0dcc0645800292be5..cdd6828b5abb4015f91091cf4ccc5d1a6432ded0 100644 (file)
--- a/arch/i386/pci/Makefile
+++ b/arch/i386/pci/Makefile
@@ -1,7 +1,7 @@
 obj-y                          := i386.o init.o
 
 obj-$(CONFIG_PCI_BIOS)         += pcbios.o
-obj-$(CONFIG_PCI_MMCONFIG)     += mmconfig.o direct.o mmconfig-shared.o
+obj-$(CONFIG_PCI_MMCONFIG)     += mmconfig_32.o direct.o mmconfig-shared.o
 obj-$(CONFIG_PCI_DIRECT)       += direct.o
 
 pci-y                          := fixup.o

diff --git a/arch/i386/pci/mmconfig.c b/arch/i386/pci/mmconfig.c
deleted file mode 100644 (file)
index 1bf5816..0000000
--- a/arch/i386/pci/mmconfig.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * Copyright (C) 2004 Matthew Wilcox <matthew@wil.cx>
- * Copyright (C) 2004 Intel Corp.
- *
- * This code is released under the GNU General Public License version 2.
- */
-
-/*
- * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
- */
-
-#include <linux/pci.h>
-#include <linux/init.h>
-#include <linux/acpi.h>
-#include <asm/e820.h>
-#include "pci.h"
-
-/* Assume systems with more busses have correct MCFG */
-#define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG))
-
-/* The base address of the last MMCONFIG device accessed */
-static u32 mmcfg_last_accessed_device;
-static int mmcfg_last_accessed_cpu;
-
-/*
- * Functions for accessing PCI configuration space with MMCONFIG accesses
- */
-static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn)
-{
-       struct acpi_mcfg_allocation *cfg;
-       int cfg_num;
-
-       if (seg == 0 && bus < PCI_MMCFG_MAX_CHECK_BUS &&
-           test_bit(PCI_SLOT(devfn) + 32*bus, pci_mmcfg_fallback_slots))
-               return 0;
-
-       for (cfg_num = 0; cfg_num < pci_mmcfg_config_num; cfg_num++) {
-               cfg = &pci_mmcfg_config[cfg_num];
-               if (cfg->pci_segment == seg &&
-                   (cfg->start_bus_number <= bus) &&
-                   (cfg->end_bus_number >= bus))
-                       return cfg->address;
-       }
-
-       /* Fall back to type 0 */
-       return 0;
-}
-
-/*
- * This is always called under pci_config_lock
- */
-static void pci_exp_set_dev_base(unsigned int base, int bus, int devfn)
-{
-       u32 dev_base = base | (bus << 20) | (devfn << 12);
-       int cpu = smp_processor_id();
-       if (dev_base != mmcfg_last_accessed_device ||
-           cpu != mmcfg_last_accessed_cpu) {
-               mmcfg_last_accessed_device = dev_base;
-               mmcfg_last_accessed_cpu = cpu;
-               set_fixmap_nocache(FIX_PCIE_MCFG, dev_base);
-       }
-}
-
-static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
-                         unsigned int devfn, int reg, int len, u32 *value)
-{
-       unsigned long flags;
-       u32 base;
-
-       if ((bus > 255) || (devfn > 255) || (reg > 4095)) {
-               *value = -1;
-               return -EINVAL;
-       }
-
-       base = get_base_addr(seg, bus, devfn);
-       if (!base)
-               return pci_conf1_read(seg,bus,devfn,reg,len,value);
-
-       spin_lock_irqsave(&pci_config_lock, flags);
-
-       pci_exp_set_dev_base(base, bus, devfn);
-
-       switch (len) {
-       case 1:
-               *value = mmio_config_readb(mmcfg_virt_addr + reg);
-               break;
-       case 2:
-               *value = mmio_config_readw(mmcfg_virt_addr + reg);
-               break;
-       case 4:
-               *value = mmio_config_readl(mmcfg_virt_addr + reg);
-               break;
-       }
-       spin_unlock_irqrestore(&pci_config_lock, flags);
-
-       return 0;
-}
-
-static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
-                          unsigned int devfn, int reg, int len, u32 value)
-{
-       unsigned long flags;
-       u32 base;
-
-       if ((bus > 255) || (devfn > 255) || (reg > 4095))
-               return -EINVAL;
-
-       base = get_base_addr(seg, bus, devfn);
-       if (!base)
-               return pci_conf1_write(seg,bus,devfn,reg,len,value);
-
-       spin_lock_irqsave(&pci_config_lock, flags);
-
-       pci_exp_set_dev_base(base, bus, devfn);
-
-       switch (len) {
-       case 1:
-               mmio_config_writeb(mmcfg_virt_addr + reg, value);
-               break;
-       case 2:
-               mmio_config_writew(mmcfg_virt_addr + reg, value);
-               break;
-       case 4:
-               mmio_config_writel(mmcfg_virt_addr + reg, value);
-               break;
-       }
-       spin_unlock_irqrestore(&pci_config_lock, flags);
-
-       return 0;
-}
-
-static struct pci_raw_ops pci_mmcfg = {
-       .read =         pci_mmcfg_read,
-       .write =        pci_mmcfg_write,
-};
-
-int __init pci_mmcfg_arch_reachable(unsigned int seg, unsigned int bus,
-                                   unsigned int devfn)
-{
-       return get_base_addr(seg, bus, devfn) != 0;
-}
-
-int __init pci_mmcfg_arch_init(void)
-{
-       printk(KERN_INFO "PCI: Using MMCONFIG\n");
-       raw_pci_ops = &pci_mmcfg;
-       return 1;
-}

diff --git a/arch/i386/pci/mmconfig_32.c b/arch/i386/pci/mmconfig_32.c
new file mode 100644 (file)
index 0000000..1bf5816
--- /dev/null
+++ b/arch/i386/pci/mmconfig_32.c
@@ -0,0 +1,148 @@
+/*
+ * Copyright (C) 2004 Matthew Wilcox <matthew@wil.cx>
+ * Copyright (C) 2004 Intel Corp.
+ *
+ * This code is released under the GNU General Public License version 2.
+ */
+
+/*
+ * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
+ */
+
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/acpi.h>
+#include <asm/e820.h>
+#include "pci.h"
+
+/* Assume systems with more busses have correct MCFG */
+#define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG))
+
+/* The base address of the last MMCONFIG device accessed */
+static u32 mmcfg_last_accessed_device;
+static int mmcfg_last_accessed_cpu;
+
+/*
+ * Functions for accessing PCI configuration space with MMCONFIG accesses
+ */
+static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn)
+{
+       struct acpi_mcfg_allocation *cfg;
+       int cfg_num;
+
+       if (seg == 0 && bus < PCI_MMCFG_MAX_CHECK_BUS &&
+           test_bit(PCI_SLOT(devfn) + 32*bus, pci_mmcfg_fallback_slots))
+               return 0;
+
+       for (cfg_num = 0; cfg_num < pci_mmcfg_config_num; cfg_num++) {
+               cfg = &pci_mmcfg_config[cfg_num];
+               if (cfg->pci_segment == seg &&
+                   (cfg->start_bus_number <= bus) &&
+                   (cfg->end_bus_number >= bus))
+                       return cfg->address;
+       }
+
+       /* Fall back to type 0 */
+       return 0;
+}
+
+/*
+ * This is always called under pci_config_lock
+ */
+static void pci_exp_set_dev_base(unsigned int base, int bus, int devfn)
+{
+       u32 dev_base = base | (bus << 20) | (devfn << 12);
+       int cpu = smp_processor_id();
+       if (dev_base != mmcfg_last_accessed_device ||
+           cpu != mmcfg_last_accessed_cpu) {
+               mmcfg_last_accessed_device = dev_base;
+               mmcfg_last_accessed_cpu = cpu;
+               set_fixmap_nocache(FIX_PCIE_MCFG, dev_base);
+       }
+}
+
+static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
+                         unsigned int devfn, int reg, int len, u32 *value)
+{
+       unsigned long flags;
+       u32 base;
+
+       if ((bus > 255) || (devfn > 255) || (reg > 4095)) {
+               *value = -1;
+               return -EINVAL;
+       }
+
+       base = get_base_addr(seg, bus, devfn);
+       if (!base)
+               return pci_conf1_read(seg,bus,devfn,reg,len,value);
+
+       spin_lock_irqsave(&pci_config_lock, flags);
+
+       pci_exp_set_dev_base(base, bus, devfn);
+
+       switch (len) {
+       case 1:
+               *value = mmio_config_readb(mmcfg_virt_addr + reg);
+               break;
+       case 2:
+               *value = mmio_config_readw(mmcfg_virt_addr + reg);
+               break;
+       case 4:
+               *value = mmio_config_readl(mmcfg_virt_addr + reg);
+               break;
+       }
+       spin_unlock_irqrestore(&pci_config_lock, flags);
+
+       return 0;
+}
+
+static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
+                          unsigned int devfn, int reg, int len, u32 value)
+{
+       unsigned long flags;
+       u32 base;
+
+       if ((bus > 255) || (devfn > 255) || (reg > 4095))
+               return -EINVAL;
+
+       base = get_base_addr(seg, bus, devfn);
+       if (!base)
+               return pci_conf1_write(seg,bus,devfn,reg,len,value);
+
+       spin_lock_irqsave(&pci_config_lock, flags);
+
+       pci_exp_set_dev_base(base, bus, devfn);
+
+       switch (len) {
+       case 1:
+               mmio_config_writeb(mmcfg_virt_addr + reg, value);
+               break;
+       case 2:
+               mmio_config_writew(mmcfg_virt_addr + reg, value);
+               break;
+       case 4:
+               mmio_config_writel(mmcfg_virt_addr + reg, value);
+               break;
+       }
+       spin_unlock_irqrestore(&pci_config_lock, flags);
+
+       return 0;
+}
+
+static struct pci_raw_ops pci_mmcfg = {
+       .read =         pci_mmcfg_read,
+       .write =        pci_mmcfg_write,
+};
+
+int __init pci_mmcfg_arch_reachable(unsigned int seg, unsigned int bus,
+                                   unsigned int devfn)
+{
+       return get_base_addr(seg, bus, devfn) != 0;
+}
+
+int __init pci_mmcfg_arch_init(void)
+{
+       printk(KERN_INFO "PCI: Using MMCONFIG\n");
+       raw_pci_ops = &pci_mmcfg;
+       return 1;
+}