mtd: fsmc_nand: Add BCH4 SW ECC support for SPEAr600

This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can
be used by boards equipped with a NAND chip that requires 4-bit ECC
strength. The SPEAr600 HW ECC only supports 1-bit ECC strength.

To enable SW BCH4, you need to specify this in your nand controller
DT node:

	nand-ecc-mode = "soft_bch";
	nand-ecc-strength = <4>;
	nand-ecc-step-size = <512>;

Tested on a custom SPEAr600 board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
[Brian: tweaked the comments a bit]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>

diff --git a/Documentation/devicetree/bindings/mtd/fsmc-nand.txt b/Documentation/devicetree/bindings/mtd/fsmc-nand.txt
index 5235cbc551b014eef7f1f0936f46298bae9ee3b4..32636eb77304ce497f55b743d4f37c6ed2fed780 100644 (file)
--- a/Documentation/devicetree/bindings/mtd/fsmc-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/fsmc-nand.txt
@@ -30,6 +30,12 @@ Optional properties:
                  command is asserted. Zero means one cycle, 255 means 256
                  cycles.
 - bank: default NAND bank to use (0-3 are valid, 0 is the default).
+- nand-ecc-mode      : see nand.txt
+- nand-ecc-strength  : see nand.txt
+- nand-ecc-step-size : see nand.txt
+
+Can support 1-bit HW ECC (default) or if stronger correction is required,
+software-based BCH.
 
 Example:
 

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 9e4fd0f59d3bb0554ec9006cd56de9841c2bf6ba..07af3dc7a4d2d9e82650af800a6aa4446d10a7a0 100644 (file)
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -1023,12 +1023,17 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
        nand->cmd_ctrl = fsmc_cmd_ctrl;
        nand->chip_delay = 30;
 
+       /*
+        * Setup default ECC mode. nand_dt_init() called from nand_scan_ident()
+        * can overwrite this value if the DT provides a different value.
+        */
        nand->ecc.mode = NAND_ECC_HW;
        nand->ecc.hwctl = fsmc_enable_hwecc;
        nand->ecc.size = 512;
        nand->options = pdata->options;
        nand->select_chip = fsmc_select_chip;
        nand->badblockbits = 7;
+       nand->flash_node = np;
 
        if (pdata->width == FSMC_NAND_BW16)
                nand->options |= NAND_BUSWIDTH_16;
@@ -1070,11 +1075,6 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
                nand->ecc.correct = fsmc_bch8_correct_data;
                nand->ecc.bytes = 13;
                nand->ecc.strength = 8;
-       } else {
-               nand->ecc.calculate = fsmc_read_hwecc_ecc1;
-               nand->ecc.correct = nand_correct_data;
-               nand->ecc.bytes = 3;
-               nand->ecc.strength = 1;
        }
 
        /*
@@ -1115,22 +1115,47 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
                        goto err_probe;
                }
        } else {
-               switch (host->mtd.oobsize) {
-               case 16:
-                       nand->ecc.layout = &fsmc_ecc1_16_layout;
+               switch (nand->ecc.mode) {
+               case NAND_ECC_HW:
+                       dev_info(&pdev->dev, "Using 1-bit HW ECC scheme\n");
+                       nand->ecc.calculate = fsmc_read_hwecc_ecc1;
+                       nand->ecc.correct = nand_correct_data;
+                       nand->ecc.bytes = 3;
+                       nand->ecc.strength = 1;
                        break;
-               case 64:
-                       nand->ecc.layout = &fsmc_ecc1_64_layout;
-                       break;
-               case 128:
-                       nand->ecc.layout = &fsmc_ecc1_128_layout;
+
+               case NAND_ECC_SOFT_BCH:
+                       dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
                        break;
+
                default:
-                       dev_warn(&pdev->dev, "No oob scheme defined for oobsize %d\n",
-                                mtd->oobsize);
-                       ret = -EINVAL;
+                       dev_err(&pdev->dev, "Unsupported ECC mode!\n");
                        goto err_probe;
                }
+
+               /*
+                * Don't set layout for BCH4 SW ECC. This will be
+                * generated later in nand_bch_init() later.
+                */
+               if (nand->ecc.mode != NAND_ECC_SOFT_BCH) {
+                       switch (host->mtd.oobsize) {
+                       case 16:
+                               nand->ecc.layout = &fsmc_ecc1_16_layout;
+                               break;
+                       case 64:
+                               nand->ecc.layout = &fsmc_ecc1_64_layout;
+                               break;
+                       case 128:
+                               nand->ecc.layout = &fsmc_ecc1_128_layout;
+                               break;
+                       default:
+                               dev_warn(&pdev->dev,
+                                        "No oob scheme defined for oobsize %d\n",
+                                        mtd->oobsize);
+                               ret = -EINVAL;
+                               goto err_probe;
+                       }
+               }
        }
 
        /* Second stage of scan to fill MTD data-structures */