MIPS: Octeon: Add hardware RNG platform device.

Add a platform device for the Octeon Random Number Generator (RNG).

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index da559249cc2fae44161c5322ce7cfd61b3cac328..468a1209833f690a004607c2ff06e51bf2fe4b08 100644 (file)
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -33,6 +33,7 @@
 #include <asm/time.h>
 
 #include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-rnm-defs.h>
 
 #ifdef CONFIG_CAVIUM_DECODE_RSL
 extern void cvmx_interrupt_rsl_decode(void);
@@ -926,3 +927,45 @@ out:
        return ret;
 }
 device_initcall(octeon_cf_device_init);
+
+/* Octeon Random Number Generator.  */
+static int __init octeon_rng_device_init(void)
+{
+       struct platform_device *pd;
+       int ret = 0;
+
+       struct resource rng_resources[] = {
+               {
+                       .flags  = IORESOURCE_MEM,
+                       .start  = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
+                       .end    = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
+               }, {
+                       .flags  = IORESOURCE_MEM,
+                       .start  = cvmx_build_io_address(8, 0),
+                       .end    = cvmx_build_io_address(8, 0) + 0x7
+               }
+       };
+
+       pd = platform_device_alloc("octeon_rng", -1);
+       if (!pd) {
+               ret = -ENOMEM;
+               goto out;
+       }
+
+       ret = platform_device_add_resources(pd, rng_resources,
+                                           ARRAY_SIZE(rng_resources));
+       if (ret)
+               goto fail;
+
+       ret = platform_device_add(pd);
+       if (ret)
+               goto fail;
+
+       return ret;
+fail:
+       platform_device_put(pd);
+
+out:
+       return ret;
+}
+device_initcall(octeon_rng_device_init);

diff --git a/arch/mips/include/asm/octeon/cvmx-rnm-defs.h b/arch/mips/include/asm/octeon/cvmx-rnm-defs.h
new file mode 100644 (file)
index 0000000..4586958
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-rnm-defs.h
@@ -0,0 +1,88 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_RNM_DEFS_H__
+#define __CVMX_RNM_DEFS_H__
+
+#include <linux/types.h>
+
+#define CVMX_RNM_BIST_STATUS \
+        CVMX_ADD_IO_SEG(0x0001180040000008ull)
+#define CVMX_RNM_CTL_STATUS \
+        CVMX_ADD_IO_SEG(0x0001180040000000ull)
+
+union cvmx_rnm_bist_status {
+       uint64_t u64;
+       struct cvmx_rnm_bist_status_s {
+               uint64_t reserved_2_63:62;
+               uint64_t rrc:1;
+               uint64_t mem:1;
+       } s;
+       struct cvmx_rnm_bist_status_s cn30xx;
+       struct cvmx_rnm_bist_status_s cn31xx;
+       struct cvmx_rnm_bist_status_s cn38xx;
+       struct cvmx_rnm_bist_status_s cn38xxp2;
+       struct cvmx_rnm_bist_status_s cn50xx;
+       struct cvmx_rnm_bist_status_s cn52xx;
+       struct cvmx_rnm_bist_status_s cn52xxp1;
+       struct cvmx_rnm_bist_status_s cn56xx;
+       struct cvmx_rnm_bist_status_s cn56xxp1;
+       struct cvmx_rnm_bist_status_s cn58xx;
+       struct cvmx_rnm_bist_status_s cn58xxp1;
+};
+
+union cvmx_rnm_ctl_status {
+       uint64_t u64;
+       struct cvmx_rnm_ctl_status_s {
+               uint64_t reserved_9_63:55;
+               uint64_t ent_sel:4;
+               uint64_t exp_ent:1;
+               uint64_t rng_rst:1;
+               uint64_t rnm_rst:1;
+               uint64_t rng_en:1;
+               uint64_t ent_en:1;
+       } s;
+       struct cvmx_rnm_ctl_status_cn30xx {
+               uint64_t reserved_4_63:60;
+               uint64_t rng_rst:1;
+               uint64_t rnm_rst:1;
+               uint64_t rng_en:1;
+               uint64_t ent_en:1;
+       } cn30xx;
+       struct cvmx_rnm_ctl_status_cn30xx cn31xx;
+       struct cvmx_rnm_ctl_status_cn30xx cn38xx;
+       struct cvmx_rnm_ctl_status_cn30xx cn38xxp2;
+       struct cvmx_rnm_ctl_status_s cn50xx;
+       struct cvmx_rnm_ctl_status_s cn52xx;
+       struct cvmx_rnm_ctl_status_s cn52xxp1;
+       struct cvmx_rnm_ctl_status_s cn56xx;
+       struct cvmx_rnm_ctl_status_s cn56xxp1;
+       struct cvmx_rnm_ctl_status_s cn58xx;
+       struct cvmx_rnm_ctl_status_s cn58xxp1;
+};
+
+#endif