arm64: dts: exynos: Fix FSYS CMU parent clocks in Exynos5433 SoC

This patch corrects FSYS CMU parent clocks specified in clock controller
node to let improved Exynos5433 clocks driver to control proper clocks
on FSYS<->TOP CMU boundary.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 0a70fadfada8295af22d7448dba4519432c4791c..f5dab754d61fa90e3f23caf90e793c73eda90039 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -312,7 +312,7 @@
 
                        clock-names = "oscclk",
                                "sclk_ufs_mphy",
-                               "div_aclk_fsys_200",
+                               "aclk_fsys_200",
                                "sclk_pcie_100_fsys",
                                "sclk_ufsunipro_fsys",
                                "sclk_mmc2_fsys",
@@ -322,7 +322,7 @@
                                "sclk_usbdrd30_fsys";
                        clocks = <&xxti>,
                                <&cmu_cpif CLK_SCLK_UFS_MPHY>,
-                               <&cmu_top CLK_DIV_ACLK_FSYS_200>,
+                               <&cmu_top CLK_ACLK_FSYS_200>,
                                <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
                                <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
                                <&cmu_top CLK_SCLK_MMC2_FSYS>,