ARM: 7532/1: decompressor: reset SCTLR.TRE for VMSA ARMv7 cores
authorMatthew Leach <matthew.leach@arm.com>
Tue, 11 Sep 2012 16:56:57 +0000 (17:56 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Sat, 15 Sep 2012 23:16:16 +0000 (00:16 +0100)
This patch zeroes the SCTLR.TRE bit prior to setting the mapping as
cacheable for ARMv7 cores in the decompressor, ensuring that the
memory region attributes are obtained from the C and B bits, not from
the page tables.

Cc: Nicolas Pitre <nico@fluxnic.net>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Matthew Leach <matthew.leach@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/boot/compressed/head.S

index 81769c1341fa7d071c105d8dcb6b2fe0d9b8110c..bc67cbff39448ff84a3f0c14cd22876975ee1965 100644 (file)
@@ -653,6 +653,7 @@ __armv7_mmu_cache_on:
                mcrne   p15, 0, r0, c8, c7, 0   @ flush I,D TLBs
 #endif
                mrc     p15, 0, r0, c1, c0, 0   @ read control reg
+               bic     r0, r0, #1 << 28        @ clear SCTLR.TRE
                orr     r0, r0, #0x5000         @ I-cache enable, RR cache replacement
                orr     r0, r0, #0x003c         @ write buffer
 #ifdef CONFIG_MMU