*/
struct idi_48_gpio {
struct gpio_chip chip;
- spinlock_t lock;
+ raw_spinlock_t lock;
spinlock_t ack_lock;
unsigned char irq_mask[6];
unsigned base;
if (!idi48gpio->irq_mask[boundary]) {
idi48gpio->cos_enb &= ~BIT(boundary);
- spin_lock_irqsave(&idi48gpio->lock, flags);
+ raw_spin_lock_irqsave(&idi48gpio->lock, flags);
outb(idi48gpio->cos_enb, idi48gpio->base + 7);
- spin_unlock_irqrestore(&idi48gpio->lock, flags);
+ raw_spin_unlock_irqrestore(&idi48gpio->lock,
+ flags);
}
return;
if (!prev_irq_mask) {
idi48gpio->cos_enb |= BIT(boundary);
- spin_lock_irqsave(&idi48gpio->lock, flags);
+ raw_spin_lock_irqsave(&idi48gpio->lock, flags);
outb(idi48gpio->cos_enb, idi48gpio->base + 7);
- spin_unlock_irqrestore(&idi48gpio->lock, flags);
+ raw_spin_unlock_irqrestore(&idi48gpio->lock,
+ flags);
}
return;
spin_lock(&idi48gpio->ack_lock);
- spin_lock(&idi48gpio->lock);
+ raw_spin_lock(&idi48gpio->lock);
cos_status = inb(idi48gpio->base + 7);
- spin_unlock(&idi48gpio->lock);
+ raw_spin_unlock(&idi48gpio->lock);
/* IRQ Status (bit 6) is active low (0 = IRQ generated by device) */
if (cos_status & BIT(6)) {
idi48gpio->chip.get = idi_48_gpio_get;
idi48gpio->base = base[id];
- spin_lock_init(&idi48gpio->lock);
+ raw_spin_lock_init(&idi48gpio->lock);
spin_lock_init(&idi48gpio->ack_lock);
err = devm_gpiochip_add_data(dev, &idi48gpio->chip, idi48gpio);