clk: meson-gxbb: Add GP0 PLL init parameters

Tha Amlogic GXBB SoC GP0 PLL needs some vendor provided parameters to be
initializated in the the GP0 control registers before configuring the rate
with the rate table provided parameters.

GXBB GP0 PLL tweaks are also selected to respect the vendor init procedure.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1490178747-14837-3-git-send-email-narmstrong@baylibre.com

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index d07dc2255fafa6c90dfb4679cf438ad65854ba2d..db95038e50c64d9c338d4f279f7e2cac5c1270dd 100644 (file)
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -352,6 +352,13 @@ static struct meson_clk_pll gxbb_sys_pll = {
        },
 };
 
+struct pll_params_table gxbb_gp0_params_table[] = {
+       PLL_PARAM(HHI_GP0_PLL_CNTL, 0x6a000228),
+       PLL_PARAM(HHI_GP0_PLL_CNTL2, 0x69c80000),
+       PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a5590c4),
+       PLL_PARAM(HHI_GP0_PLL_CNTL4, 0x0000500d),
+};
+
 static struct meson_clk_pll gxbb_gp0_pll = {
        .m = {
                .reg_off = HHI_GP0_PLL_CNTL,
@@ -368,6 +375,12 @@ static struct meson_clk_pll gxbb_gp0_pll = {
                .shift   = 16,
                .width   = 2,
        },
+       .params = {
+               .params_table = gxbb_gp0_params_table,
+               .params_count = ARRAY_SIZE(gxbb_gp0_params_table),
+               .no_init_reset = true,
+               .clear_reset_for_lock = true,
+       },
        .rate_table = gp0_pll_rate_table,
        .rate_count = ARRAY_SIZE(gp0_pll_rate_table),
        .lock = &clk_lock,