x86/cpu: Restore AMD's DE_CFG MSR after resume

commit 2632daebafd04746b4b96c2f26a6021bc38f6209 upstream.

DE_CFG contains the LFENCE serializing bit, restore it on resume too.
This is relevant to older families due to the way how they do S3.

Unify and correct naming while at it.

Fixes: e4d0e84e4907 ("x86/cpu/AMD: Make LFENCE a serializing instruction")
Reported-by: Andrew Cooper <Andrew.Cooper3@citrix.com>
Reported-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: <stable@kernel.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 5131146e1bd8622c6adc7846ba5e2dc0d945214c..aafd1747cae646e19853c449c0c830d7152fa95c 100644 (file)
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -364,6 +364,11 @@
 #define MSR_AMD64_OSVW_STATUS          0xc0010141
 #define MSR_AMD64_LS_CFG               0xc0011020
 #define MSR_AMD64_DC_CFG               0xc0011022
+
+#define MSR_AMD64_DE_CFG               0xc0011029
+#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT   1
+#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE      BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)
+
 #define MSR_AMD64_BU_CFG2              0xc001102a
 #define MSR_AMD64_IBSFETCHCTL          0xc0011030
 #define MSR_AMD64_IBSFETCHLINAD                0xc0011031
@@ -414,9 +419,6 @@
 #define FAM10H_MMIO_CONF_BASE_MASK     0xfffffffULL
 #define FAM10H_MMIO_CONF_BASE_SHIFT    20
 #define MSR_FAM10H_NODE_ID             0xc001100c
-#define MSR_F10H_DECFG                 0xc0011029
-#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT    1
-#define MSR_F10H_DECFG_LFENCE_SERIALIZE                BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT)
 
 /* K8 MSRs */
 #define MSR_K8_TOP_MEM1                        0xc001001a

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 9428b54fff664776cb3b45c5a0fd6d894f073e59..13915fdbb4c904ee52f45ae72b525e4e948e6863 100644 (file)
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -735,8 +735,6 @@ static void init_amd_gh(struct cpuinfo_x86 *c)
                set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
 }
 
-#define MSR_AMD64_DE_CFG       0xC0011029
-
 static void init_amd_ln(struct cpuinfo_x86 *c)
 {
        /*
@@ -898,16 +896,16 @@ static void init_amd(struct cpuinfo_x86 *c)
                 * msr_set_bit() uses the safe accessors, too, even if the MSR
                 * is not present.
                 */
-               msr_set_bit(MSR_F10H_DECFG,
-                           MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
+               msr_set_bit(MSR_AMD64_DE_CFG,
+                           MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT);
 
                /*
                 * Verify that the MSR write was successful (could be running
                 * under a hypervisor) and only then assume that LFENCE is
                 * serializing.
                 */
-               ret = rdmsrl_safe(MSR_F10H_DECFG, &val);
-               if (!ret && (val & MSR_F10H_DECFG_LFENCE_SERIALIZE)) {
+               ret = rdmsrl_safe(MSR_AMD64_DE_CFG, &val);
+               if (!ret && (val & MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)) {
                        /* A serializing LFENCE stops RDTSC speculation */
                        set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
                } else {

diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index c8e18144ecf2f7b2ba44bd4f033fabf2747ebe44..1556c55a0909b6076372f23a309a7a2b31c610aa 100644 (file)
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -3528,9 +3528,9 @@ static int svm_get_msr_feature(struct kvm_msr_entry *msr)
        msr->data = 0;
 
        switch (msr->index) {
-       case MSR_F10H_DECFG:
-               if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
-                       msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
+       case MSR_AMD64_DE_CFG:
+               if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC))
+                       msr->data |= MSR_AMD64_DE_CFG_LFENCE_SERIALIZE;
                break;
        default:
                return 1;
@@ -3638,7 +3638,7 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
                        msr_info->data = 0x1E;
                }
                break;
-       case MSR_F10H_DECFG:
+       case MSR_AMD64_DE_CFG:
                msr_info->data = svm->msr_decfg;
                break;
        default:
@@ -3829,7 +3829,7 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
        case MSR_VM_IGNNE:
                vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
                break;
-       case MSR_F10H_DECFG: {
+       case MSR_AMD64_DE_CFG: {
                struct kvm_msr_entry msr_entry;
 
                msr_entry.index = msr->index;

diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 78c1838b9fffdb7c7ab3513bc88d6c731730d208..007dc3298f88e059b4c296012aa065805efea06c 100644 (file)
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1026,7 +1026,7 @@ static unsigned num_emulated_msrs;
  * can be used by a hypervisor to validate requested CPU features.
  */
 static u32 msr_based_features[] = {
-       MSR_F10H_DECFG,
+       MSR_AMD64_DE_CFG,
        MSR_IA32_UCODE_REV,
        MSR_IA32_ARCH_CAPABILITIES,
 };

diff --git a/arch/x86/power/cpu.c b/arch/x86/power/cpu.c
index a1fbf18eed5a80571166c5de7524bf9d63656243..4c073926ab931677f017b4048ba8134dde67710d 100644 (file)
--- a/arch/x86/power/cpu.c
+++ b/arch/x86/power/cpu.c
@@ -526,6 +526,7 @@ static void pm_save_spec_msr(void)
                MSR_TSX_FORCE_ABORT,
                MSR_IA32_MCU_OPT_CTRL,
                MSR_AMD64_LS_CFG,
+               MSR_AMD64_DE_CFG,
        };
 
        msr_build_context(spec_msr_id, ARRAY_SIZE(spec_msr_id));