x86: coding style fixes to arch/x86/kernel/cpu/mtrr/state.c

Before:
   total: 6 errors, 5 warnings, 80 lines checked
After:
   total: 0 errors, 4 warnings, 82 lines checked

No code changed:

arch/x86/kernel/cpu/mtrr/state.o:

   text	   data	    bss	    dec	    hex	filename
    313	      0	      4	    317	    13d	state.o.before
    313	      0	      4	    317	    13d	state.o.after

md5:
   a0fbd61096205f9180f0bf45ed386d61  state.o.before.asm
   a0fbd61096205f9180f0bf45ed386d61  state.o.after.asm

Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

diff --git a/arch/x86/kernel/cpu/mtrr/state.c b/arch/x86/kernel/cpu/mtrr/state.c
index 9f8ba923d1c973c138f0fad5f5b9a5d31063e0a6..7f7e2753685bce875ccd6dca8903474e366456cc 100644 (file)
--- a/arch/x86/kernel/cpu/mtrr/state.c
+++ b/arch/x86/kernel/cpu/mtrr/state.c
@@ -19,13 +19,15 @@ void set_mtrr_prepare_save(struct set_mtrr_context *ctxt)
        if (use_intel() || is_cpu(CYRIX)) {
 
                /*  Save value of CR4 and clear Page Global Enable (bit 7)  */
-               if ( cpu_has_pge ) {
+               if (cpu_has_pge) {
                        ctxt->cr4val = read_cr4();
                        write_cr4(ctxt->cr4val & ~X86_CR4_PGE);
                }
 
-               /*  Disable and flush caches. Note that wbinvd flushes the TLBs as
-                   a side-effect  */
+               /*
+                * Disable and flush caches. Note that wbinvd flushes the TLBs
+                * as a side-effect
+                */
                cr0 = read_cr0() | X86_CR0_CD;
                wbinvd();
                write_cr0(cr0);
@@ -42,7 +44,7 @@ void set_mtrr_prepare_save(struct set_mtrr_context *ctxt)
 
 void set_mtrr_cache_disable(struct set_mtrr_context *ctxt)
 {
-       if (use_intel()) 
+       if (use_intel())
                /*  Disable MTRRs, and set the default type to uncached  */
                mtrr_wrmsr(MTRRdefType_MSR, ctxt->deftype_lo & 0xf300UL,
                      ctxt->deftype_hi);
@@ -66,12 +68,12 @@ void set_mtrr_done(struct set_mtrr_context *ctxt)
                else
                        /* Cyrix ARRs - everything else was excluded at the top */
                        setCx86(CX86_CCR3, ctxt->ccr3);
-               
+
                /*  Enable caches  */
                write_cr0(read_cr0() & 0xbfffffff);
 
                /*  Restore value of CR4  */
-               if ( cpu_has_pge )
+               if (cpu_has_pge)
                        write_cr4(ctxt->cr4val);
        }
        /*  Re-enable interrupts locally (if enabled previously)  */