staging: comedi: s626: add missing bits for 'CRB' register

There are some bits in the 'CRB' register not defined in "s626.h".
Three of these are read-only bits that overlay the write-only interrupt
control bits.  Another missing bit controls whether counter 'B' is
cleared when counter 'A' overflows.  Add the missing bit definitions for
completeness.

Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Reviewed-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/staging/comedi/drivers/s626.h b/drivers/staging/comedi/drivers/s626.h
index bdecdfbe6099d8a7f0227da76a882f3230e561ee..7f38de5f07f5cb9b3e1914434e758961ff53c043 100644 (file)
--- a/drivers/staging/comedi/drivers/s626.h
+++ b/drivers/staging/comedi/drivers/s626.h
@@ -544,13 +544,17 @@
 #define S626_CRABIT_CNTSRC_A    0      /* A counter source. */
 
 /* Bit field positions in CRB: */
-#define S626_CRBBIT_INTRESETCMD        15      /* Interrupt reset command. */
-#define S626_CRBBIT_INTRESET_B 14      /* B interrupt reset enable. */
-#define S626_CRBBIT_INTRESET_A 13      /* A interrupt reset enable. */
+#define S626_CRBBIT_INTRESETCMD        15      /* (w) Interrupt reset command. */
+#define S626_CRBBIT_CNTDIR_B   15      /* (r) B counter direction. */
+#define S626_CRBBIT_INTRESET_B 14      /* (w) B interrupt reset enable. */
+#define S626_CRBBIT_OVERDO_A   14      /* (r) A overflow routed to dig. out. */
+#define S626_CRBBIT_INTRESET_A 13      /* (w) A interrupt reset enable. */
+#define S626_CRBBIT_OVERDO_B   13      /* (r) B overflow routed to dig. out. */
 #define S626_CRBBIT_CLKENAB_A  12      /* A clock enable. */
 #define S626_CRBBIT_INTSRC_B   10      /* B interrupt source. */
 #define S626_CRBBIT_LATCHSRC    8      /* A/B latch source. */
 #define S626_CRBBIT_LOADSRC_B   6      /* B preload trigger. */
+#define S626_CRBBIT_CLEAR_B     7      /* B cleared when A overflows. */
 #define S626_CRBBIT_CLKMULT_B   3      /* B clock multiplier. */
 #define S626_CRBBIT_CLKENAB_B   2      /* B clock enable. */
 #define S626_CRBBIT_INDXPOL_B   1      /* B index polarity. */
@@ -569,12 +573,16 @@
 #define S626_CRAMSK_CNTSRC_A   (3 << S626_CRABIT_CNTSRC_A)
 
 #define S626_CRBMSK_INTRESETCMD        (1 << S626_CRBBIT_INTRESETCMD)
+#define S626_CRBMSK_CNTDIR_B   (1 << S626_CRBBIT_CNTDIR_B)
 #define S626_CRBMSK_INTRESET_B (1 << S626_CRBBIT_INTRESET_B)
+#define S626_CRBMSK_OVERDO_A   (1 << S626_CRBBIT_OVERDO_A)
 #define S626_CRBMSK_INTRESET_A (1 << S626_CRBBIT_INTRESET_A)
+#define S626_CRBMSK_OVERDO_B   (1 << S626_CRBBIT_OVERDO_B)
 #define S626_CRBMSK_CLKENAB_A  (1 << S626_CRBBIT_CLKENAB_A)
 #define S626_CRBMSK_INTSRC_B   (3 << S626_CRBBIT_INTSRC_B)
 #define S626_CRBMSK_LATCHSRC   (3 << S626_CRBBIT_LATCHSRC)
 #define S626_CRBMSK_LOADSRC_B  (3 << S626_CRBBIT_LOADSRC_B)
+#define S626_CRBMSK_CLEAR_B    (1 << S626_CRBBIT_CLEAR_B)
 #define S626_CRBMSK_CLKMULT_B  (3 << S626_CRBBIT_CLKMULT_B)
 #define S626_CRBMSK_CLKENAB_B  (1 << S626_CRBBIT_CLKENAB_B)
 #define S626_CRBMSK_INDXPOL_B  (1 << S626_CRBBIT_INDXPOL_B)