spi: davinci: change the lower limit of pre-scale divider to 1

SPI hardware spec for Keystone specify a lower value of 0 for pre-scale
divider which determine what max value of spi clock (spi-max-frequency)
the device can support. This translates to a clock divider of 2. So fix
the lower limit value used for the boundary check in
davinci_spi_get_prescale() function to 1 so that a maximum of spi device
clock rate / 2 is possible to be set for spi-max-frequency.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c
index 5e991065f5b0166437aceb3f313ed7bd65f9bcbd..987afebea09379507f2c8505e7f4c14acbde079c 100644 (file)
--- a/drivers/spi/spi-davinci.c
+++ b/drivers/spi/spi-davinci.c
@@ -265,7 +265,7 @@ static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,
 
        ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz);
 
-       if (ret < 3 || ret > 256)
+       if (ret < 1 || ret > 256)
                return -EINVAL;
 
        return ret - 1;