arm64: dts: exynos: TM2 - add support for JPEG codec device

This patch adds device nodes for JPEG codec device to Exynos5433 SoC dtsi
and proper initial clock configuration to TM2 dts.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
index 8eb59adc2bc486e840b4e7f5c02e33d2d143d34f..6f506dd117148f4be6b58308a1e8ba3489b477f4 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
@@ -196,6 +196,17 @@
                                 <&cmu_top CLK_ACLK_GSCL_333>;
 };
 
+&cmu_mscl {
+       assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>,
+                         <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
+                         <&cmu_mscl CLK_MOUT_SCLK_JPEG>,
+                         <&cmu_top CLK_MOUT_SCLK_JPEG_A>;
+       assigned-clock-parents = <&cmu_top CLK_ACLK_MSCL_400>,
+                                <&cmu_top CLK_SCLK_JPEG_MSCL>,
+                                <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
+                                <&cmu_top CLK_MOUT_BUS_PLL_USER>;
+};
+
 &cpu0 {
        cpu-supply = <&buck3_reg>;
 };

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 945b2502a4caed3e5967475a42ac888fd73dff6e..1d47480f4104c09db7001d7c3ccc0e206b842ab0 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -844,6 +844,18 @@
                        iommus = <&sysmmu_gscl2>;
                };
 
+               jpeg: codec@15020000 {
+                       compatible = "samsung,exynos5433-jpeg";
+                       reg = <0x15020000 0x10000>;
+                       interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-names = "pclk", "aclk", "aclk_xiu", "sclk";
+                       clocks = <&cmu_mscl CLK_PCLK_JPEG>,
+                                <&cmu_mscl CLK_ACLK_JPEG>,
+                                <&cmu_mscl CLK_ACLK_XIU_MSCLX>,
+                                <&cmu_mscl CLK_SCLK_JPEG>;
+                       iommus = <&sysmmu_jpeg>;
+               };
+
                sysmmu_decon0x: sysmmu@0x13a00000 {
                        compatible = "samsung,exynos-sysmmu";
                        reg = <0x13a00000 0x1000>;
@@ -894,6 +906,16 @@
                        #iommu-cells = <0>;
                };
 
+               sysmmu_jpeg: sysmmu@0x15060000 {
+                       compatible = "samsung,exynos-sysmmu";
+                       reg = <0x15060000 0x1000>;
+                       interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-names = "pclk", "aclk";
+                       clocks = <&cmu_mscl CLK_PCLK_SMMU_JPEG>,
+                                <&cmu_mscl CLK_ACLK_SMMU_JPEG>;
+                       #iommu-cells = <0>;
+               };
+
                serial_0: serial@14c10000 {
                        compatible = "samsung,exynos5433-uart";
                        reg = <0x14c10000 0x100>;