ARM: imx: mem bit must be cleared before entering DSM mode

According to hardware design, mem bit must be clear before
entering DSM mode, as ARM core will be power gated in DSM mode.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>

diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 50ee9c23974c2021954edb9804ab4ff4a3c8b562..13a6e1f8e11e8325f47cddba63163d1e53db8c4a 100644 (file)
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -116,7 +116,7 @@ void imx_anatop_init(void);
 void imx_anatop_pre_suspend(void);
 void imx_anatop_post_resume(void);
 int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
-void imx6q_set_int_mem_clk_lpm(void);
+void imx6q_set_int_mem_clk_lpm(bool enable);
 void imx6sl_set_wait_clk(bool enter);
 
 void imx_cpu_die(unsigned int cpu);

diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c
index fc0bb1eafee3159111beabd56f414b4bbfe4a5cf..10844d3bb926bcb5edec39e719c02355360d79e4 100644 (file)
--- a/arch/arm/mach-imx/cpuidle-imx6q.c
+++ b/arch/arm/mach-imx/cpuidle-imx6q.c
@@ -71,7 +71,7 @@ int __init imx6q_cpuidle_init(void)
                imx_scu_standby_enable();
 
        /* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */
-       imx6q_set_int_mem_clk_lpm();
+       imx6q_set_int_mem_clk_lpm(true);
 
        return cpuidle_register(&imx6q_cpuidle_driver, NULL);
 }

diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
index 331055b59218b76ff3c9c72c2928a6d3856a39ae..b3c770d0cc3f823d9e008b12a2e0e233357e0e18 100644 (file)
--- a/arch/arm/mach-imx/pm-imx6.c
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -199,11 +199,13 @@ struct imx6_cpu_pm_info {
        u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */
 } __aligned(8);
 
-void imx6q_set_int_mem_clk_lpm(void)
+void imx6q_set_int_mem_clk_lpm(bool enable)
 {
        u32 val = readl_relaxed(ccm_base + CGPR);
 
-       val |= BM_CGPR_INT_MEM_CLK_LPM;
+       val &= ~BM_CGPR_INT_MEM_CLK_LPM;
+       if (enable)
+               val |= BM_CGPR_INT_MEM_CLK_LPM;
        writel_relaxed(val, ccm_base + CGPR);
 }
 
@@ -334,6 +336,7 @@ static int imx6q_pm_enter(suspend_state_t state)
        switch (state) {
        case PM_SUSPEND_MEM:
                imx6q_set_lpm(STOP_POWER_OFF);
+               imx6q_set_int_mem_clk_lpm(false);
                imx6q_enable_wb(true);
                /*
                 * For suspend into ocram, asm code already take care of
@@ -352,6 +355,7 @@ static int imx6q_pm_enter(suspend_state_t state)
                imx_gpc_post_resume();
                imx6q_enable_rbc(false);
                imx6q_enable_wb(false);
+               imx6q_set_int_mem_clk_lpm(true);
                imx6q_set_lpm(WAIT_CLOCKED);
                break;
        default: