ath9k: fix few register offsets for AR9330
authorGabor Juhos <juhosg@openwrt.org>
Tue, 21 Jun 2011 09:23:48 +0000 (11:23 +0200)
committerJohn W. Linville <linville@tuxdriver.com>
Wed, 22 Jun 2011 20:09:56 +0000 (16:09 -0400)
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath/ath9k/ar9003_phy.h

index d259278fcc840fbccdb5ab00e6f97181bfa25b42..9eb3aa211688942de42ed07d6ccd0576b17e0772 100644 (file)
 #define AR_PHY_65NM_CH2_RXTX1       0x16900
 #define AR_PHY_65NM_CH2_RXTX2       0x16904
 
-#define AR_CH0_TOP2 (AR_SREV_9485(ah) ? 0x00016284 : 0x0001628c)
+#define AR_CH0_TOP2            (AR_SREV_9300(ah) ? 0x1628c : 0x16284)
 #define AR_CH0_TOP2_XPABIASLVL         0xf000
 #define AR_CH0_TOP2_XPABIASLVL_S       12
 
-#define AR_CH0_XTAL            (AR_SREV_9485(ah) ? 0x16290 : 0x16294)
+#define AR_CH0_XTAL            (AR_SREV_9300(ah) ? 0x16294 : 0x16290)
 #define AR_CH0_XTAL_CAPINDAC   0x7f000000
 #define AR_CH0_XTAL_CAPINDAC_S 24
 #define AR_CH0_XTAL_CAPOUTDAC  0x00fe0000