watchdog: dw_wdt: initialise TOP_INIT in dw_wdt_set_top()

The TOP_INIT, ie bit 4-7 of the WDOG_TIMEOUT_RANGE_REG_OFFSET register
may be zero, so the timeout period may be very short after initialization
is done, thus the system may be reset soon after enabling. We fix this
problem by also initialising the TOP_INIT when setting TOP in function
dw_wdt_set_top().

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>

diff --git a/drivers/watchdog/dw_wdt.c b/drivers/watchdog/dw_wdt.c
index 9f210299de2491cd9c9ed654268e0bda991a6c5e..449c885233644e9d5a8ea07fbd36f5982ecad81b 100644 (file)
--- a/drivers/watchdog/dw_wdt.c
+++ b/drivers/watchdog/dw_wdt.c
@@ -40,6 +40,7 @@
 #define WDOG_CONTROL_REG_OFFSET                    0x00
 #define WDOG_CONTROL_REG_WDT_EN_MASK       0x01
 #define WDOG_TIMEOUT_RANGE_REG_OFFSET      0x04
+#define WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT    4
 #define WDOG_CURRENT_COUNT_REG_OFFSET      0x08
 #define WDOG_COUNTER_RESTART_REG_OFFSET     0x0c
 #define WDOG_COUNTER_RESTART_KICK_VALUE            0x76
@@ -106,7 +107,8 @@ static int dw_wdt_set_top(unsigned top_s)
                }
 
        /* Set the new value in the watchdog. */
-       writel(top_val, dw_wdt.regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
+       writel(top_val | top_val << WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT,
+               dw_wdt.regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
 
        dw_wdt_set_next_heartbeat();