drm/amdgpu: export gfx config double offchip LDS buffers (v3)
authorJunwei Zhang <Jerry.Zhang@amd.com>
Fri, 17 Feb 2017 03:05:49 +0000 (11:05 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 30 Mar 2017 03:53:17 +0000 (23:53 -0400)
v2: move the config struct to drm_amdgpu_info_device
v3: move the config feature to amdgpu_gca_config

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
include/uapi/drm/amdgpu_drm.h

index 80ab8516db7cba4207a90ac37e8e986064f92e5e..ef72f52a6a207bca77738fc0087e033affad27a3 100644 (file)
@@ -845,6 +845,9 @@ struct amdgpu_gca_config {
        uint32_t macrotile_mode_array[16];
 
        struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
+
+       /* gfx configure feature */
+       uint32_t double_offchip_lds_buf;
 };
 
 struct amdgpu_cu_info {
index 027692bf8457dbfaf478ce829d8380d11b22a2ad..096386515f2f122c1ad06534035cdfa56446ae63 100644 (file)
@@ -528,6 +528,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
                dev_info.vram_type = adev->mc.vram_type;
                dev_info.vram_bit_width = adev->mc.vram_width;
                dev_info.vce_harvest_config = adev->vce.harvest_config;
+               dev_info.gc_double_offchip_lds_buf =
+                       adev->gfx.config.double_offchip_lds_buf;
 
                return copy_to_user(out, &dev_info,
                                    min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
index 2086e7e68de447630bf099e1722805fbe585c06c..e78433799a6d8d7e6798d9a629e8799f383457c5 100644 (file)
@@ -1579,6 +1579,11 @@ static void gfx_v6_0_setup_spi(struct amdgpu_device *adev)
        mutex_unlock(&adev->grbm_idx_mutex);
 }
 
+static void gfx_v6_0_config_init(struct amdgpu_device *adev)
+{
+       adev->gfx.config.double_offchip_lds_buf = 1;
+}
+
 static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
 {
        u32 gb_addr_config = 0;
@@ -1736,6 +1741,7 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
        gfx_v6_0_setup_spi(adev);
 
        gfx_v6_0_get_cu_info(adev);
+       gfx_v6_0_config_init(adev);
 
        WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) |
                                       (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT)));
index 1f9354541f29b1c13aa2a87f590b1382a9a1756d..286d6763afa735b046e85e3b09a96683f71df0e7 100644 (file)
@@ -1876,6 +1876,11 @@ static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev)
        mutex_unlock(&adev->srbm_mutex);
 }
 
+static void gfx_v7_0_config_init(struct amdgpu_device *adev)
+{
+       adev->gfx.config.double_offchip_lds_buf = 1;
+}
+
 /**
  * gfx_v7_0_gpu_init - setup the 3D engine
  *
@@ -1899,6 +1904,7 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
 
        gfx_v7_0_setup_rb(adev);
        gfx_v7_0_get_cu_info(adev);
+       gfx_v7_0_config_init(adev);
 
        /* set HW defaults for 3D engine */
        WREG32(mmCP_MEQ_THRESHOLDS,
index c2a3251857538ded0c5e6320d2ef8095c9e306f3..5682d945e5887d9f1f15291e182405c538757e7c 100644 (file)
@@ -3846,6 +3846,19 @@ static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
        mutex_unlock(&adev->srbm_mutex);
 }
 
+static void gfx_v8_0_config_init(struct amdgpu_device *adev)
+{
+       switch (adev->asic_type) {
+       default:
+               adev->gfx.config.double_offchip_lds_buf = 1;
+               break;
+       case CHIP_CARRIZO:
+       case CHIP_STONEY:
+               adev->gfx.config.double_offchip_lds_buf = 0;
+               break;
+       }
+}
+
 static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
 {
        u32 tmp;
@@ -3859,6 +3872,7 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
        gfx_v8_0_tiling_mode_table_init(adev);
        gfx_v8_0_setup_rb(adev);
        gfx_v8_0_get_cu_info(adev);
+       gfx_v8_0_config_init(adev);
 
        /* XXX SH_MEM regs */
        /* where to put LDS, scratch, GPUVM in FSA64 space */
index a30fe693175fb3a6f2ed4865ba786600f8ffcc85..732c662fad7943bd639445531113486dc88ee833 100644 (file)
@@ -726,6 +726,8 @@ struct drm_amdgpu_info_device {
        __u32 vram_bit_width;
        /* vce harvesting instance */
        __u32 vce_harvest_config;
+       /* gfx double offchip LDS buffers */
+       __u32 gc_double_offchip_lds_buf;
 };
 
 struct drm_amdgpu_info_hw_ip {