drm/radeon: remove struct radeon_bo_list
authorChristian König <christian.koenig@amd.com>
Mon, 3 Mar 2014 11:38:08 +0000 (12:38 +0100)
committerChristian König <christian.koenig@amd.com>
Tue, 4 Mar 2014 13:34:34 +0000 (14:34 +0100)
Just move all fields into radeon_cs_reloc, removing unused/duplicated fields.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/radeon/evergreen_cs.c
drivers/gpu/drm/radeon/r100.c
drivers/gpu/drm/radeon/r200.c
drivers/gpu/drm/radeon/r300.c
drivers/gpu/drm/radeon/r600_cs.c
drivers/gpu/drm/radeon/radeon.h
drivers/gpu/drm/radeon/radeon_cs.c
drivers/gpu/drm/radeon/radeon_object.c
drivers/gpu/drm/radeon/radeon_uvd.c
drivers/gpu/drm/radeon/radeon_vce.c
drivers/gpu/drm/radeon/radeon_vm.c

index c7cac07f139b2106041208179d124d8ff5ba20b0..5c8b358f9fbad903fb8615fd7806235fec0e5bf4 100644 (file)
@@ -1165,7 +1165,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                                        "0x%04X\n", reg);
                        return -EINVAL;
                }
-               ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+               ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
                break;
        case DB_DEPTH_CONTROL:
                track->db_depth_control = radeon_get_ib_value(p, idx);
@@ -1196,12 +1196,12 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                        }
                        ib[idx] &= ~Z_ARRAY_MODE(0xf);
                        track->db_z_info &= ~Z_ARRAY_MODE(0xf);
-                       ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
-                       track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
-                       if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
+                       ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
+                       track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
+                       if (reloc->tiling_flags & RADEON_TILING_MACRO) {
                                unsigned bankw, bankh, mtaspect, tile_split;
 
-                               evergreen_tiling_fields(reloc->lobj.tiling_flags,
+                               evergreen_tiling_fields(reloc->tiling_flags,
                                                        &bankw, &bankh, &mtaspect,
                                                        &tile_split);
                                ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
@@ -1237,7 +1237,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                        return -EINVAL;
                }
                track->db_z_read_offset = radeon_get_ib_value(p, idx);
-               ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+               ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
                track->db_z_read_bo = reloc->robj;
                track->db_dirty = true;
                break;
@@ -1249,7 +1249,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                        return -EINVAL;
                }
                track->db_z_write_offset = radeon_get_ib_value(p, idx);
-               ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+               ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
                track->db_z_write_bo = reloc->robj;
                track->db_dirty = true;
                break;
@@ -1261,7 +1261,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                        return -EINVAL;
                }
                track->db_s_read_offset = radeon_get_ib_value(p, idx);
-               ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+               ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
                track->db_s_read_bo = reloc->robj;
                track->db_dirty = true;
                break;
@@ -1273,7 +1273,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                        return -EINVAL;
                }
                track->db_s_write_offset = radeon_get_ib_value(p, idx);
-               ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+               ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
                track->db_s_write_bo = reloc->robj;
                track->db_dirty = true;
                break;
@@ -1297,7 +1297,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                }
                tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
                track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
-               ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+               ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
                track->vgt_strmout_bo[tmp] = reloc->robj;
                track->streamout_dirty = true;
                break;
@@ -1317,7 +1317,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                                        "0x%04X\n", reg);
                        return -EINVAL;
                }
-               ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+               ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
        case CB_TARGET_MASK:
                track->cb_target_mask = radeon_get_ib_value(p, idx);
                track->cb_dirty = true;
@@ -1381,8 +1381,8 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                                                "0x%04X\n", reg);
                                return -EINVAL;
                        }
-                       ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
-                       track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
+                       ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
+                       track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
                }
                track->cb_dirty = true;
                break;
@@ -1399,8 +1399,8 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                                                "0x%04X\n", reg);
                                return -EINVAL;
                        }
-                       ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
-                       track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
+                       ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
+                       track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
                }
                track->cb_dirty = true;
                break;
@@ -1461,10 +1461,10 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                        return -EINVAL;
                }
                if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
-                       if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
+                       if (reloc->tiling_flags & RADEON_TILING_MACRO) {
                                unsigned bankw, bankh, mtaspect, tile_split;
 
-                               evergreen_tiling_fields(reloc->lobj.tiling_flags,
+                               evergreen_tiling_fields(reloc->tiling_flags,
                                                        &bankw, &bankh, &mtaspect,
                                                        &tile_split);
                                ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
@@ -1489,10 +1489,10 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                        return -EINVAL;
                }
                if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
-                       if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
+                       if (reloc->tiling_flags & RADEON_TILING_MACRO) {
                                unsigned bankw, bankh, mtaspect, tile_split;
 
-                               evergreen_tiling_fields(reloc->lobj.tiling_flags,
+                               evergreen_tiling_fields(reloc->tiling_flags,
                                                        &bankw, &bankh, &mtaspect,
                                                        &tile_split);
                                ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
@@ -1520,7 +1520,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                        dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
                        return -EINVAL;
                }
-               ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+               ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
                track->cb_color_fmask_bo[tmp] = reloc->robj;
                break;
        case CB_COLOR0_CMASK:
@@ -1537,7 +1537,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                        dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
                        return -EINVAL;
                }
-               ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+               ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
                track->cb_color_cmask_bo[tmp] = reloc->robj;
                break;
        case CB_COLOR0_FMASK_SLICE:
@@ -1578,7 +1578,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                }
                tmp = (reg - CB_COLOR0_BASE) / 0x3c;
                track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
-               ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+               ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
                track->cb_color_bo[tmp] = reloc->robj;
                track->cb_dirty = true;
                break;
@@ -1594,7 +1594,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                }
                tmp = ((reg - CB_COLOR8_BASE) / 0x1c) + 8;
                track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
-               ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+               ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
                track->cb_color_bo[tmp] = reloc->robj;
                track->cb_dirty = true;
                break;
@@ -1606,7 +1606,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                        return -EINVAL;
                }
                track->htile_offset = radeon_get_ib_value(p, idx);
-               ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+               ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
                track->htile_bo = reloc->robj;
                track->db_dirty = true;
                break;
@@ -1723,7 +1723,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                                        "0x%04X\n", reg);
                        return -EINVAL;
                }
-               ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+               ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
                break;
        case SX_MEMORY_EXPORT_BASE:
                if (p->rdev->family >= CHIP_CAYMAN) {
@@ -1737,7 +1737,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                                        "0x%04X\n", reg);
                        return -EINVAL;
                }
-               ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+               ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
                break;
        case CAYMAN_SX_SCATTER_EXPORT_BASE:
                if (p->rdev->family < CHIP_CAYMAN) {
@@ -1751,7 +1751,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                                        "0x%04X\n", reg);
                        return -EINVAL;
                }
-               ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+               ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
                break;
        case SX_MISC:
                track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
@@ -1836,7 +1836,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                        return -EINVAL;
                }
 
-               offset = reloc->lobj.gpu_offset +
+               offset = reloc->gpu_offset +
                         (idx_value & 0xfffffff0) +
                         ((u64)(tmp & 0xff) << 32);
 
@@ -1882,7 +1882,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                        return -EINVAL;
                }
 
-               offset = reloc->lobj.gpu_offset +
+               offset = reloc->gpu_offset +
                         idx_value +
                         ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
 
@@ -1909,7 +1909,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                        return -EINVAL;
                }
 
-               offset = reloc->lobj.gpu_offset +
+               offset = reloc->gpu_offset +
                         idx_value +
                         ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
 
@@ -1937,7 +1937,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                        return -EINVAL;
                }
 
-               offset = reloc->lobj.gpu_offset +
+               offset = reloc->gpu_offset +
                         radeon_get_ib_value(p, idx+1) +
                         ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
 
@@ -2027,7 +2027,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                        DRM_ERROR("bad DISPATCH_INDIRECT\n");
                        return -EINVAL;
                }
-               ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
+               ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff);
                r = evergreen_cs_track_check(p);
                if (r) {
                        dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
@@ -2049,7 +2049,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                                return -EINVAL;
                        }
 
-                       offset = reloc->lobj.gpu_offset +
+                       offset = reloc->gpu_offset +
                                 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
                                 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
 
@@ -2106,7 +2106,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                                tmp = radeon_get_ib_value(p, idx) +
                                        ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
 
-                               offset = reloc->lobj.gpu_offset + tmp;
+                               offset = reloc->gpu_offset + tmp;
 
                                if ((tmp + size) > radeon_bo_size(reloc->robj)) {
                                        dev_warn(p->dev, "CP DMA src buffer too small (%llu %lu)\n",
@@ -2144,7 +2144,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                                tmp = radeon_get_ib_value(p, idx+2) +
                                        ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32);
 
-                               offset = reloc->lobj.gpu_offset + tmp;
+                               offset = reloc->gpu_offset + tmp;
 
                                if ((tmp + size) > radeon_bo_size(reloc->robj)) {
                                        dev_warn(p->dev, "CP DMA dst buffer too small (%llu %lu)\n",
@@ -2174,7 +2174,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                                DRM_ERROR("bad SURFACE_SYNC\n");
                                return -EINVAL;
                        }
-                       ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+                       ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
                }
                break;
        case PACKET3_EVENT_WRITE:
@@ -2190,7 +2190,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                                DRM_ERROR("bad EVENT_WRITE\n");
                                return -EINVAL;
                        }
-                       offset = reloc->lobj.gpu_offset +
+                       offset = reloc->gpu_offset +
                                 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) +
                                 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
 
@@ -2212,7 +2212,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                        return -EINVAL;
                }
 
-               offset = reloc->lobj.gpu_offset +
+               offset = reloc->gpu_offset +
                         (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
                         ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
 
@@ -2234,7 +2234,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                        return -EINVAL;
                }
 
-               offset = reloc->lobj.gpu_offset +
+               offset = reloc->gpu_offset +
                         (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
                         ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
 
@@ -2302,11 +2302,11 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                                }
                                if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
                                        ib[idx+1+(i*8)+1] |=
-                                               TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
-                                       if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
+                                               TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
+                                       if (reloc->tiling_flags & RADEON_TILING_MACRO) {
                                                unsigned bankw, bankh, mtaspect, tile_split;
 
-                                               evergreen_tiling_fields(reloc->lobj.tiling_flags,
+                                               evergreen_tiling_fields(reloc->tiling_flags,
                                                                        &bankw, &bankh, &mtaspect,
                                                                        &tile_split);
                                                ib[idx+1+(i*8)+6] |= TEX_TILE_SPLIT(tile_split);
@@ -2318,7 +2318,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                                        }
                                }
                                texture = reloc->robj;
-                               toffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+                               toffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
 
                                /* tex mip base */
                                tex_dim = ib[idx+1+(i*8)+0] & 0x7;
@@ -2337,7 +2337,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                                                DRM_ERROR("bad SET_RESOURCE (tex)\n");
                                                return -EINVAL;
                                        }
-                                       moffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+                                       moffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
                                        mipmap = reloc->robj;
                                }
 
@@ -2364,7 +2364,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                                        ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset;
                                }
 
-                               offset64 = reloc->lobj.gpu_offset + offset;
+                               offset64 = reloc->gpu_offset + offset;
                                ib[idx+1+(i*8)+0] = offset64;
                                ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) |
                                                    (upper_32_bits(offset64) & 0xff);
@@ -2445,7 +2445,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                                          offset + 4, radeon_bo_size(reloc->robj));
                                return -EINVAL;
                        }
-                       offset += reloc->lobj.gpu_offset;
+                       offset += reloc->gpu_offset;
                        ib[idx+1] = offset;
                        ib[idx+2] = upper_32_bits(offset) & 0xff;
                }
@@ -2464,7 +2464,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                                          offset + 4, radeon_bo_size(reloc->robj));
                                return -EINVAL;
                        }
-                       offset += reloc->lobj.gpu_offset;
+                       offset += reloc->gpu_offset;
                        ib[idx+3] = offset;
                        ib[idx+4] = upper_32_bits(offset) & 0xff;
                }
@@ -2493,7 +2493,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                                  offset + 8, radeon_bo_size(reloc->robj));
                        return -EINVAL;
                }
-               offset += reloc->lobj.gpu_offset;
+               offset += reloc->gpu_offset;
                ib[idx+0] = offset;
                ib[idx+1] = upper_32_bits(offset) & 0xff;
                break;
@@ -2518,7 +2518,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                                          offset + 4, radeon_bo_size(reloc->robj));
                                return -EINVAL;
                        }
-                       offset += reloc->lobj.gpu_offset;
+                       offset += reloc->gpu_offset;
                        ib[idx+1] = offset;
                        ib[idx+2] = upper_32_bits(offset) & 0xff;
                } else {
@@ -2542,7 +2542,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                                          offset + 4, radeon_bo_size(reloc->robj));
                                return -EINVAL;
                        }
-                       offset += reloc->lobj.gpu_offset;
+                       offset += reloc->gpu_offset;
                        ib[idx+3] = offset;
                        ib[idx+4] = upper_32_bits(offset) & 0xff;
                } else {
@@ -2717,7 +2717,7 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
                                dst_offset = radeon_get_ib_value(p, idx+1);
                                dst_offset <<= 8;
 
-                               ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
+                               ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);
                                p->idx += count + 7;
                                break;
                        /* linear */
@@ -2725,8 +2725,8 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
                                dst_offset = radeon_get_ib_value(p, idx+1);
                                dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
 
-                               ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
-                               ib[idx+2] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
+                               ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
+                               ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
                                p->idx += count + 3;
                                break;
                        default:
@@ -2768,10 +2768,10 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
                                                        dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
                                        return -EINVAL;
                                }
-                               ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
-                               ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
-                               ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
-                               ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
+                               ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
+                               ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
+                               ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
+                               ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
                                p->idx += 5;
                                break;
                        /* Copy L2T/T2L */
@@ -2781,22 +2781,22 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
                                        /* tiled src, linear dst */
                                        src_offset = radeon_get_ib_value(p, idx+1);
                                        src_offset <<= 8;
-                                       ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
+                                       ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);
 
                                        dst_offset = radeon_get_ib_value(p, idx + 7);
                                        dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;
-                                       ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
-                                       ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
+                                       ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
+                                       ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
                                } else {
                                        /* linear src, tiled dst */
                                        src_offset = radeon_get_ib_value(p, idx+7);
                                        src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;
-                                       ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
-                                       ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
+                                       ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
+                                       ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
 
                                        dst_offset = radeon_get_ib_value(p, idx+1);
                                        dst_offset <<= 8;
-                                       ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
+                                       ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);
                                }
                                if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
                                        dev_warn(p->dev, "DMA L2T, src buffer too small (%llu %lu)\n",
@@ -2827,10 +2827,10 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
                                                        dst_offset + count, radeon_bo_size(dst_reloc->robj));
                                        return -EINVAL;
                                }
-                               ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xffffffff);
-                               ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xffffffff);
-                               ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
-                               ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
+                               ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xffffffff);
+                               ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xffffffff);
+                               ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
+                               ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
                                p->idx += 5;
                                break;
                        /* Copy L2L, partial */
@@ -2840,10 +2840,10 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
                                        DRM_ERROR("L2L Partial is cayman only !\n");
                                        return -EINVAL;
                                }
-                               ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset & 0xffffffff);
-                               ib[idx+2] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
-                               ib[idx+4] += (u32)(dst_reloc->lobj.gpu_offset & 0xffffffff);
-                               ib[idx+5] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
+                               ib[idx+1] += (u32)(src_reloc->gpu_offset & 0xffffffff);
+                               ib[idx+2] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
+                               ib[idx+4] += (u32)(dst_reloc->gpu_offset & 0xffffffff);
+                               ib[idx+5] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
 
                                p->idx += 9;
                                break;
@@ -2876,12 +2876,12 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
                                                        dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
                                        return -EINVAL;
                                }
-                               ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
-                               ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset & 0xfffffffc);
-                               ib[idx+3] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
-                               ib[idx+4] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
-                               ib[idx+5] += upper_32_bits(dst2_reloc->lobj.gpu_offset) & 0xff;
-                               ib[idx+6] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
+                               ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
+                               ib[idx+2] += (u32)(dst2_reloc->gpu_offset & 0xfffffffc);
+                               ib[idx+3] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
+                               ib[idx+4] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
+                               ib[idx+5] += upper_32_bits(dst2_reloc->gpu_offset) & 0xff;
+                               ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
                                p->idx += 7;
                                break;
                        /* Copy L2T Frame to Field */
@@ -2916,10 +2916,10 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
                                                        dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
                                        return -EINVAL;
                                }
-                               ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
-                               ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8);
-                               ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
-                               ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
+                               ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);
+                               ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8);
+                               ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
+                               ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
                                p->idx += 10;
                                break;
                        /* Copy L2T/T2L, partial */
@@ -2932,16 +2932,16 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
                                /* detile bit */
                                if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {
                                        /* tiled src, linear dst */
-                                       ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
+                                       ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);
 
-                                       ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
-                                       ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
+                                       ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
+                                       ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
                                } else {
                                        /* linear src, tiled dst */
-                                       ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
-                                       ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
+                                       ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
+                                       ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
 
-                                       ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
+                                       ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);
                                }
                                p->idx += 12;
                                break;
@@ -2978,10 +2978,10 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
                                                        dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
                                        return -EINVAL;
                                }
-                               ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
-                               ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8);
-                               ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
-                               ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
+                               ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);
+                               ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8);
+                               ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
+                               ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
                                p->idx += 10;
                                break;
                        /* Copy L2T/T2L (tile units) */
@@ -2992,22 +2992,22 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
                                        /* tiled src, linear dst */
                                        src_offset = radeon_get_ib_value(p, idx+1);
                                        src_offset <<= 8;
-                                       ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
+                                       ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);
 
                                        dst_offset = radeon_get_ib_value(p, idx+7);
                                        dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;
-                                       ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
-                                       ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
+                                       ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
+                                       ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
                                } else {
                                        /* linear src, tiled dst */
                                        src_offset = radeon_get_ib_value(p, idx+7);
                                        src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;
-                                       ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
-                                       ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
+                                       ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
+                                       ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
 
                                        dst_offset = radeon_get_ib_value(p, idx+1);
                                        dst_offset <<= 8;
-                                       ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
+                                       ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);
                                }
                                if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
                                        dev_warn(p->dev, "DMA L2T, T2L src buffer too small (%llu %lu)\n",
@@ -3028,8 +3028,8 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
                                        DRM_ERROR("L2T, T2L Partial is cayman only !\n");
                                        return -EINVAL;
                                }
-                               ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
-                               ib[idx+4] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
+                               ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);
+                               ib[idx+4] += (u32)(dst_reloc->gpu_offset >> 8);
                                p->idx += 13;
                                break;
                        /* Copy L2T broadcast (tile units) */
@@ -3065,10 +3065,10 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
                                                        dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
                                        return -EINVAL;
                                }
-                               ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
-                               ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8);
-                               ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
-                               ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
+                               ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);
+                               ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8);
+                               ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
+                               ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
                                p->idx += 10;
                                break;
                        default:
@@ -3089,8 +3089,8 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
                                         dst_offset, radeon_bo_size(dst_reloc->robj));
                                return -EINVAL;
                        }
-                       ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
-                       ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) << 16) & 0x00ff0000;
+                       ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
+                       ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000;
                        p->idx += 4;
                        break;
                case DMA_PACKET_NOP:
index 1690a2dc0721041a613bb0ee28045a49554ce2dc..0a894aee7406e1131aa27402183d75b7b2d8af6e 100644 (file)
@@ -1274,12 +1274,12 @@ int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
 
        value = radeon_get_ib_value(p, idx);
        tmp = value & 0x003fffff;
-       tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
+       tmp += (((u32)reloc->gpu_offset) >> 10);
 
        if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
-               if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+               if (reloc->tiling_flags & RADEON_TILING_MACRO)
                        tile_flags |= RADEON_DST_TILE_MACRO;
-               if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
+               if (reloc->tiling_flags & RADEON_TILING_MICRO) {
                        if (reg == RADEON_SRC_PITCH_OFFSET) {
                                DRM_ERROR("Cannot src blit from microtiled surface\n");
                                radeon_cs_dump_packet(p, pkt);
@@ -1325,7 +1325,7 @@ int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
                        return r;
                }
                idx_value = radeon_get_ib_value(p, idx);
-               ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
+               ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
 
                track->arrays[i + 0].esize = idx_value >> 8;
                track->arrays[i + 0].robj = reloc->robj;
@@ -1337,7 +1337,7 @@ int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
                        radeon_cs_dump_packet(p, pkt);
                        return r;
                }
-               ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
+               ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);
                track->arrays[i + 1].robj = reloc->robj;
                track->arrays[i + 1].esize = idx_value >> 24;
                track->arrays[i + 1].esize &= 0x7F;
@@ -1351,7 +1351,7 @@ int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
                        return r;
                }
                idx_value = radeon_get_ib_value(p, idx);
-               ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
+               ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
                track->arrays[i + 0].robj = reloc->robj;
                track->arrays[i + 0].esize = idx_value >> 8;
                track->arrays[i + 0].esize &= 0x7F;
@@ -1594,7 +1594,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
                track->zb.robj = reloc->robj;
                track->zb.offset = idx_value;
                track->zb_dirty = true;
-               ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
+               ib[idx] = idx_value + ((u32)reloc->gpu_offset);
                break;
        case RADEON_RB3D_COLOROFFSET:
                r = radeon_cs_packet_next_reloc(p, &reloc, 0);
@@ -1607,7 +1607,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
                track->cb[0].robj = reloc->robj;
                track->cb[0].offset = idx_value;
                track->cb_dirty = true;
-               ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
+               ib[idx] = idx_value + ((u32)reloc->gpu_offset);
                break;
        case RADEON_PP_TXOFFSET_0:
        case RADEON_PP_TXOFFSET_1:
@@ -1621,16 +1621,16 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
                        return r;
                }
                if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
-                       if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+                       if (reloc->tiling_flags & RADEON_TILING_MACRO)
                                tile_flags |= RADEON_TXO_MACRO_TILE;
-                       if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
+                       if (reloc->tiling_flags & RADEON_TILING_MICRO)
                                tile_flags |= RADEON_TXO_MICRO_TILE_X2;
 
                        tmp = idx_value & ~(0x7 << 2);
                        tmp |= tile_flags;
-                       ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
+                       ib[idx] = tmp + ((u32)reloc->gpu_offset);
                } else
-                       ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
+                       ib[idx] = idx_value + ((u32)reloc->gpu_offset);
                track->textures[i].robj = reloc->robj;
                track->tex_dirty = true;
                break;
@@ -1648,7 +1648,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
                        return r;
                }
                track->textures[0].cube_info[i].offset = idx_value;
-               ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
+               ib[idx] = idx_value + ((u32)reloc->gpu_offset);
                track->textures[0].cube_info[i].robj = reloc->robj;
                track->tex_dirty = true;
                break;
@@ -1666,7 +1666,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
                        return r;
                }
                track->textures[1].cube_info[i].offset = idx_value;
-               ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
+               ib[idx] = idx_value + ((u32)reloc->gpu_offset);
                track->textures[1].cube_info[i].robj = reloc->robj;
                track->tex_dirty = true;
                break;
@@ -1684,7 +1684,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
                        return r;
                }
                track->textures[2].cube_info[i].offset = idx_value;
-               ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
+               ib[idx] = idx_value + ((u32)reloc->gpu_offset);
                track->textures[2].cube_info[i].robj = reloc->robj;
                track->tex_dirty = true;
                break;
@@ -1702,9 +1702,9 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
                        return r;
                }
                if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
-                       if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+                       if (reloc->tiling_flags & RADEON_TILING_MACRO)
                                tile_flags |= RADEON_COLOR_TILE_ENABLE;
-                       if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
+                       if (reloc->tiling_flags & RADEON_TILING_MICRO)
                                tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
 
                        tmp = idx_value & ~(0x7 << 16);
@@ -1772,7 +1772,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
                        radeon_cs_dump_packet(p, pkt);
                        return r;
                }
-               ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
+               ib[idx] = idx_value + ((u32)reloc->gpu_offset);
                break;
        case RADEON_PP_CNTL:
                {
@@ -1932,7 +1932,7 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
                        radeon_cs_dump_packet(p, pkt);
                        return r;
                }
-               ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
+               ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset);
                r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
                if (r) {
                        return r;
@@ -1946,7 +1946,7 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
                        radeon_cs_dump_packet(p, pkt);
                        return r;
                }
-               ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
+               ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset);
                track->num_arrays = 1;
                track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
 
index b3807edb19365e79e61bf392a66c22156803859e..58f0473aa73fba3cd1e62a786d6776c7a20ccd3b 100644 (file)
@@ -185,7 +185,7 @@ int r200_packet0_check(struct radeon_cs_parser *p,
                track->zb.robj = reloc->robj;
                track->zb.offset = idx_value;
                track->zb_dirty = true;
-               ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
+               ib[idx] = idx_value + ((u32)reloc->gpu_offset);
                break;
        case RADEON_RB3D_COLOROFFSET:
                r = radeon_cs_packet_next_reloc(p, &reloc, 0);
@@ -198,7 +198,7 @@ int r200_packet0_check(struct radeon_cs_parser *p,
                track->cb[0].robj = reloc->robj;
                track->cb[0].offset = idx_value;
                track->cb_dirty = true;
-               ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
+               ib[idx] = idx_value + ((u32)reloc->gpu_offset);
                break;
        case R200_PP_TXOFFSET_0:
        case R200_PP_TXOFFSET_1:
@@ -215,16 +215,16 @@ int r200_packet0_check(struct radeon_cs_parser *p,
                        return r;
                }
                if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
-                       if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+                       if (reloc->tiling_flags & RADEON_TILING_MACRO)
                                tile_flags |= R200_TXO_MACRO_TILE;
-                       if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
+                       if (reloc->tiling_flags & RADEON_TILING_MICRO)
                                tile_flags |= R200_TXO_MICRO_TILE;
 
                        tmp = idx_value & ~(0x7 << 2);
                        tmp |= tile_flags;
-                       ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
+                       ib[idx] = tmp + ((u32)reloc->gpu_offset);
                } else
-                       ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
+                       ib[idx] = idx_value + ((u32)reloc->gpu_offset);
                track->textures[i].robj = reloc->robj;
                track->tex_dirty = true;
                break;
@@ -268,7 +268,7 @@ int r200_packet0_check(struct radeon_cs_parser *p,
                        return r;
                }
                track->textures[i].cube_info[face - 1].offset = idx_value;
-               ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
+               ib[idx] = idx_value + ((u32)reloc->gpu_offset);
                track->textures[i].cube_info[face - 1].robj = reloc->robj;
                track->tex_dirty = true;
                break;
@@ -287,9 +287,9 @@ int r200_packet0_check(struct radeon_cs_parser *p,
                }
 
                if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
-                       if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+                       if (reloc->tiling_flags & RADEON_TILING_MACRO)
                                tile_flags |= RADEON_COLOR_TILE_ENABLE;
-                       if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
+                       if (reloc->tiling_flags & RADEON_TILING_MICRO)
                                tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
 
                        tmp = idx_value & ~(0x7 << 16);
@@ -362,7 +362,7 @@ int r200_packet0_check(struct radeon_cs_parser *p,
                        radeon_cs_dump_packet(p, pkt);
                        return r;
                }
-               ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
+               ib[idx] = idx_value + ((u32)reloc->gpu_offset);
                break;
        case RADEON_PP_CNTL:
                {
index 7c63ef840e86abaf04f216201b32ee2f40323b9b..41cdf236ee9ab49b843c8007792aa38af504056e 100644 (file)
@@ -640,7 +640,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
                track->cb[i].robj = reloc->robj;
                track->cb[i].offset = idx_value;
                track->cb_dirty = true;
-               ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
+               ib[idx] = idx_value + ((u32)reloc->gpu_offset);
                break;
        case R300_ZB_DEPTHOFFSET:
                r = radeon_cs_packet_next_reloc(p, &reloc, 0);
@@ -653,7 +653,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
                track->zb.robj = reloc->robj;
                track->zb.offset = idx_value;
                track->zb_dirty = true;
-               ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
+               ib[idx] = idx_value + ((u32)reloc->gpu_offset);
                break;
        case R300_TX_OFFSET_0:
        case R300_TX_OFFSET_0+4:
@@ -682,16 +682,16 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
 
                if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) {
                        ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */
-                                 ((idx_value & ~31) + (u32)reloc->lobj.gpu_offset);
+                                 ((idx_value & ~31) + (u32)reloc->gpu_offset);
                } else {
-                       if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+                       if (reloc->tiling_flags & RADEON_TILING_MACRO)
                                tile_flags |= R300_TXO_MACRO_TILE;
-                       if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
+                       if (reloc->tiling_flags & RADEON_TILING_MICRO)
                                tile_flags |= R300_TXO_MICRO_TILE;
-                       else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
+                       else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
                                tile_flags |= R300_TXO_MICRO_TILE_SQUARE;
 
-                       tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
+                       tmp = idx_value + ((u32)reloc->gpu_offset);
                        tmp |= tile_flags;
                        ib[idx] = tmp;
                }
@@ -753,11 +753,11 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
                                return r;
                        }
 
-                       if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+                       if (reloc->tiling_flags & RADEON_TILING_MACRO)
                                tile_flags |= R300_COLOR_TILE_ENABLE;
-                       if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
+                       if (reloc->tiling_flags & RADEON_TILING_MICRO)
                                tile_flags |= R300_COLOR_MICROTILE_ENABLE;
-                       else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
+                       else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
                                tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE;
 
                        tmp = idx_value & ~(0x7 << 16);
@@ -838,11 +838,11 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
                                return r;
                        }
 
-                       if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+                       if (reloc->tiling_flags & RADEON_TILING_MACRO)
                                tile_flags |= R300_DEPTHMACROTILE_ENABLE;
-                       if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
+                       if (reloc->tiling_flags & RADEON_TILING_MICRO)
                                tile_flags |= R300_DEPTHMICROTILE_TILED;
-                       else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
+                       else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
                                tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE;
 
                        tmp = idx_value & ~(0x7 << 16);
@@ -1052,7 +1052,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
                        radeon_cs_dump_packet(p, pkt);
                        return r;
                }
-               ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
+               ib[idx] = idx_value + ((u32)reloc->gpu_offset);
                break;
        case 0x4e0c:
                /* RB3D_COLOR_CHANNEL_MASK */
@@ -1097,7 +1097,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
                track->aa.robj = reloc->robj;
                track->aa.offset = idx_value;
                track->aa_dirty = true;
-               ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
+               ib[idx] = idx_value + ((u32)reloc->gpu_offset);
                break;
        case R300_RB3D_AARESOLVE_PITCH:
                track->aa.pitch = idx_value & 0x3FFE;
@@ -1162,7 +1162,7 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
                        radeon_cs_dump_packet(p, pkt);
                        return r;
                }
-               ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
+               ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
                r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
                if (r) {
                        return r;
index 2812c7d1ae6f21b5d4ba6550755b5ecc3fc8ef61..12511bb5fd6facea3f6b5eca1a5eaf43093274fe 100644 (file)
@@ -1022,7 +1022,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                                        "0x%04X\n", reg);
                        return -EINVAL;
                }
-               ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+               ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
                break;
        case SQ_CONFIG:
                track->sq_config = radeon_get_ib_value(p, idx);
@@ -1043,7 +1043,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                        track->db_depth_info = radeon_get_ib_value(p, idx);
                        ib[idx] &= C_028010_ARRAY_MODE;
                        track->db_depth_info &= C_028010_ARRAY_MODE;
-                       if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
+                       if (reloc->tiling_flags & RADEON_TILING_MACRO) {
                                ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
                                track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
                        } else {
@@ -1084,9 +1084,9 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                }
                tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
                track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
-               ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+               ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
                track->vgt_strmout_bo[tmp] = reloc->robj;
-               track->vgt_strmout_bo_mc[tmp] = reloc->lobj.gpu_offset;
+               track->vgt_strmout_bo_mc[tmp] = reloc->gpu_offset;
                track->streamout_dirty = true;
                break;
        case VGT_STRMOUT_BUFFER_SIZE_0:
@@ -1105,7 +1105,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                                        "0x%04X\n", reg);
                        return -EINVAL;
                }
-               ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+               ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
                break;
        case R_028238_CB_TARGET_MASK:
                track->cb_target_mask = radeon_get_ib_value(p, idx);
@@ -1142,10 +1142,10 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                        }
                        tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
                        track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
-                       if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
+                       if (reloc->tiling_flags & RADEON_TILING_MACRO) {
                                ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
                                track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
-                       } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
+                       } else if (reloc->tiling_flags & RADEON_TILING_MICRO) {
                                ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
                                track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
                        }
@@ -1214,7 +1214,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                        }
                        track->cb_color_frag_bo[tmp] = reloc->robj;
                        track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8;
-                       ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+                       ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
                }
                if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
                        track->cb_dirty = true;
@@ -1245,7 +1245,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                        }
                        track->cb_color_tile_bo[tmp] = reloc->robj;
                        track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8;
-                       ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+                       ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
                }
                if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
                        track->cb_dirty = true;
@@ -1281,10 +1281,10 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                }
                tmp = (reg - CB_COLOR0_BASE) / 4;
                track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
-               ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+               ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
                track->cb_color_base_last[tmp] = ib[idx];
                track->cb_color_bo[tmp] = reloc->robj;
-               track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset;
+               track->cb_color_bo_mc[tmp] = reloc->gpu_offset;
                track->cb_dirty = true;
                break;
        case DB_DEPTH_BASE:
@@ -1295,9 +1295,9 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                        return -EINVAL;
                }
                track->db_offset = radeon_get_ib_value(p, idx) << 8;
-               ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+               ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
                track->db_bo = reloc->robj;
-               track->db_bo_mc = reloc->lobj.gpu_offset;
+               track->db_bo_mc = reloc->gpu_offset;
                track->db_dirty = true;
                break;
        case DB_HTILE_DATA_BASE:
@@ -1308,7 +1308,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                        return -EINVAL;
                }
                track->htile_offset = radeon_get_ib_value(p, idx) << 8;
-               ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+               ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
                track->htile_bo = reloc->robj;
                track->db_dirty = true;
                break;
@@ -1377,7 +1377,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                                        "0x%04X\n", reg);
                        return -EINVAL;
                }
-               ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+               ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
                break;
        case SX_MEMORY_EXPORT_BASE:
                r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
@@ -1386,7 +1386,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                                        "0x%04X\n", reg);
                        return -EINVAL;
                }
-               ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+               ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
                break;
        case SX_MISC:
                track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
@@ -1672,7 +1672,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                        return -EINVAL;
                }
 
-               offset = reloc->lobj.gpu_offset +
+               offset = reloc->gpu_offset +
                         (idx_value & 0xfffffff0) +
                         ((u64)(tmp & 0xff) << 32);
 
@@ -1713,7 +1713,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                        return -EINVAL;
                }
 
-               offset = reloc->lobj.gpu_offset +
+               offset = reloc->gpu_offset +
                         idx_value +
                         ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
 
@@ -1765,7 +1765,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                                return -EINVAL;
                        }
 
-                       offset = reloc->lobj.gpu_offset +
+                       offset = reloc->gpu_offset +
                                 (radeon_get_ib_value(p, idx+1) & 0xfffffff0) +
                                 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
 
@@ -1805,7 +1805,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                        tmp = radeon_get_ib_value(p, idx) +
                                ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
 
-                       offset = reloc->lobj.gpu_offset + tmp;
+                       offset = reloc->gpu_offset + tmp;
 
                        if ((tmp + size) > radeon_bo_size(reloc->robj)) {
                                dev_warn(p->dev, "CP DMA src buffer too small (%llu %lu)\n",
@@ -1835,7 +1835,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                        tmp = radeon_get_ib_value(p, idx+2) +
                                ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32);
 
-                       offset = reloc->lobj.gpu_offset + tmp;
+                       offset = reloc->gpu_offset + tmp;
 
                        if ((tmp + size) > radeon_bo_size(reloc->robj)) {
                                dev_warn(p->dev, "CP DMA dst buffer too small (%llu %lu)\n",
@@ -1861,7 +1861,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                                DRM_ERROR("bad SURFACE_SYNC\n");
                                return -EINVAL;
                        }
-                       ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+                       ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
                }
                break;
        case PACKET3_EVENT_WRITE:
@@ -1877,7 +1877,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                                DRM_ERROR("bad EVENT_WRITE\n");
                                return -EINVAL;
                        }
-                       offset = reloc->lobj.gpu_offset +
+                       offset = reloc->gpu_offset +
                                 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) +
                                 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
 
@@ -1899,7 +1899,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                        return -EINVAL;
                }
 
-               offset = reloc->lobj.gpu_offset +
+               offset = reloc->gpu_offset +
                         (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
                         ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
 
@@ -1964,11 +1964,11 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                                        DRM_ERROR("bad SET_RESOURCE\n");
                                        return -EINVAL;
                                }
-                               base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+                               base_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
                                if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
-                                       if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+                                       if (reloc->tiling_flags & RADEON_TILING_MACRO)
                                                ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
-                                       else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
+                                       else if (reloc->tiling_flags & RADEON_TILING_MICRO)
                                                ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
                                }
                                texture = reloc->robj;
@@ -1978,13 +1978,13 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                                        DRM_ERROR("bad SET_RESOURCE\n");
                                        return -EINVAL;
                                }
-                               mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+                               mip_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
                                mipmap = reloc->robj;
                                r = r600_check_texture_resource(p,  idx+(i*7)+1,
                                                                texture, mipmap,
                                                                base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2),
                                                                mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3),
-                                                               reloc->lobj.tiling_flags);
+                                                               reloc->tiling_flags);
                                if (r)
                                        return r;
                                ib[idx+1+(i*7)+2] += base_offset;
@@ -2008,7 +2008,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                                        ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset;
                                }
 
-                               offset64 = reloc->lobj.gpu_offset + offset;
+                               offset64 = reloc->gpu_offset + offset;
                                ib[idx+1+(i*8)+0] = offset64;
                                ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) |
                                                    (upper_32_bits(offset64) & 0xff);
@@ -2118,7 +2118,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                                          offset + 4, radeon_bo_size(reloc->robj));
                                return -EINVAL;
                        }
-                       ib[idx+1] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+                       ib[idx+1] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
                }
                break;
        case PACKET3_SURFACE_BASE_UPDATE:
@@ -2151,7 +2151,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                                          offset + 4, radeon_bo_size(reloc->robj));
                                return -EINVAL;
                        }
-                       offset += reloc->lobj.gpu_offset;
+                       offset += reloc->gpu_offset;
                        ib[idx+1] = offset;
                        ib[idx+2] = upper_32_bits(offset) & 0xff;
                }
@@ -2170,7 +2170,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                                          offset + 4, radeon_bo_size(reloc->robj));
                                return -EINVAL;
                        }
-                       offset += reloc->lobj.gpu_offset;
+                       offset += reloc->gpu_offset;
                        ib[idx+3] = offset;
                        ib[idx+4] = upper_32_bits(offset) & 0xff;
                }
@@ -2199,7 +2199,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                                  offset + 8, radeon_bo_size(reloc->robj));
                        return -EINVAL;
                }
-               offset += reloc->lobj.gpu_offset;
+               offset += reloc->gpu_offset;
                ib[idx+0] = offset;
                ib[idx+1] = upper_32_bits(offset) & 0xff;
                break;
@@ -2224,7 +2224,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                                          offset + 4, radeon_bo_size(reloc->robj));
                                return -EINVAL;
                        }
-                       offset += reloc->lobj.gpu_offset;
+                       offset += reloc->gpu_offset;
                        ib[idx+1] = offset;
                        ib[idx+2] = upper_32_bits(offset) & 0xff;
                } else {
@@ -2248,7 +2248,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                                          offset + 4, radeon_bo_size(reloc->robj));
                                return -EINVAL;
                        }
-                       offset += reloc->lobj.gpu_offset;
+                       offset += reloc->gpu_offset;
                        ib[idx+3] = offset;
                        ib[idx+4] = upper_32_bits(offset) & 0xff;
                } else {
@@ -2505,14 +2505,14 @@ int r600_dma_cs_parse(struct radeon_cs_parser *p)
                                dst_offset = radeon_get_ib_value(p, idx+1);
                                dst_offset <<= 8;
 
-                               ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
+                               ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);
                                p->idx += count + 5;
                        } else {
                                dst_offset = radeon_get_ib_value(p, idx+1);
                                dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
 
-                               ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
-                               ib[idx+2] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
+                               ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
+                               ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
                                p->idx += count + 3;
                        }
                        if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
@@ -2539,22 +2539,22 @@ int r600_dma_cs_parse(struct radeon_cs_parser *p)
                                        /* tiled src, linear dst */
                                        src_offset = radeon_get_ib_value(p, idx+1);
                                        src_offset <<= 8;
-                                       ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
+                                       ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);
 
                                        dst_offset = radeon_get_ib_value(p, idx+5);
                                        dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;
-                                       ib[idx+5] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
-                                       ib[idx+6] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
+                                       ib[idx+5] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
+                                       ib[idx+6] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
                                } else {
                                        /* linear src, tiled dst */
                                        src_offset = radeon_get_ib_value(p, idx+5);
                                        src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;
-                                       ib[idx+5] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
-                                       ib[idx+6] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
+                                       ib[idx+5] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
+                                       ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
 
                                        dst_offset = radeon_get_ib_value(p, idx+1);
                                        dst_offset <<= 8;
-                                       ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
+                                       ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);
                                }
                                p->idx += 7;
                        } else {
@@ -2564,10 +2564,10 @@ int r600_dma_cs_parse(struct radeon_cs_parser *p)
                                        dst_offset = radeon_get_ib_value(p, idx+1);
                                        dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;
 
-                                       ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
-                                       ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
-                                       ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
-                                       ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
+                                       ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
+                                       ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
+                                       ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
+                                       ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
                                        p->idx += 5;
                                } else {
                                        src_offset = radeon_get_ib_value(p, idx+2);
@@ -2575,10 +2575,10 @@ int r600_dma_cs_parse(struct radeon_cs_parser *p)
                                        dst_offset = radeon_get_ib_value(p, idx+1);
                                        dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16;
 
-                                       ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
-                                       ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
-                                       ib[idx+3] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
-                                       ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff) << 16;
+                                       ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
+                                       ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
+                                       ib[idx+3] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
+                                       ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) & 0xff) << 16;
                                        p->idx += 4;
                                }
                        }
@@ -2610,8 +2610,8 @@ int r600_dma_cs_parse(struct radeon_cs_parser *p)
                                         dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
                                return -EINVAL;
                        }
-                       ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
-                       ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) << 16) & 0x00ff0000;
+                       ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
+                       ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000;
                        p->idx += 4;
                        break;
                case DMA_PACKET_NOP:
index cd6a48099547232feb99b47a0b432cc6bc949224..111deab2492a082e7be66a129c7614aaa8b10fbb 100644 (file)
@@ -479,15 +479,6 @@ struct radeon_bo {
 };
 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
 
-struct radeon_bo_list {
-       struct ttm_validate_buffer tv;
-       struct radeon_bo        *bo;
-       uint64_t                gpu_offset;
-       unsigned                domain;
-       unsigned                alt_domain;
-       u32                     tiling_flags;
-};
-
 int radeon_gem_debugfs_init(struct radeon_device *rdev);
 
 /* sub-allocation manager, it has to be protected by another lock.
@@ -987,9 +978,12 @@ void cayman_dma_fini(struct radeon_device *rdev);
 struct radeon_cs_reloc {
        struct drm_gem_object           *gobj;
        struct radeon_bo                *robj;
-       struct radeon_bo_list           lobj;
+       struct ttm_validate_buffer      tv;
+       uint64_t                        gpu_offset;
+       unsigned                        domain;
+       unsigned                        alt_domain;
+       uint32_t                        tiling_flags;
        uint32_t                        handle;
-       uint32_t                        flags;
 };
 
 struct radeon_cs_chunk {
@@ -1013,7 +1007,7 @@ struct radeon_cs_parser {
        unsigned                nrelocs;
        struct radeon_cs_reloc  *relocs;
        struct radeon_cs_reloc  **relocs_ptr;
-       struct radeon_bo_list   *vm_bos;
+       struct radeon_cs_reloc  *vm_bos;
        struct list_head        validated;
        unsigned                dma_reloc_idx;
        /* indices of various chunks */
@@ -2803,9 +2797,9 @@ int radeon_vm_manager_init(struct radeon_device *rdev);
 void radeon_vm_manager_fini(struct radeon_device *rdev);
 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
-struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
-                                        struct radeon_vm *vm,
-                                         struct list_head *head);
+struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
+                                         struct radeon_vm *vm,
+                                          struct list_head *head);
 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
                                       struct radeon_vm *vm, int ring);
 void radeon_vm_flush(struct radeon_device *rdev,
index 0570e7675fd3557979d973c354a083897cee5978..2b6e0ebcc13ab5e75b76089dcbcc00eeae08b360 100644 (file)
@@ -125,7 +125,6 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
                }
                p->relocs_ptr[i] = &p->relocs[i];
                p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
-               p->relocs[i].lobj.bo = p->relocs[i].robj;
 
                /* The userspace buffer priorities are from 0 to 15. A higher
                 * number means the buffer is more important.
@@ -141,10 +140,10 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
                if (p->ring == R600_RING_TYPE_UVD_INDEX &&
                    (i == 0 || drm_pci_device_is_agp(p->rdev->ddev))) {
                        /* TODO: is this still needed for NI+ ? */
-                       p->relocs[i].lobj.domain =
+                       p->relocs[i].domain =
                                RADEON_GEM_DOMAIN_VRAM;
 
-                       p->relocs[i].lobj.alt_domain =
+                       p->relocs[i].alt_domain =
                                RADEON_GEM_DOMAIN_VRAM;
 
                        /* prioritize this over any other relocation */
@@ -153,16 +152,16 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
                        uint32_t domain = r->write_domain ?
                                r->write_domain : r->read_domains;
 
-                       p->relocs[i].lobj.domain = domain;
+                       p->relocs[i].domain = domain;
                        if (domain == RADEON_GEM_DOMAIN_VRAM)
                                domain |= RADEON_GEM_DOMAIN_GTT;
-                       p->relocs[i].lobj.alt_domain = domain;
+                       p->relocs[i].alt_domain = domain;
                }
 
-               p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
+               p->relocs[i].tv.bo = &p->relocs[i].robj->tbo;
                p->relocs[i].handle = r->handle;
 
-               radeon_cs_buckets_add(&buckets, &p->relocs[i].lobj.tv.head,
+               radeon_cs_buckets_add(&buckets, &p->relocs[i].tv.head,
                                      priority);
        }
 
@@ -356,11 +355,11 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
 static int cmp_size_smaller_first(void *priv, struct list_head *a,
                                  struct list_head *b)
 {
-       struct radeon_bo_list *la = list_entry(a, struct radeon_bo_list, tv.head);
-       struct radeon_bo_list *lb = list_entry(b, struct radeon_bo_list, tv.head);
+       struct radeon_cs_reloc *la = list_entry(a, struct radeon_cs_reloc, tv.head);
+       struct radeon_cs_reloc *lb = list_entry(b, struct radeon_cs_reloc, tv.head);
 
        /* Sort A before B if A is smaller. */
-       return (int)la->bo->tbo.num_pages - (int)lb->bo->tbo.num_pages;
+       return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages;
 }
 
 /**
@@ -786,9 +785,9 @@ int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
        /* FIXME: we assume reloc size is 4 dwords */
        if (nomm) {
                *cs_reloc = p->relocs;
-               (*cs_reloc)->lobj.gpu_offset =
+               (*cs_reloc)->gpu_offset =
                        (u64)relocs_chunk->kdata[idx + 3] << 32;
-               (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
+               (*cs_reloc)->gpu_offset |= relocs_chunk->kdata[idx + 0];
        } else
                *cs_reloc = p->relocs_ptr[(idx / 4)];
        return 0;
index ed03f2d158534e286be9c281032d1dd0b9acea32..ca79431b2c1cb0689cfdef39225a5e61f5a6f355 100644 (file)
@@ -422,7 +422,7 @@ int radeon_bo_list_validate(struct radeon_device *rdev,
                            struct ww_acquire_ctx *ticket,
                            struct list_head *head, int ring)
 {
-       struct radeon_bo_list *lobj;
+       struct radeon_cs_reloc *lobj;
        struct radeon_bo *bo;
        int r;
        u64 bytes_moved = 0, initial_bytes_moved;
@@ -434,7 +434,7 @@ int radeon_bo_list_validate(struct radeon_device *rdev,
        }
 
        list_for_each_entry(lobj, head, tv.head) {
-               bo = lobj->bo;
+               bo = lobj->robj;
                if (!bo->pin_count) {
                        u32 domain = lobj->domain;
                        u32 current_domain =
index ceb7b289b7458d848b655708b40f07be94e449b1..6a2e3ff683748a83ba69dab5edd0e88fc4e469cb 100644 (file)
@@ -453,7 +453,7 @@ static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
        }
 
        reloc = p->relocs_ptr[(idx / 4)];
-       start = reloc->lobj.gpu_offset;
+       start = reloc->gpu_offset;
        end = start + radeon_bo_size(reloc->robj);
        start += offset;
 
index 39ec7d8f33ab3b10f00ee8315f812d9b7783a842..76e9904bc5377c23ea33c842137266ed18d560e8 100644 (file)
@@ -461,7 +461,7 @@ int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi)
                return -EINVAL;
        }
 
-       offset += p->relocs_ptr[(idx / 4)]->lobj.gpu_offset;
+       offset += p->relocs_ptr[(idx / 4)]->gpu_offset;
 
         p->ib.ptr[lo] = offset & 0xFFFFFFFF;
         p->ib.ptr[hi] = offset >> 32;
index 81d91b513ce17f2e5af3bd1b696ab321be0cd6e9..2aae6ce49d3286888ea22347b60d71cc5220eef4 100644 (file)
@@ -125,33 +125,39 @@ void radeon_vm_manager_fini(struct radeon_device *rdev)
  * Add the page directory to the list of BOs to
  * validate for command submission (cayman+).
  */
-struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
-                                        struct radeon_vm *vm,
-                                        struct list_head *head)
+struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
+                                         struct radeon_vm *vm,
+                                         struct list_head *head)
 {
-       struct radeon_bo_list *list;
+       struct radeon_cs_reloc *list;
        unsigned i, idx, size;
 
-       size = (radeon_vm_num_pdes(rdev) + 1) * sizeof(struct radeon_bo_list);
+       size = (radeon_vm_num_pdes(rdev) + 1) * sizeof(struct radeon_cs_reloc);
        list = kmalloc(size, GFP_KERNEL);
        if (!list)
                return NULL;
 
        /* add the vm page table to the list */
-       list[0].bo = vm->page_directory;
+       list[0].gobj = NULL;
+       list[0].robj = vm->page_directory;
        list[0].domain = RADEON_GEM_DOMAIN_VRAM;
        list[0].alt_domain = RADEON_GEM_DOMAIN_VRAM;
        list[0].tv.bo = &vm->page_directory->tbo;
+       list[0].tiling_flags = 0;
+       list[0].handle = 0;
        list_add(&list[0].tv.head, head);
 
        for (i = 0, idx = 1; i <= vm->max_pde_used; i++) {
                if (!vm->page_tables[i].bo)
                        continue;
 
-               list[idx].bo = vm->page_tables[i].bo;
+               list[idx].gobj = NULL;
+               list[idx].robj = vm->page_tables[i].bo;
                list[idx].domain = RADEON_GEM_DOMAIN_VRAM;
                list[idx].alt_domain = RADEON_GEM_DOMAIN_VRAM;
-               list[idx].tv.bo = &list[idx].bo->tbo;
+               list[idx].tv.bo = &list[idx].robj->tbo;
+               list[idx].tiling_flags = 0;
+               list[idx].handle = 0;
                list_add(&list[idx++].tv.head, head);
        }