ARM: tegra: fuse: add bct strapping reading

This is used by the memory setup code to pick the right memory
timing table, if needed.

Signed-off-by: Olof Johansson <olof@lixom.net>

diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index b1895c53ed607ad086ddae5843a4aad103e3dbfa..17fdd4086e6fcf87a4216592514fc622d17cb7b8 100644 (file)
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -35,6 +35,17 @@ int tegra_cpu_process_id;
 int tegra_core_process_id;
 enum tegra_revision tegra_revision;
 
+/* The BCT to use at boot is specified by board straps that can be read
+ * through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
+ */
+int tegra_bct_strapping;
+
+#define STRAP_OPT 0x008
+#define GMI_AD0 (1 << 4)
+#define GMI_AD1 (1 << 5)
+#define RAM_ID_MASK (GMI_AD0 | GMI_AD1)
+#define RAM_CODE_SHIFT 4
+
 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
        [TEGRA_REVISION_UNKNOWN] = "unknown",
        [TEGRA_REVISION_A01]     = "A01",
@@ -93,6 +104,9 @@ void tegra_init_fuse(void)
        reg = tegra_fuse_readl(FUSE_SPARE_BIT);
        tegra_core_process_id = (reg >> 12) & 3;
 
+       reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
+       tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
+
        tegra_revision = tegra_get_revision();
 
        pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",

diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index 7576aaf6865c8a1674274639affed52f41255178..d65d2abf803b1da33ac70e909e0ae15477d2135a 100644 (file)
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -40,6 +40,8 @@ extern int tegra_cpu_process_id;
 extern int tegra_core_process_id;
 extern enum tegra_revision tegra_revision;
 
+extern int tegra_bct_strapping;
+
 unsigned long long tegra_chip_uid(void);
 void tegra_init_fuse(void);