[PATCH] i386: Enable bank 0 on non K7 Athlon

As a bug workaround bank 0 on K7s is normally disabled, but no need
to do that on other AMD CPUs.

Cc: davej@redhat.com
Signed-off-by: Andi Kleen <ak@suse.de>

diff --git a/arch/i386/kernel/cpu/mcheck/k7.c b/arch/i386/kernel/cpu/mcheck/k7.c
index b0862af595aa5f502f043f93a305fcd9eb35cc08..7a2472557bbbb7cd4513a3f50f4089f713505c93 100644 (file)
--- a/arch/i386/kernel/cpu/mcheck/k7.c
+++ b/arch/i386/kernel/cpu/mcheck/k7.c
@@ -82,9 +82,13 @@ void amd_mcheck_init(struct cpuinfo_x86 *c)
        nr_mce_banks = l & 0xff;
 
        /* Clear status for MC index 0 separately, we don't touch CTL,
-        * as some Athlons cause spurious MCEs when its enabled. */
-       wrmsr (MSR_IA32_MC0_STATUS, 0x0, 0x0);
-       for (i=1; i<nr_mce_banks; i++) {
+        * as some K7 Athlons cause spurious MCEs when its enabled. */
+       if (boot_cpu_data.x86 == 6) {
+               wrmsr (MSR_IA32_MC0_STATUS, 0x0, 0x0);
+               i = 1;
+       } else
+               i = 0;
+       for (; i<nr_mce_banks; i++) {
                wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
                wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
        }