ucon |= S3C2443_UCON_LOOPBACK;
}
+ /* To prevent unexpected Interrupt before enabling the channel */
+ wr_regl(port, S3C64XX_UINTM, 0xf);
+
/* reset both fifos */
wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
wr_regl(port, S3C2410_UFCON, cfg->ufcon);
struct s3c24xx_uart_port *ourport = to_ourport(port);
if (port) {
- uart_clock_enable(ourport);
- exynos_usi_init(port);
- s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
- uart_clock_disable(ourport);
uart_resume_port(&s3c24xx_uart_drv, port);