drm/i915: Apply B-spec mandated workaround for read flushes on Ironlake.

This is not known to fix any particular bugs we have, but the spec
says to do it, and the BIOS hadn't already set it up on my system.

Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c79d4ba4fb1223bd6b5d14983943c980ceaee97c..09e2a5502652726cb32d0d7bbdfad7d58b39bc0b 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -316,6 +316,19 @@
 
 #define ERROR_GEN6     0x040a0
 
+/* GM45+ chicken bits -- debug workaround bits that may be required
+ * for various sorts of correct behavior.  The top 16 bits of each are
+ * the enables for writing to the corresponding low bit.
+ */
+#define _3D_CHICKEN    0x02084
+#define _3D_CHICKEN2   0x0208c
+/* Disables pipelining of read flushes past the SF-WIZ interface.
+ * Required on all Ironlake steppings according to the B-Spec, but the
+ * particular danger of not doing so is not specified.
+ */
+# define _3D_CHICKEN2_WM_READ_PIPELINED                        (1 << 14)
+#define _3D_CHICKEN3   0x02090
+
 #define MI_MODE                0x0209c
 # define VS_TIMER_DISPATCH                             (1 << 6)
 # define MI_FLUSH_ENABLE                               (1 << 11)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 77b34942dc91ff3f0da4465d08dd0b5cb5ae826a..5ab4035568464c561a17006c2b67c1fd654e837b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5818,6 +5818,12 @@ void intel_init_clock_gating(struct drm_device *dev)
                                   ILK_DPFC_DIS2 |
                                   ILK_CLK_FBC);
                }
+
+               if (IS_GEN5(dev)) {
+                       I915_WRITE(_3D_CHICKEN2,
+                                  _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
+                                  _3D_CHICKEN2_WM_READ_PIPELINED);
+               }
                return;
        } else if (IS_G4X(dev)) {
                uint32_t dspclk_gate;