}
}
+ /* calculate the various different addresses for the object */
+ if (chan) {
+ gpuobj->pinst = gpuobj->im_pramin->start +
+ chan->ramin->gpuobj->im_pramin->start;
+ if (dev_priv->card_type < NV_50) {
+ gpuobj->cinst = gpuobj->pinst;
+ } else {
+ gpuobj->cinst = gpuobj->im_pramin->start;
+ gpuobj->vinst = gpuobj->im_pramin->start +
+ chan->ramin->gpuobj->im_backing_start;
+ }
+ } else {
+ gpuobj->pinst = gpuobj->im_pramin->start;
+ gpuobj->cinst = 0xdeadbeef;
+ gpuobj->vinst = gpuobj->im_backing_start;
+ }
+
if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) {
int i;
/* <NV50 use PRAMIN address everywhere */
if (dev_priv->card_type < NV_50) {
*inst = gpuobj->im_pramin->start;
+ if (gpuobj->im_channel) {
+ cpramin = gpuobj->im_channel->ramin->gpuobj;
+ *inst += cpramin->im_pramin->start;
+ }
return 0;
}
- if (chan && gpuobj->im_channel != chan) {
- NV_ERROR(dev, "Channel mismatch: obj %d, ref %d\n",
- gpuobj->im_channel->id, chan->id);
- return -EINVAL;
- }
-
/* NV50 channel-local instance */
if (chan) {
- cpramin = chan->ramin->gpuobj;
- *inst = gpuobj->im_pramin->start - cpramin->im_pramin->start;
+ *inst = gpuobj->im_pramin->start;
return 0;
}
} else {
/* ...from local heap */
cpramin = gpuobj->im_channel->ramin->gpuobj;
- *inst = cpramin->im_backing_start +
- (gpuobj->im_pramin->start - cpramin->im_pramin->start);
+ *inst = cpramin->im_backing_start + gpuobj->im_pramin->start;
return 0;
}
gpuobj->im_backing_start = b_offset;
}
+ gpuobj->pinst = gpuobj->im_pramin->start;
+ gpuobj->cinst = 0xdeadbeef;
+ gpuobj->vinst = gpuobj->im_backing_start;
+
if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) {
for (i = 0; i < gpuobj->im_pramin->size; i += 4)
nv_wo32(gpuobj, i, 0);
}
pramin = chan->ramin->gpuobj;
- ret = drm_mm_init(&chan->ramin_heap, pramin->im_pramin->start + base, size);
+ ret = drm_mm_init(&chan->ramin_heap, base, size);
if (ret) {
NV_ERROR(dev, "Error creating PRAMIN heap: %d\n", ret);
nouveau_gpuobj_ref_del(dev, &chan->ramin);
u32
nv_ro32(struct nouveau_gpuobj *gpuobj, u32 offset)
{
- struct drm_device *dev = gpuobj->dev;
- return nv_ri32(dev, gpuobj->im_pramin->start + offset);
+ return nv_ri32(gpuobj->dev, gpuobj->pinst + offset);
}
void
nv_wo32(struct nouveau_gpuobj *gpuobj, u32 offset, u32 val)
{
- struct drm_device *dev = gpuobj->dev;
- nv_wi32(dev, gpuobj->im_pramin->start + offset, val);
+ nv_wi32(gpuobj->dev, gpuobj->pinst + offset, val);
}
NV_DEBUG(dev, "ch%d\n", chan->id);
if (dev_priv->chipset == 0x50) {
- uint32_t ramin_poffset = chan->ramin->gpuobj->im_pramin->start;
- uint32_t ramin_voffset = chan->ramin->gpuobj->im_backing_start;
-
- ret = nouveau_gpuobj_new_fake(dev, ramin_poffset, ramin_voffset,
- 0x100, NVOBJ_FLAG_ZERO_ALLOC |
+ ret = nouveau_gpuobj_new_fake(dev, chan->ramin->gpuobj->pinst,
+ chan->ramin->gpuobj->vinst, 0x100,
+ NVOBJ_FLAG_ZERO_ALLOC |
NVOBJ_FLAG_ZERO_FREE, &ramfc,
&chan->ramfc);
if (ret)
return ret;
- ret = nouveau_gpuobj_new_fake(dev, ramin_poffset + 0x0400,
- ramin_voffset + 0x0400, 4096,
- 0, NULL, &chan->cache);
+ ret = nouveau_gpuobj_new_fake(dev, chan->ramin->gpuobj->pinst +
+ 0x0400,
+ chan->ramin->gpuobj->vinst +
+ 0x0400, 4096, 0, NULL,
+ &chan->cache);
if (ret)
return ret;
} else {