drm/i915: Initialize CHV digital lock detect threshold

Initialize lock detect threshold and select coarse threshold for the
case where M2 fraction division is disabled.

v2: Split the changes into multiple smaller patches (Ville)
v3: Clear out the old bits before we modify those bits as RMW (Ville)
v4: Reset coarse threshold when M2 fraction is enabled (Ville)

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
Reviewed-by: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 17b662f0849d352bb1288c8dafc2d9daa06a3765..4c64f17f188ddd26dfe4e557152b2ea9b20405ef 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1046,6 +1046,7 @@ enum skl_disp_power_wells {
 #define _CHV_PLL_DW9_CH0               0x8024
 #define _CHV_PLL_DW9_CH1               0x81A4
 #define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT             1 /* 3 bits */
+#define  DPIO_CHV_INT_LOCK_THRESHOLD_MASK              (7 << 1)
 #define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE        1 /* 1: coarse & 0 : fine  */
 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
 

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8676cb8deaf848168311d8f67ad8a8894b67185d..2eea258e58651a2a911d8e33b2f07c94642c0c16 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6207,6 +6207,15 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
                dpio_val |= DPIO_CHV_FRAC_DIV_EN;
        vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
 
+       /* Program digital lock detect threshold */
+       dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
+       dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
+                                       DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
+       dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
+       if (!bestm2_frac)
+               dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
+       vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
+
        /* Loop filter */
        refclk = i9xx_get_refclk(crtc, 0);
        loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |