drm/etnaviv: add function to construct MMUv2 init buffer
authorLucas Stach <l.stach@pengutronix.de>
Fri, 19 Aug 2016 21:53:59 +0000 (23:53 +0200)
committerLucas Stach <l.stach@pengutronix.de>
Thu, 15 Sep 2016 13:29:41 +0000 (15:29 +0200)
Both the safe/scratch address and the master TLB address are per pipe
with the CPU mapped registers not properly propagating to the
different translation units.

The only way to correctly configure all translation units is to have
a command stream snipped executed by the FE, before any other execution
can start.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
drivers/gpu/drm/etnaviv/etnaviv_buffer.c
drivers/gpu/drm/etnaviv/etnaviv_drv.h

index 46d13f49883ef05a91fce0ea71795cfe2ea15f44..47b93427fecb524c798cbbab9472ab8efa52b53a 100644 (file)
@@ -21,6 +21,7 @@
 
 #include "common.xml.h"
 #include "state.xml.h"
+#include "state_hi.xml.h"
 #include "state_3d.xml.h"
 #include "cmdstream.xml.h"
 
@@ -174,6 +175,39 @@ u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu)
        return buffer->user_size / 8;
 }
 
+u16 etnaviv_buffer_config_mmuv2(struct etnaviv_gpu *gpu, u32 mtlb_addr, u32 safe_addr)
+{
+       struct etnaviv_cmdbuf *buffer = gpu->buffer;
+
+       buffer->user_size = 0;
+
+       if (gpu->identity.features & chipFeatures_PIPE_3D) {
+               CMD_LOAD_STATE(buffer, VIVS_GL_PIPE_SELECT,
+                              VIVS_GL_PIPE_SELECT_PIPE(ETNA_PIPE_3D));
+               CMD_LOAD_STATE(buffer, VIVS_MMUv2_CONFIGURATION,
+                       mtlb_addr | VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K);
+               CMD_LOAD_STATE(buffer, VIVS_MMUv2_SAFE_ADDRESS, safe_addr);
+               CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
+               CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
+       }
+
+       if (gpu->identity.features & chipFeatures_PIPE_2D) {
+               CMD_LOAD_STATE(buffer, VIVS_GL_PIPE_SELECT,
+                              VIVS_GL_PIPE_SELECT_PIPE(ETNA_PIPE_2D));
+               CMD_LOAD_STATE(buffer, VIVS_MMUv2_CONFIGURATION,
+                       mtlb_addr | VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K);
+               CMD_LOAD_STATE(buffer, VIVS_MMUv2_SAFE_ADDRESS, safe_addr);
+               CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
+               CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
+       }
+
+       CMD_END(buffer);
+
+       buffer->user_size = ALIGN(buffer->user_size, 8);
+
+       return buffer->user_size / 8;
+}
+
 void etnaviv_buffer_end(struct etnaviv_gpu *gpu)
 {
        struct etnaviv_cmdbuf *buffer = gpu->buffer;
index 115c5bc6d7c8329312c04e49b06fe2100571b265..65e057639653026363b03c3f740c91f6bb4735d0 100644 (file)
@@ -96,6 +96,7 @@ struct drm_gem_object *etnaviv_gem_new(struct drm_device *dev,
 int etnaviv_gem_new_userptr(struct drm_device *dev, struct drm_file *file,
        uintptr_t ptr, u32 size, u32 flags, u32 *handle);
 u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu);
+u16 etnaviv_buffer_config_mmuv2(struct etnaviv_gpu *gpu, u32 mtlb_addr, u32 safe_addr);
 void etnaviv_buffer_end(struct etnaviv_gpu *gpu);
 void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, unsigned int event,
        struct etnaviv_cmdbuf *cmdbuf);