drm/i915: print Gen5+ CPU/PCH poison interrupts

This is bad news and shouldn't be happening.

V2: Rebase.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c79793ee868ba743cc1f9e489c4c667a4daa8264..dae8953d29128583514b5762a59e5a20e9e0a21d 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1023,6 +1023,9 @@ static void ivb_err_int_handler(struct drm_device *dev)
        struct drm_i915_private *dev_priv = dev->dev_private;
        u32 err_int = I915_READ(GEN7_ERR_INT);
 
+       if (err_int & ERR_INT_POISON)
+               DRM_ERROR("Poison interrupt\n");
+
        if (err_int & ERR_INT_FIFO_UNDERRUN_A)
                if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
                        DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
@@ -1043,6 +1046,9 @@ static void cpt_serr_int_handler(struct drm_device *dev)
        struct drm_i915_private *dev_priv = dev->dev_private;
        u32 serr_int = I915_READ(SERR_INT);
 
+       if (serr_int & SERR_INT_POISON)
+               DRM_ERROR("PCH poison interrupt\n");
+
        if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
                if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
                                                          false))
@@ -1261,6 +1267,9 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
        if (de_iir & DE_PIPEB_VBLANK)
                drm_handle_vblank(dev, 1);
 
+       if (de_iir & DE_POISON)
+               DRM_ERROR("Poison interrupt\n");
+
        if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
                if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
                        DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
@@ -2496,7 +2505,7 @@ static void ibx_irq_postinstall(struct drm_device *dev)
 
        if (HAS_PCH_IBX(dev)) {
                mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
-                      SDE_TRANSA_FIFO_UNDER;
+                      SDE_TRANSA_FIFO_UNDER | SDE_POISON;
        } else {
                mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
 
@@ -2517,7 +2526,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
        u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
                           DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
                           DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
-                          DE_PIPEA_FIFO_UNDERRUN;
+                          DE_PIPEA_FIFO_UNDERRUN | DE_POISON;
        u32 render_irqs;
 
        dev_priv->irq_mask = ~display_mask;

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 32f970d2fd5186f84c63c42a5deb36333fbd6450..9093d6669560a1d601d2c6a3b3fe422701dcaf56 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -640,6 +640,7 @@
 
 #define ERROR_GEN6     0x040a0
 #define GEN7_ERR_INT   0x44040
+#define   ERR_INT_POISON               (1<<31)
 #define   ERR_INT_MMIO_UNCLAIMED       (1<<13)
 #define   ERR_INT_FIFO_UNDERRUN_C      (1<<6)
 #define   ERR_INT_FIFO_UNDERRUN_B      (1<<3)
@@ -3810,6 +3811,7 @@
 #define SDEIER  0xc400c
 
 #define SERR_INT                       0xc4040
+#define  SERR_INT_POISON               (1<<31)
 #define  SERR_INT_TRANS_C_FIFO_UNDERRUN        (1<<6)
 #define  SERR_INT_TRANS_B_FIFO_UNDERRUN        (1<<3)
 #define  SERR_INT_TRANS_A_FIFO_UNDERRUN        (1<<0)