MIPS: Add SMP_ICACHE_FLUSH for the Cavium CPU family.

Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h
index 86557b5d1b3f152932d9fe02744cad4eb4ec6316..40e5ef1d4d26b195b205433c5d14a5c2ba382e35 100644 (file)
--- a/arch/mips/include/asm/smp.h
+++ b/arch/mips/include/asm/smp.h
@@ -37,6 +37,9 @@ extern int __cpu_logical_map[NR_CPUS];
 
 #define SMP_RESCHEDULE_YOURSELF        0x1     /* XXX braindead */
 #define SMP_CALL_FUNCTION      0x2
+/* Octeon - Tell another core to flush its icache */
+#define SMP_ICACHE_FLUSH       0x4
+
 
 extern void asmlinkage smp_bootstrap(void);