igb: add counter for dma out of sync errors
authorAlexander Duyck <alexander.h.duyck@intel.com>
Fri, 6 Feb 2009 23:19:08 +0000 (23:19 +0000)
committerDavid S. Miller <davem@davemloft.net>
Sat, 7 Feb 2009 10:43:08 +0000 (02:43 -0800)
Add a counter for dma out of sync errors reported via interrupt.

Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/igb/e1000_defines.h
drivers/net/igb/e1000_hw.h
drivers/net/igb/igb_ethtool.c
drivers/net/igb/igb_main.c

index 54a1489233867404fcb5ca4be7fc1899fced8328..bff62dd84312868aad28e36b7d100a6344f4c28f 100644 (file)
 /* LAN connected device generates an interrupt */
 #define E1000_ICR_PHYINT        0x00001000
 #define E1000_ICR_EPRST         0x00100000 /* ME handware reset occurs */
+#define E1000_ICR_DOUTSYNC      0x10000000 /* NIC DMA out of sync */
 
 /* Extended Interrupt Cause Read */
 #define E1000_EICR_RX_QUEUE0    0x00000001 /* Rx Queue 0 Interrupt */
     E1000_IMS_TXDW   |    \
     E1000_IMS_RXDMT0 |    \
     E1000_IMS_RXSEQ  |    \
-    E1000_IMS_LSC)
+    E1000_IMS_LSC    |    \
+    E1000_IMS_DOUTSYNC)
 
 /* Interrupt Mask Set */
 #define E1000_IMS_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */
 #define E1000_IMS_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
 #define E1000_IMS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
 #define E1000_IMS_RXT0      E1000_ICR_RXT0      /* rx timer intr */
+#define E1000_IMS_DOUTSYNC  E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
 
 /* Extended Interrupt Mask Set */
 #define E1000_EIMS_TCP_TIMER    E1000_EICR_TCP_TIMER /* TCP Timer */
 /* Interrupt Cause Set */
 #define E1000_ICS_LSC       E1000_ICR_LSC       /* Link Status Change */
 #define E1000_ICS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
+#define E1000_ICS_DOUTSYNC  E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
 
 /* Extended Interrupt Cause Set */
 
index acb42a21e95c1349a5887fb1fbf02e9a23ea7a5a..62ccd495356e9d9ab832d8bb9c2adfe203194bb3 100644 (file)
@@ -359,6 +359,7 @@ struct e1000_hw_stats {
        u64 lenerrs;
        u64 scvpc;
        u64 hrmpc;
+       u64 doosync;
 };
 
 struct e1000_phy_stats {
index 33c23a117fe6223db8f7b9f49f23dfa57988e808..de09430ce7f55f733a0f61ef30319c47ade24f3b 100644 (file)
@@ -88,6 +88,7 @@ static const struct igb_stats igb_gstrings_stats[] = {
        { "rx_long_byte_count", IGB_STAT(stats.gorc) },
        { "rx_csum_offload_good", IGB_STAT(hw_csum_good) },
        { "rx_csum_offload_errors", IGB_STAT(hw_csum_err) },
+       { "tx_dma_out_of_sync", IGB_STAT(stats.doosync) },
        { "alloc_rx_buff_failed", IGB_STAT(alloc_rx_buff_failed) },
        { "tx_smbus", IGB_STAT(stats.mgptc) },
        { "rx_smbus", IGB_STAT(stats.mgprc) },
index 8c27e0a23dff30b7fba07a535787469a0dbf2e74..c05ca3461f60e5b147f76391f0274421570e89a8 100644 (file)
@@ -689,7 +689,7 @@ static void igb_irq_enable(struct igb_adapter *adapter)
                wr32(E1000_EIAC, adapter->eims_enable_mask);
                wr32(E1000_EIAM, adapter->eims_enable_mask);
                wr32(E1000_EIMS, adapter->eims_enable_mask);
-               wr32(E1000_IMS, E1000_IMS_LSC);
+               wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
        } else {
                wr32(E1000_IMS, IMS_ENABLE_MASK);
                wr32(E1000_IAM, IMS_ENABLE_MASK);
@@ -3287,6 +3287,11 @@ static irqreturn_t igb_msix_other(int irq, void *data)
        u32 icr = rd32(E1000_ICR);
 
        /* reading ICR causes bit 31 of EICR to be cleared */
+
+       if(icr & E1000_ICR_DOUTSYNC) {
+               /* HW is reporting DMA is out of sync */
+               adapter->stats.doosync++;
+       }
        if (!(icr & E1000_ICR_LSC))
                goto no_link_interrupt;
        hw->mac.get_link_status = 1;
@@ -3295,7 +3300,7 @@ static irqreturn_t igb_msix_other(int irq, void *data)
                mod_timer(&adapter->watchdog_timer, jiffies + 1);
        
 no_link_interrupt:
-       wr32(E1000_IMS, E1000_IMS_LSC);
+       wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
        wr32(E1000_EIMS, adapter->eims_other);
 
        return IRQ_HANDLED;
@@ -3499,6 +3504,11 @@ static irqreturn_t igb_intr_msi(int irq, void *data)
 
        igb_write_itr(adapter->rx_ring);
 
+       if(icr & E1000_ICR_DOUTSYNC) {
+               /* HW is reporting DMA is out of sync */
+               adapter->stats.doosync++;
+       }
+
        if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
                hw->mac.get_link_status = 1;
                if (!test_bit(__IGB_DOWN, &adapter->state))
@@ -3534,6 +3544,11 @@ static irqreturn_t igb_intr(int irq, void *data)
        if (!(icr & E1000_ICR_INT_ASSERTED))
                return IRQ_NONE;
 
+       if(icr & E1000_ICR_DOUTSYNC) {
+               /* HW is reporting DMA is out of sync */
+               adapter->stats.doosync++;
+       }
+
        eicr = rd32(E1000_EICR);
 
        if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {