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ARM: mach-shmobile: sh73a0 CPGA fix for FRQCRA M3
authorMagnus Damm <damm@opensource.se>
Tue, 18 Jan 2011 08:53:06 +0000 (08:53 +0000)
committerPaul Mundt <lethal@linux-sh.org>
Tue, 18 Jan 2011 11:01:10 +0000 (20:01 +0900)
Fix the M3 field offset for the FRQCRA register
in the sh73a0 CPGA. It should be 12, not 8.

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
arch/arm/mach-shmobile/clock-sh73a0.c patch | blob | blame | history

diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index aa1c51dc6d771ae3a488799d5a03161d38d90669..af7d4c20ad7bd2a48904da0f419a5da32be396fc 100644 (file)
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -212,7 +212,7 @@ enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
 static struct clk div4_clks[DIV4_NR] = {
        [DIV4_I] = DIV4(FRQCRA, 20, 0xfff, CLK_ENABLE_ON_INIT),
        [DIV4_ZG] = DIV4(FRQCRA, 16, 0xbff, CLK_ENABLE_ON_INIT),
-       [DIV4_M3] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT),
+       [DIV4_M3] = DIV4(FRQCRA, 12, 0xfff, CLK_ENABLE_ON_INIT),
        [DIV4_B] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT),
        [DIV4_M1] = DIV4(FRQCRA, 4, 0xfff, 0),
        [DIV4_M2] = DIV4(FRQCRA, 0, 0xfff, 0),