ifeq ($(LOCAL_KK),0)
GPU_DRV_VERSION?=r6p1
GPU_DRV_VERSION:=$(strip $(GPU_DRV_VERSION))
+MALI_PLAT=hardware/arm/gpu/utgard/platform
MALI=hardware/arm/gpu/utgard/${GPU_DRV_VERSION}
MALI_OUT=$(PRODUCT_OUT)/obj/mali
KERNEL_ARCH ?= arm
rm $(MALI_OUT) -rf
mkdir -p $(MALI_OUT)
cp $(MALI)/* $(MALI_OUT)/ -airf
+ cp $(MALI_PLAT) $(MALI_OUT)/ -airf
@echo "make mali module KERNEL_ARCH is $(KERNEL_ARCH)"
@echo "make mali module MALI_OUT is $(MALI_OUT)"
@echo "make mali module MAKE is $(MAKE)"
@echo "GPU_DRV_VERSION is ${GPU_DRV_VERSION}"
$(MAKE) -C $(shell pwd)/$(PRODUCT_OUT)/obj/KERNEL_OBJ M=$(shell pwd)/$(MALI_OUT)/ \
- ARCH=$(KERNEL_ARCH) CROSS_COMPILE=$(PREFIX_CROSS_COMPILE) CONFIG_MALI400=m CONFIG_MALI450=m \
+ ARCH=$(KERNEL_ARCH) CROSS_COMPILE=$(PREFIX_CROSS_COMPILE) CONFIG_MALI400=m CONFIG_MALI450=m \
EXTRA_CFLAGS="-DCONFIG_MALI400=m -DCONFIG_MALI450=m" \
CONFIG_GPU_THERMAL=y CONFIG_AM_VDEC_H264_4K2K=y modules
#
# This file is called by the Linux build system.
-include $(src)/Kbuild.amlogic
-# set up defaults if not defined by the user
-TIMESTAMP ?= default
-ifeq ($(CONFIG_UMP), m)
- USING_UMP ?= 1
-else
- USING_UMP ?= 0
-endif
-ifneq ($(KBUILD_SRC),)
- ifneq ($(wildcard $(KBUILD_SRC)/$(src)),)
- TOP_KBUILD_SRC := $(KBUILD_SRC)/
- endif
-endif
+# set up defaults if not defined by the user
+include $(src)/platform/Kbuild.amlogic
+TIMESTAMP ?= default
OS_MEMORY_KERNEL_BUFFER_SIZE_IN_MB ?= 16
-
-#USING_GPU_UTILIZATION ?= 0
-#PROFILING_SKIP_PP_JOBS ?= 0
-#PROFILING_SKIP_PP_AND_GP_JOBS ?= 0
-ifeq ($(CONFIG_MALI_DVFS),y)
- ccflags-y += -DCONFIG_MALI_DVFS
- USING_GPU_UTILIZATION=0
- USING_DVFS=1
-else
- USING_GPU_UTILIZATION=1
- USING_DVFS=0
-endif
+USING_GPU_UTILIZATION ?= 0
PROFILING_SKIP_PP_JOBS ?= 0
PROFILING_SKIP_PP_AND_GP_JOBS ?= 0
-############## Kasin Added, for platform. ################
-
-ifeq ($(CONFIG_MALI400_DEBUG),y)
- BUILD ?= debug
-else
- BUILD ?= release
- #ldflags-y += --strip-debug
-
-endif
-##################### end Kasin Added. ###################
-
MALI_PP_SCHEDULER_FORCE_NO_JOB_OVERLAP ?= 0
MALI_PP_SCHEDULER_KEEP_SUB_JOB_STARTS_ALIGNED ?= 0
MALI_PP_SCHEDULER_FORCE_NO_JOB_OVERLAP_BETWEEN_APPS ?= 0
MALI_UPPER_HALF_SCHEDULING ?= 1
-
-############## Kasin Added, useless now. ################
-# Get path to driver source from Linux build system
-DRIVER_DIR=$(src)
-##################### end Kasin Added. ###################
-
MALI_ENABLE_CPU_CYCLES ?= 0
# For customer releases the Linux Device Drivers will be provided as ARM proprietary and GPL releases:
# The ARM proprietary product will only include the license/proprietary directory
# The GPL product will only include the license/gpl directory
-ifeq ($(wildcard $(TOP_KBUILD_SRC)$(DRIVER_DIR)/linux/license/gpl/*),)
- ccflags-y += -I$(TOP_KBUILD_SRC)$(DRIVER_DIR)/linux/license/proprietary
+ifeq ($(wildcard $(src)/linux/license/gpl/*),)
+ ccflags-y += -I$(src)/linux/license/proprietary
ifeq ($(CONFIG_MALI400_PROFILING),y)
$(error Profiling is incompatible with non-GPL license)
endif
endif
$(error Linux Device integration is incompatible with non-GPL license)
else
- ccflags-y += -I$(TOP_KBUILD_SRC)$(DRIVER_DIR)/linux/license/gpl
+ ccflags-y += -I$(src)/linux/license/gpl
endif
ifeq ($(USING_GPU_UTILIZATION), 1)
linux/mali_pmu_power_up_down.o \
__malidrv_build_info.o
-############## Kasin Added, for platform. ################
-ifeq (true,false)
-mali-y += \
- platform/meson_main.o \
- platform/mali_pm_device.o \
- platform/mali_clock.o \
- platform/mpgpu.o
-else
-mali-y += \
- platform/mali_pm_device.o \
- platform/meson_bu/meson_main2.o \
- platform/meson_bu/mali_clock.o \
- platform/meson_bu/mpgpu.o \
- platform/meson_bu/platform_gx.o
-endif
-ifeq ($(CONFIG_MALI_DVFS),y)
- mali-y += platform/meson_bu/mali_dvfs.o
-else
- mali-y += platform/meson_bu/scaling.o
-endif
-
-ifeq ($(TARGET_PLATFORM),meson_m400)
-MALI_PLATFORM_FILES:= \
- platform/meson_m400/mali_fix.o \
- platform/meson_m400/mali_platform.o \
- platform/meson_m400/platform_mx.o
-endif
-
-ifeq ($(TARGET_PLATFORM),meson_m450)
-ccflags-y += -DCONFIG_MALI450=y
-mali-y += \
- platform/meson_m450/scaling.o
-
-mali-$(CONFIG_ARCH_MESON) += \
- platform/meson_m450/platform_m8.o
-
-mali-$(CONFIG_ARCH_MESON8) += \
- platform/meson_m450/platform_m8.o
-
-mali-$(CONFIG_ARCH_MESON6TVD) += \
- platform/meson_m450/platform_m6tvd.o
-
-mali-$(CONFIG_ARCH_MESON8B) += \
- platform/meson_m450/platform_m8b.o
-
-mali-$(CONFIG_ARCH_MESONG9TV) += \
- platform/meson_m450/platform_m8.o
-
-mali-$(CONFIG_ARCH_MESONG9BB) += \
- platform/meson_m450/platform_m8b.o
-endif
-##################### end Kasin Added. ###################
-
ifneq ($(wildcard $(src)/linux/mali_slp_global_lock.c),)
mali-y += linux/mali_slp_global_lock.o
endif
ccflags-y += -DMALI_OS_MEMORY_KERNEL_BUFFER_SIZE_IN_MB=$(OS_MEMORY_KERNEL_BUFFER_SIZE_IN_MB)
ccflags-y += -DUSING_GPU_UTILIZATION=$(USING_GPU_UTILIZATION)
ccflags-y += -DMALI_ENABLE_CPU_CYCLES=$(MALI_ENABLE_CPU_CYCLES)
-ccflags-y += -DMALI_FAKE_PLATFORM_DEVICE
ifeq ($(MALI_UPPER_HALF_SCHEDULING),1)
ccflags-y += -DMALI_UPPER_HALF_SCHEDULING
ifeq ($(MALI_PLATFORM_FILES),)
ccflags-$(CONFIG_MALI400_UMP) += -I$(src)/../ump/include/
else
-ccflags-$(CONFIG_MALI400_UMP) += -I$(src)/../ump/include/ump
-ccflags-$(CONFIG_MALI400_DEBUG) += -DDEBUG
+ccflags-$(CONFIG_MALI400_UMP) += -I$(src)/../../ump/include/ump
endif
+ccflags-$(CONFIG_MALI400_DEBUG) += -DDEBUG
# Use our defines when compiling
ccflags-y += -I$(src) -I$(src)/include -I$(src)/common -I$(src)/linux -I$(src)/platform
# Get subversion revision number, fall back to only ${MALI_RELEASE_NAME} if no svn info is available
-MALI_RELEASE_NAME=$(shell cat $(TOP_KBUILD_SRC)$(DRIVER_DIR)/.version 2> /dev/null)
+MALI_RELEASE_NAME=$(shell cat $(src)/.version 2> /dev/null)
-SVN_INFO = (cd $(TOP_KBUILD_SRC)$(DRIVER_DIR); svn info 2>/dev/null)
+SVN_INFO = (cd $(src); svn info 2>/dev/null)
ifneq ($(shell $(SVN_INFO) 2>/dev/null),)
# SVN detected
REPO_URL := $(shell $(SVN_INFO) | grep '^URL: ' | cut -d: -f2- | cut -b2-)
else # SVN
-GIT_REV := $(shell cd $(TOP_KBUILD_SRC)$(DRIVER_DIR); git describe --always 2>/dev/null)
+GIT_REV := $(shell cd $(src); git describe --always 2>/dev/null)
ifneq ($(GIT_REV),)
# Git detected
DRIVER_REV := $(MALI_RELEASE_NAME)-$(GIT_REV)
-CHANGE_DATE := $(shell cd $(TOP_KBUILD_SRC)$(DRIVER_DIR); git log -1 --format="%ci")
+CHANGE_DATE := $(shell cd $(src); git log -1 --format="%ci")
CHANGED_REVISION := $(GIT_REV)
-REPO_URL := $(shell cd $(TOP_KBUILD_SRC)$(DRIVER_DIR); git describe --all --always 2>/dev/null)
+REPO_URL := $(shell cd $(src); git describe --all --always 2>/dev/null)
else # Git
# No Git or SVN detected
ccflags-y += -DSVN_REV_STRING=\"$(DRIVER_REV)\"
VERSION_STRINGS :=
-VERSION_STRINGS += API_VERSION=$(shell cd $(TOP_KBUILD_SRC)$(DRIVER_DIR); grep "\#define _MALI_API_VERSION" $(FILES_PREFIX)include/linux/mali/mali_utgard_uk_types.h | cut -d' ' -f 3 )
+VERSION_STRINGS += API_VERSION=$(shell cd $(src); grep "\#define _MALI_API_VERSION" $(FILES_PREFIX)include/linux/mali/mali_utgard_uk_types.h | cut -d' ' -f 3 )
VERSION_STRINGS += REPO_URL=$(REPO_URL)
VERSION_STRINGS += REVISION=$(DRIVER_REV)
VERSION_STRINGS += CHANGED_REVISION=$(CHANGED_REVISION)
VERSION_STRINGS += MALI_UPPER_HALF_SCHEDULING=$(MALI_UPPER_HALF_SCHEDULING)
# Create file with Mali driver configuration
-$(TOP_KBUILD_SRC)$(DRIVER_DIR)/__malidrv_build_info.c:
- @echo 'const char *__malidrv_build_info(void) { return "malidrv: $(VERSION_STRINGS)";}' > $(TOP_KBUILD_SRC)$(DRIVER_DIR)/__malidrv_build_info.c
+$(src)/__malidrv_build_info.c:
+ @echo 'const char *__malidrv_build_info(void) { return "malidrv: $(VERSION_STRINGS)";}' > $(src)/__malidrv_build_info.c
+++ /dev/null
-############## Kasin Added, for platform. ################
-
-ifndef CONFIG_MALI_DMA_BUF_MAP_ON_ATTACH
- ccflags-y += -DCONFIG_MALI_DMA_BUF_MAP_ON_ATTACH=y
-endif
-
-ccflags-y += -DCONFIG_MALI_DT=y
-ccflags-y += -DMESON_CPU_TYPE=0x80
-ccflags-y += -DMESON_CPU_TYPE_MESON6=0x60
-ccflags-y += -DMESON_CPU_TYPE_MESON6TVD=0x75
-ccflags-y += -DMESON_CPU_TYPE_MESON8=0x80
-ccflags-y += -DMESON_CPU_TYPE_MESON8B=0x8B
-
-USE_GPPLL?=0
-ifdef CONFIG_AM_VIDEO
- USE_GPPLL:=1
-endif
-
-ccflags-y += -DAMLOGIC_GPU_USE_GPPLL=$(USE_GPPLL)
+++ /dev/null
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#include <plat/io.h>
-#endif
-
-#include <linux/io.h>
-
-#include <asm/io.h>
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 29))
-#include <linux/amlogic/iomap.h>
-#endif
-#include "meson_main.h"
-
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6TVD
-
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 29))
-#define HHI_MALI_CLK_CNTL 0x106C
-#define mplt_read(r) aml_read_cbus((r))
-#define mplt_write(v, r) aml_write_cbus((r), (v))
-#define mplt_setbits(r, m) aml_write_cbus((r), (aml_read_cbus(r) | (m)));
-#define mplt_clrbits(r, m) aml_write_cbus((r), (aml_read_cbus(r) & (~(m))));
-#else
-#define mplt_read(r) aml_read_reg32((P_##r))
-#define mplt_write(v, r) aml_write_reg32((P_##r), (v))
-#define mplt_setbits(r, m) aml_write_reg32((P_##r), (aml_read_reg32(P_##r) | (m)));
-#define mplt_clrbits(r, m) aml_write_reg32((P_##r), (aml_read_reg32(P_##r) & (~(m))));
-#endif
-#define FCLK_MPLL2 (2 << 9)
-static DEFINE_SPINLOCK(lock);
-static mali_plat_info_t* pmali_plat = NULL;
-static u32 mali_extr_backup = 0;
-static u32 mali_extr_sample_backup = 0;
-
-int mali_clock_init(mali_plat_info_t* mali_plat)
-{
- u32 def_clk_data;
- if (mali_plat == NULL) {
- printk(" Mali platform data is NULL!!!\n");
- return -1;
- }
-
- pmali_plat = mali_plat;
- if (pmali_plat->have_switch) {
- def_clk_data = pmali_plat->clk[pmali_plat->def_clock];
- mplt_write(def_clk_data | (def_clk_data << 16), HHI_MALI_CLK_CNTL);
- mplt_setbits(HHI_MALI_CLK_CNTL, 1 << 24);
- mplt_setbits(HHI_MALI_CLK_CNTL, 1 << 8);
- } else {
- mali_clock_set(pmali_plat->def_clock);
- }
-
- mali_extr_backup = pmali_plat->clk[pmali_plat->clk_len - 1];
- mali_extr_sample_backup = pmali_plat->clk_sample[pmali_plat->clk_len - 1];
- return 0;
-}
-
-int mali_clock_critical(critical_t critical, size_t param)
-{
- int ret = 0;
- unsigned long flags;
-
- spin_lock_irqsave(&lock, flags);
- ret = critical(param);
- spin_unlock_irqrestore(&lock, flags);
- return ret;
-}
-
-static int critical_clock_set(size_t param)
-{
- unsigned int idx = param;
- if (pmali_plat->have_switch) {
- u32 clk_value;
- mplt_setbits(HHI_MALI_CLK_CNTL, 1 << 31);
- clk_value = mplt_read(HHI_MALI_CLK_CNTL) & 0xffff0000;
- clk_value = clk_value | pmali_plat->clk[idx] | (1 << 8);
- mplt_write(clk_value, HHI_MALI_CLK_CNTL);
- mplt_clrbits(HHI_MALI_CLK_CNTL, 1 << 31);
- } else {
- mplt_clrbits(HHI_MALI_CLK_CNTL, 1 << 8);
- mplt_clrbits(HHI_MALI_CLK_CNTL, (0x7F | (0x7 << 9)));
- mplt_write(pmali_plat->clk[idx], HHI_MALI_CLK_CNTL);
- mplt_setbits(HHI_MALI_CLK_CNTL, 1 << 8);
- }
- return 0;
-}
-
-int mali_clock_set(unsigned int clock)
-{
- return mali_clock_critical(critical_clock_set, (size_t)clock);
-}
-
-void disable_clock(void)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&lock, flags);
- mplt_clrbits(HHI_MALI_CLK_CNTL, 1 << 8);
- spin_unlock_irqrestore(&lock, flags);
-}
-
-void enable_clock(void)
-{
- u32 ret;
- unsigned long flags;
-
- spin_lock_irqsave(&lock, flags);
- mplt_setbits(HHI_MALI_CLK_CNTL, 1 << 8);
- ret = mplt_read(HHI_MALI_CLK_CNTL) & (1 << 8);
- spin_unlock_irqrestore(&lock, flags);
-}
-
-u32 get_mali_freq(u32 idx)
-{
- if (!mali_pm_statue) {
- return pmali_plat->clk_sample[idx];
- } else {
- return 0;
- }
-}
-
-void set_str_src(u32 data)
-{
-#if 0
- if (data == 11) {
- writel(0x0004d000, (u32*)P_HHI_MPLL_CNTL9);
- } else if (data > 11) {
- writel(data, (u32*)P_HHI_MPLL_CNTL9);
- }
-#endif
- if (data == 0) {
- pmali_plat->clk[pmali_plat->clk_len - 1] = mali_extr_backup;
- pmali_plat->clk_sample[pmali_plat->clk_len - 1] = mali_extr_sample_backup;
- } else if (data > 10) {
- pmali_plat->clk_sample[pmali_plat->clk_len - 1] = 600;
- pmali_plat->clk[pmali_plat->clk_len - 1] = FCLK_MPLL2;
- }
-}
-#endif
+++ /dev/null
-#ifndef _MALI_CLOCK_H_
-#define _MALI_CLOCK_H_
-
-typedef int (*critical_t)(size_t param);
-int mali_clock_critical(critical_t critical, size_t param);
-
-int mali_clock_init(mali_plat_info_t*);
-int mali_clock_set(unsigned int index);
-void disable_clock(void);
-void enable_clock(void);
-u32 get_mali_freq(u32 idx);
-void set_str_src(u32 data);
-#endif /* _MALI_CLOCK_H_ */
+++ /dev/null
-/*
- * mali_platform.h
- *
- * Created on: Nov 8, 2013
- * Author: amlogic
- */
-
-#include <linux/kernel.h>
-#ifndef MALI_PLATFORM_H_
-#define MALI_PLATFORM_H_
-
-extern u32 mali_gp_reset_fail;
-extern u32 mali_core_timeout;
-
-#endif /* MALI_PLATFORM_H_ */
+++ /dev/null
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/module.h> /* kernel module definitions */
-#include <linux/ioport.h> /* request_mem_region */
-#include <linux/slab.h>
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#endif
-#include "meson_main.h"
-#include <common/mali_kernel_common.h>
-#include <common/mali_osk_profiling.h>
-#include <common/mali_pmu.h>
-#include <linux/mali/mali_utgard.h>
-
-static int mali_os_suspend(struct device *device)
-{
- int ret = 0;
-
- MALI_DEBUG_PRINT(4, ("mali_os_suspend() called\n"));
- ret = mali_deep_suspend(device);
-
- return ret;
-}
-
-static int mali_os_resume(struct device *device)
-{
- int ret = 0;
-
- MALI_DEBUG_PRINT(4, ("mali_os_resume() called\n"));
-
- ret = mali_deep_resume(device);
-
- return ret;
-}
-
-static int mali_os_freeze(struct device *device)
-{
- int ret = 0;
-
- MALI_DEBUG_PRINT(4, ("mali_os_freeze() called\n"));
-
- mali_dev_freeze();
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->freeze)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->freeze(device);
- }
-
- return ret;
-}
-//copy from r4p1 linux/mali_pmu_power_up_down.c
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
-static int mali_pmu_powerup(void)
-{
- struct mali_pmu_core *pmu = mali_pmu_get_global_pmu_core();
-
- MALI_DEBUG_PRINT(5, ("Mali PMU: Power up\n"));
-
- MALI_DEBUG_ASSERT_POINTER(pmu);
- if (NULL == pmu) {
- return -ENXIO;
- }
-
- mali_pmu_power_up_all(pmu);
-
- return 0;
-}
-#endif
-
-static int mali_os_thaw(struct device *device)
-{
- int ret = 0;
-
- MALI_DEBUG_PRINT(4, ("mali_os_thaw() called\n"));
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
- enable_clock();
- mali_pmu_powerup();
-#endif
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->thaw)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->thaw(device);
- }
-
- return ret;
-}
-
-static int mali_os_restore(struct device *device)
-{
- MALI_DEBUG_PRINT(4, ("mali_os_thaw() called\n"));
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
- mali_dev_restore();
-#endif
- return mali_os_resume(device);
-}
-
-#ifdef CONFIG_PM_RUNTIME
-#if 0
-static int mali_runtime_suspend(struct device *device)
-{
- int ret = 0;
-
- MALI_DEBUG_PRINT(4, ("mali_runtime_suspend() called\n"));
- ret = mali_light_suspend(device);
-
- return ret;
-}
-
-static int mali_runtime_resume(struct device *device)
-{
- int ret = 0;
-
- MALI_DEBUG_PRINT(4, ("mali_run time_resume() called\n"));
- ret = mali_light_resume(device);
-
- return ret;
-}
-
-static int mali_runtime_idle(struct device *device)
-{
- MALI_DEBUG_PRINT(4, ("mali_runtime_idle() called\n"));
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_idle)
- {
- /* Need to notify Mali driver about this event */
- int ret = device->driver->pm->runtime_idle(device);
- if (0 != ret)
- {
- return ret;
- }
- }
-
- pm_runtime_suspend(device);
-
- return 0;
-}
-#endif
-#endif
-
-static struct dev_pm_ops mali_gpu_device_type_pm_ops =
-{
- .suspend = mali_os_suspend,
- .resume = mali_os_resume,
- .freeze = mali_os_freeze,
- .thaw = mali_os_thaw,
- .restore = mali_os_restore,
-#if 0//def CONFIG_PM_RUNTIME
- .runtime_suspend = mali_runtime_suspend,
- .runtime_resume = mali_runtime_resume,
- .runtime_idle = mali_runtime_idle,
-#endif
-};
-
-struct device_type mali_pm_device =
-{
- .pm = &mali_gpu_device_type_pm_ops,
-};
+++ /dev/null
-/*
- * Copyright (C) 2013 ARM Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
- *
- * A copy of the licence is included with the program, and can also be obtained from Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-/**
- * @file arm_core_scaling.h
- * Example core scaling policy.
- */
-
-#ifndef __ARM_CORE_SCALING_H__
-#define __ARM_CORE_SCALING_H__
-
-#include <linux/types.h>
-#include <linux/workqueue.h>
-#include <linux/clk-provider.h>
-#include <linux/clk.h>
-
-enum mali_scale_mode_t {
- MALI_PP_SCALING = 0,
- MALI_PP_FS_SCALING,
- MALI_SCALING_DISABLE,
- MALI_TURBO_MODE,
- MALI_SCALING_MODE_MAX
-};
-
-typedef struct mali_dvfs_threshold_table {
- uint32_t freq_index;
- uint32_t voltage;
- uint32_t keep_count;
- uint32_t downthreshold;
- uint32_t upthreshold;
- uint32_t clk_freq;
- const char *clk_parent;
- struct clk *clkp_handle;
- uint32_t clkp_freq;
-} mali_dvfs_threshold_table;
-
-/**
- * restrictions on frequency and number of pp.
- */
-typedef struct mali_scale_info_t {
- u32 minpp;
- u32 maxpp;
- u32 minclk;
- u32 maxclk;
-} mali_scale_info_t;
-
-/**
- * Platform spesific data for meson chips.
- */
-typedef struct mali_plat_info_t {
- u32 cfg_pp; /* number of pp. */
- u32 cfg_min_pp;
- u32 turbo_clock; /* reserved clock src. */
- u32 def_clock; /* gpu clock used most of time.*/
- u32 cfg_clock; /* max clock could be used.*/
- u32 cfg_clock_bkup; /* same as cfg_clock, for backup. */
- u32 cfg_min_clock;
-
- u32 sc_mpp; /* number of pp used most of time.*/
- u32 bst_gpu; /* threshold for boosting gpu. */
- u32 bst_pp; /* threshold for boosting PP. */
-
- u32 *clk;
- u32 *clk_sample;
- u32 clk_len;
- u32 have_switch; /* have clock gate switch or not. */
-
- mali_dvfs_threshold_table *dvfs_table;
- struct mali_gpu_clk_item *clk_items;
- u32 dvfs_table_size;
-
- mali_scale_info_t scale_info;
- u32 maxclk_sysfs;
- u32 maxpp_sysfs;
-
- /* set upper limit of pp or frequency, for THERMAL thermal or band width saving.*/
- u32 limit_on;
-
- /* for boost up gpu by user. */
- void (*plat_preheat)(void);
-
- struct platform_device *pdev;
- void __iomem *reg_base_hiubus;
- void __iomem *reg_base_aobus;
- struct work_struct wq_work;
- struct clk *clk_mali;
- struct clk *clk_mali_0;
- struct clk *clk_mali_1;
-} mali_plat_info_t;
-mali_plat_info_t* get_mali_plat_data(void);
-
-/**
- * Initialize core scaling policy.
- *
- * @note The core scaling policy will assume that all PP cores are on initially.
- *
- * @param num_pp_cores Total number of PP cores.
- */
-int mali_core_scaling_init(mali_plat_info_t*);
-
-/**
- * Terminate core scaling policy.
- */
-void mali_core_scaling_term(void);
-
-/**
- * cancel and flush scaling job queue.
- */
-void flush_scaling_job(void);
-
-/* get current state(pp, clk). */
-void get_mali_rt_clkpp(u32* clk, u32* pp);
-u32 set_mali_rt_clkpp(u32 clk, u32 pp, u32 flush);
-void revise_mali_rt(void);
-/* get max gpu clk level of this chip*/
-int get_gpu_max_clk_level(void);
-
-/* get or set the scale mode. */
-u32 get_mali_schel_mode(void);
-void set_mali_schel_mode(u32 mode);
-
-/* for frequency reporter in DS-5 streamline. */
-u32 get_current_frequency(void);
-void mali_dev_freeze(void);
-void mali_dev_restore(void);
-
-extern int mali_pm_statue;
-#endif /* __ARM_CORE_SCALING_H__ */
+++ /dev/null
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <linux/clk-provider.h>
-#include <linux/clk.h>
-#include <linux/of_address.h>
-#include <linux/delay.h>
-#include <linux/mali/mali_utgard.h>
-#include <linux/amlogic/cpu_version.h>
-#include "mali_scaling.h"
-#include "mali_clock.h"
-
-#ifndef AML_CLK_LOCK_ERROR
-#define AML_CLK_LOCK_ERROR 1
-#endif
-#define GXBBM_MAX_GPU_FREQ 700000000UL
-struct clk;
-static unsigned gpu_dbg_level = 0;
-module_param(gpu_dbg_level, uint, 0644);
-MODULE_PARM_DESC(gpu_dbg_level, "gpu debug level");
-
-#define gpu_dbg(level, fmt, arg...) \
- do { \
- if (gpu_dbg_level >= (level)) \
- printk("gpu_debug"fmt , ## arg); \
- } while (0)
-
-#define GPU_CLK_DBG(fmt, arg...)
-
-//disable print
-#define _dev_info(...)
-
-//static DEFINE_SPINLOCK(lock);
-static mali_plat_info_t* pmali_plat = NULL;
-//static u32 mali_extr_backup = 0;
-//static u32 mali_extr_sample_backup = 0;
-struct timeval start;
-struct timeval end;
-
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 16))
-int mali_clock_init_clk_tree(struct platform_device* pdev)
-{
- mali_dvfs_threshold_table *dvfs_tbl = &pmali_plat->dvfs_table[pmali_plat->def_clock];
- struct clk *clk_mali_0_parent = dvfs_tbl->clkp_handle;
- struct clk *clk_mali_0 = pmali_plat->clk_mali_0;
-#ifdef AML_CLK_LOCK_ERROR
- struct clk *clk_mali_1 = pmali_plat->clk_mali_1;
-#endif
- struct clk *clk_mali = pmali_plat->clk_mali;
-
- clk_set_parent(clk_mali_0, clk_mali_0_parent);
-
- clk_prepare_enable(clk_mali_0);
-
- clk_set_parent(clk_mali, clk_mali_0);
-
-#ifdef AML_CLK_LOCK_ERROR
- clk_set_parent(clk_mali_1, clk_mali_0_parent);
- clk_prepare_enable(clk_mali_1);
-#endif
-
- GPU_CLK_DBG("%s:enable(%d), %s:enable(%d)\n",
- clk_mali_0->name, clk_mali_0->enable_count,
- clk_mali_0_parent->name, clk_mali_0_parent->enable_count);
-
- return 0;
-}
-
-int mali_clock_init(mali_plat_info_t *pdev)
-{
- *pdev = *pdev;
- return 0;
-}
-
-int mali_clock_critical(critical_t critical, size_t param)
-{
- int ret = 0;
-
- ret = critical(param);
-
- return ret;
-}
-
-static int critical_clock_set(size_t param)
-{
- int ret = 0;
- unsigned int idx = param;
- mali_dvfs_threshold_table *dvfs_tbl = &pmali_plat->dvfs_table[idx];
-
- struct clk *clk_mali_0 = pmali_plat->clk_mali_0;
- struct clk *clk_mali_1 = pmali_plat->clk_mali_1;
- struct clk *clk_mali_x = NULL;
- struct clk *clk_mali_x_parent = NULL;
- struct clk *clk_mali_x_old = NULL;
- struct clk *clk_mali = pmali_plat->clk_mali;
- unsigned long time_use=0;
-
- clk_mali_x_old = clk_get_parent(clk_mali);
-
- if (!clk_mali_x_old) {
- printk("gpu: could not get clk_mali_x_old or clk_mali_x_old\n");
- return 0;
- }
- if (clk_mali_x_old == clk_mali_0) {
- clk_mali_x = clk_mali_1;
- } else if (clk_mali_x_old == clk_mali_1) {
- clk_mali_x = clk_mali_0;
- } else {
- printk("gpu: unmatched clk_mali_x_old\n");
- return 0;
- }
-
- GPU_CLK_DBG("idx=%d, clk_freq=%d\n", idx, dvfs_tbl->clk_freq);
- clk_mali_x_parent = dvfs_tbl->clkp_handle;
- if (!clk_mali_x_parent) {
- printk("gpu: could not get clk_mali_x_parent\n");
- return 0;
- }
-
- GPU_CLK_DBG();
- ret = clk_set_rate(clk_mali_x_parent, dvfs_tbl->clkp_freq);
- GPU_CLK_DBG();
- ret = clk_set_parent(clk_mali_x, clk_mali_x_parent);
- GPU_CLK_DBG();
- ret = clk_set_rate(clk_mali_x, dvfs_tbl->clk_freq);
- GPU_CLK_DBG();
-#ifndef AML_CLK_LOCK_ERROR
- ret = clk_prepare_enable(clk_mali_x);
-#endif
- GPU_CLK_DBG("new %s:enable(%d)\n", clk_mali_x->name, clk_mali_x->enable_count);
- do_gettimeofday(&start);
- udelay(1);// delay 10ns
- do_gettimeofday(&end);
- ret = clk_set_parent(clk_mali, clk_mali_x);
- GPU_CLK_DBG();
-
-#ifndef AML_CLK_LOCK_ERROR
- clk_disable_unprepare(clk_mali_x_old);
-#endif
- GPU_CLK_DBG("old %s:enable(%d)\n", clk_mali_x_old->name, clk_mali_x_old->enable_count);
- time_use = (end.tv_sec - start.tv_sec)*1000000 + end.tv_usec - start.tv_usec;
- GPU_CLK_DBG("step 1, mali_mux use: %ld us\n", time_use);
-
- return 0;
-}
-
-int mali_clock_set(unsigned int clock)
-{
- return mali_clock_critical(critical_clock_set, (size_t)clock);
-}
-
-void disable_clock(void)
-{
- struct clk *clk_mali = pmali_plat->clk_mali;
- struct clk *clk_mali_x = NULL;
-
- clk_mali_x = clk_get_parent(clk_mali);
- GPU_CLK_DBG();
-#ifndef AML_CLK_LOCK_ERROR
- clk_disable_unprepare(clk_mali_x);
-#endif
- GPU_CLK_DBG();
-}
-
-void enable_clock(void)
-{
- struct clk *clk_mali = pmali_plat->clk_mali;
- struct clk *clk_mali_x = NULL;
-
- clk_mali_x = clk_get_parent(clk_mali);
- GPU_CLK_DBG();
-#ifndef AML_CLK_LOCK_ERROR
- clk_prepare_enable(clk_mali_x);
-#endif
- GPU_CLK_DBG();
-}
-
-u32 get_mali_freq(u32 idx)
-{
- if (!mali_pm_statue) {
- return pmali_plat->clk_sample[idx];
- } else {
- return 0;
- }
-}
-
-void set_str_src(u32 data)
-{
- printk("gpu: %s, %s, %d\n", __FILE__, __func__, __LINE__);
-}
-
-int mali_dt_info(struct platform_device *pdev, struct mali_plat_info_t *mpdata)
-{
- struct device_node *gpu_dn = pdev->dev.of_node;
- struct device_node *gpu_clk_dn;
- struct mali_gpu_clk_item *clk_item;
- phandle dvfs_clk_hdl;
- mali_dvfs_threshold_table *dvfs_tbl = NULL;
- uint32_t *clk_sample = NULL;
-
- struct property *prop;
- const __be32 *p;
- int length = 0, i = 0;
- u32 u;
-
- int ret = 0;
- if (!gpu_dn) {
- dev_notice(&pdev->dev, "gpu device node not right\n");
- return -ENODEV;
- }
-
- ret = of_property_read_u32(gpu_dn,"num_of_pp",
- &mpdata->cfg_pp);
- if (ret) {
- dev_notice(&pdev->dev, "set max pp to default 6\n");
- mpdata->cfg_pp = 6;
- }
- mpdata->scale_info.maxpp = mpdata->cfg_pp;
- mpdata->maxpp_sysfs = mpdata->cfg_pp;
- _dev_info(&pdev->dev, "max pp is %d\n", mpdata->scale_info.maxpp);
-
- ret = of_property_read_u32(gpu_dn,"min_pp",
- &mpdata->cfg_min_pp);
- if (ret) {
- dev_notice(&pdev->dev, "set min pp to default 1\n");
- mpdata->cfg_min_pp = 1;
- }
- mpdata->scale_info.minpp = mpdata->cfg_min_pp;
- _dev_info(&pdev->dev, "min pp is %d\n", mpdata->scale_info.minpp);
-
- ret = of_property_read_u32(gpu_dn,"min_clk",
- &mpdata->cfg_min_clock);
- if (ret) {
- dev_notice(&pdev->dev, "set min clk default to 0\n");
- mpdata->cfg_min_clock = 0;
- }
- mpdata->scale_info.minclk = mpdata->cfg_min_clock;
- _dev_info(&pdev->dev, "min clk is %d\n", mpdata->scale_info.minclk);
-
- mpdata->reg_base_hiubus = of_iomap(gpu_dn, 1);
- _dev_info(&pdev->dev, "hiu io source 0x%p\n", mpdata->reg_base_hiubus);
-
- mpdata->reg_base_aobus = of_iomap(gpu_dn, 2);
- _dev_info(&pdev->dev, "hiu io source 0x%p\n", mpdata->reg_base_aobus);
-
- ret = of_property_read_u32(gpu_dn,"sc_mpp",
- &mpdata->sc_mpp);
- if (ret) {
- dev_notice(&pdev->dev, "set pp used most of time default to %d\n", mpdata->cfg_pp);
- mpdata->sc_mpp = mpdata->cfg_pp;
- }
- _dev_info(&pdev->dev, "num of pp used most of time %d\n", mpdata->sc_mpp);
-
- of_get_property(gpu_dn, "tbl", &length);
-
- length = length /sizeof(u32);
- _dev_info(&pdev->dev, "clock dvfs cfg table size is %d\n", length);
-
- mpdata->dvfs_table = devm_kzalloc(&pdev->dev,
- sizeof(struct mali_dvfs_threshold_table)*length,
- GFP_KERNEL);
- dvfs_tbl = mpdata->dvfs_table;
- if (mpdata->dvfs_table == NULL) {
- dev_err(&pdev->dev, "failed to alloc dvfs table\n");
- return -ENOMEM;
- }
- mpdata->clk_sample = devm_kzalloc(&pdev->dev, sizeof(u32)*length, GFP_KERNEL);
- if (mpdata->clk_sample == NULL) {
- dev_err(&pdev->dev, "failed to alloc clk_sample table\n");
- return -ENOMEM;
- }
- clk_sample = mpdata->clk_sample;
-///////////
- mpdata->clk_items = devm_kzalloc(&pdev->dev, sizeof(struct mali_gpu_clk_item) * length, GFP_KERNEL);
- if (mpdata->clk_items == NULL) {
- dev_err(&pdev->dev, "failed to alloc clk_item table\n");
- return -ENOMEM;
- }
- clk_item = mpdata->clk_items;
-//
- of_property_for_each_u32(gpu_dn, "tbl", prop, p, u) {
- dvfs_clk_hdl = (phandle) u;
- gpu_clk_dn = of_find_node_by_phandle(dvfs_clk_hdl);
- ret = of_property_read_u32(gpu_clk_dn,"clk_freq", &dvfs_tbl->clk_freq);
- if (ret) {
- dev_notice(&pdev->dev, "read clk_freq failed\n");
- }
-#if 0
-#ifdef MESON_CPU_VERSION_OPS
- if (is_meson_gxbbm_cpu()) {
- if (dvfs_tbl->clk_freq >= GXBBM_MAX_GPU_FREQ)
- continue;
- }
-#endif
-#endif
- ret = of_property_read_string(gpu_clk_dn,"clk_parent",
- &dvfs_tbl->clk_parent);
- if (ret) {
- dev_notice(&pdev->dev, "read clk_parent failed\n");
- }
- dvfs_tbl->clkp_handle = devm_clk_get(&pdev->dev, dvfs_tbl->clk_parent);
- if (IS_ERR(dvfs_tbl->clkp_handle)) {
- dev_notice(&pdev->dev, "failed to get %s's clock pointer\n", dvfs_tbl->clk_parent);
- }
- ret = of_property_read_u32(gpu_clk_dn,"clkp_freq", &dvfs_tbl->clkp_freq);
- if (ret) {
- dev_notice(&pdev->dev, "read clk_parent freq failed\n");
- }
- ret = of_property_read_u32(gpu_clk_dn,"voltage", &dvfs_tbl->voltage);
- if (ret) {
- dev_notice(&pdev->dev, "read voltage failed\n");
- }
- ret = of_property_read_u32(gpu_clk_dn,"keep_count", &dvfs_tbl->keep_count);
- if (ret) {
- dev_notice(&pdev->dev, "read keep_count failed\n");
- }
- //downthreshold and upthreshold shall be u32
- ret = of_property_read_u32_array(gpu_clk_dn,"threshold",
- &dvfs_tbl->downthreshold, 2);
- if (ret) {
- dev_notice(&pdev->dev, "read threshold failed\n");
- }
- dvfs_tbl->freq_index = i;
- clk_item->clock = dvfs_tbl->clk_freq / 1000000;
- clk_item->vol = dvfs_tbl->voltage;
-
- *clk_sample = dvfs_tbl->clk_freq / 1000000;
-
- dvfs_tbl ++;
- clk_item ++;
- clk_sample ++;
- i++;
- mpdata->dvfs_table_size ++;
- }
-
- ret = of_property_read_u32(gpu_dn,"max_clk",
- &mpdata->cfg_clock);
- if (ret) {
- dev_notice(&pdev->dev, "max clk set %d\n", mpdata->dvfs_table_size-2);
- mpdata->cfg_clock = mpdata->dvfs_table_size-2;
- }
-
- mpdata->cfg_clock_bkup = mpdata->cfg_clock;
- mpdata->maxclk_sysfs = mpdata->cfg_clock;
- mpdata->scale_info.maxclk = mpdata->cfg_clock;
- _dev_info(&pdev->dev, "max clk is %d\n", mpdata->scale_info.maxclk);
-
- ret = of_property_read_u32(gpu_dn,"turbo_clk",
- &mpdata->turbo_clock);
- if (ret) {
- dev_notice(&pdev->dev, "turbo clk set to %d\n", mpdata->dvfs_table_size-1);
- mpdata->turbo_clock = mpdata->dvfs_table_size-1;
- }
- _dev_info(&pdev->dev, "turbo clk is %d\n", mpdata->turbo_clock);
-
- ret = of_property_read_u32(gpu_dn,"def_clk",
- &mpdata->def_clock);
- if (ret) {
- dev_notice(&pdev->dev, "default clk set to %d\n", mpdata->dvfs_table_size/2-1);
- mpdata->def_clock = mpdata->dvfs_table_size/2 - 1;
- }
- _dev_info(&pdev->dev, "default clk is %d\n", mpdata->def_clock);
-
- dvfs_tbl = mpdata->dvfs_table;
- clk_sample = mpdata->clk_sample;
- for (i = 0; i< mpdata->dvfs_table_size; i++) {
- _dev_info(&pdev->dev, "====================%d====================\n"
- "clk_freq=%10d, clk_parent=%9s, voltage=%d, keep_count=%d, threshod=<%d %d>, clk_sample=%d\n",
- i,
- dvfs_tbl->clk_freq, dvfs_tbl->clk_parent,
- dvfs_tbl->voltage, dvfs_tbl->keep_count,
- dvfs_tbl->downthreshold, dvfs_tbl->upthreshold, *clk_sample);
- dvfs_tbl ++;
- clk_sample ++;
- }
- _dev_info(&pdev->dev, "clock dvfs table size is %d\n", mpdata->dvfs_table_size);
-
- mpdata->clk_mali = devm_clk_get(&pdev->dev, "clk_mali");
- mpdata->clk_mali_0 = devm_clk_get(&pdev->dev, "clk_mali_0");
- mpdata->clk_mali_1 = devm_clk_get(&pdev->dev, "clk_mali_1");
- if (IS_ERR(mpdata->clk_mali) || IS_ERR(mpdata->clk_mali_0) || IS_ERR(mpdata->clk_mali_1)) {
- dev_err(&pdev->dev, "failed to get clock pointer\n");
- return -EFAULT;
- }
-
- pmali_plat = mpdata;
- mpdata->pdev = pdev;
- return 0;
-}
-#else
-int mali_clock_init_clk_tree(struct platform_device* pdev)
-{
- //mali_dvfs_threshold_table *dvfs_tbl = &pmali_plat->dvfs_table[pmali_plat->def_clock];
- struct clk *clk_mali = pmali_plat->clk_mali;
-
- clk_prepare_enable(clk_mali);
-
- return 0;
-}
-
-int mali_clock_init(mali_plat_info_t *pdev)
-{
- *pdev = *pdev;
- return 0;
-}
-
-int mali_clock_critical(critical_t critical, size_t param)
-{
- int ret = 0;
-
- ret = critical(param);
-
- return ret;
-}
-
-static int critical_clock_set(size_t param)
-{
- int ret = 0;
- unsigned int idx = param;
- mali_dvfs_threshold_table *dvfs_tbl = &pmali_plat->dvfs_table[idx];
-
- struct clk *clk_mali = pmali_plat->clk_mali;
- unsigned long time_use=0;
-
-
- GPU_CLK_DBG();
- do_gettimeofday(&start);
- ret = clk_set_rate(clk_mali, dvfs_tbl->clk_freq);
- do_gettimeofday(&end);
- GPU_CLK_DBG();
-
-#ifndef AML_CLK_LOCK_ERROR
- clk_disable_unprepare(clk_mali_x_old);
-#endif
- time_use = (end.tv_sec - start.tv_sec)*1000000 + end.tv_usec - start.tv_usec;
- GPU_CLK_DBG("step 1, mali_mux use: %ld us\n", time_use);
-
- return 0;
-}
-
-int mali_clock_set(unsigned int clock)
-{
- return mali_clock_critical(critical_clock_set, (size_t)clock);
-}
-
-void disable_clock(void)
-{
-#ifndef AML_CLK_LOCK_ERROR
- struct clk *clk_mali = pmali_plat->clk_mali;
-
- GPU_CLK_DBG();
- clk_disable_unprepare(clk_mali);
-#endif
- GPU_CLK_DBG();
-}
-
-void enable_clock(void)
-{
-#ifndef AML_CLK_LOCK_ERROR
- struct clk *clk_mali = pmali_plat->clk_mali;
-
- clk_prepare_enable(clk_mali);
-#endif
- GPU_CLK_DBG();
-}
-
-u32 get_mali_freq(u32 idx)
-{
- if (!mali_pm_statue) {
- return pmali_plat->clk_sample[idx];
- } else {
- return 0;
- }
-}
-
-void set_str_src(u32 data)
-{
- printk("gpu: %s, %s, %d\n", __FILE__, __func__, __LINE__);
-}
-
-int mali_dt_info(struct platform_device *pdev, struct mali_plat_info_t *mpdata)
-{
- struct device_node *gpu_dn = pdev->dev.of_node;
- struct device_node *gpu_clk_dn;
- struct mali_gpu_clk_item *clk_item;
- phandle dvfs_clk_hdl;
- mali_dvfs_threshold_table *dvfs_tbl = NULL;
- uint32_t *clk_sample = NULL;
-
- struct property *prop;
- const __be32 *p;
- int length = 0, i = 0;
- u32 u;
-
- int ret = 0;
- if (!gpu_dn) {
- dev_notice(&pdev->dev, "gpu device node not right\n");
- return -ENODEV;
- }
-
- ret = of_property_read_u32(gpu_dn,"num_of_pp",
- &mpdata->cfg_pp);
- if (ret) {
- dev_notice(&pdev->dev, "set max pp to default 6\n");
- mpdata->cfg_pp = 6;
- }
- mpdata->scale_info.maxpp = mpdata->cfg_pp;
- mpdata->maxpp_sysfs = mpdata->cfg_pp;
- _dev_info(&pdev->dev, "max pp is %d\n", mpdata->scale_info.maxpp);
-
- ret = of_property_read_u32(gpu_dn,"min_pp",
- &mpdata->cfg_min_pp);
- if (ret) {
- dev_notice(&pdev->dev, "set min pp to default 1\n");
- mpdata->cfg_min_pp = 1;
- }
- mpdata->scale_info.minpp = mpdata->cfg_min_pp;
- _dev_info(&pdev->dev, "min pp is %d\n", mpdata->scale_info.minpp);
-
- ret = of_property_read_u32(gpu_dn,"min_clk",
- &mpdata->cfg_min_clock);
- if (ret) {
- dev_notice(&pdev->dev, "set min clk default to 0\n");
- mpdata->cfg_min_clock = 0;
- }
- mpdata->scale_info.minclk = mpdata->cfg_min_clock;
- _dev_info(&pdev->dev, "min clk is %d\n", mpdata->scale_info.minclk);
-
- mpdata->reg_base_hiubus = of_iomap(gpu_dn, 1);
- _dev_info(&pdev->dev, "hiu io source 0x%p\n", mpdata->reg_base_hiubus);
-
- mpdata->reg_base_aobus = of_iomap(gpu_dn, 2);
- _dev_info(&pdev->dev, "hiu io source 0x%p\n", mpdata->reg_base_aobus);
-
- ret = of_property_read_u32(gpu_dn,"sc_mpp",
- &mpdata->sc_mpp);
- if (ret) {
- dev_notice(&pdev->dev, "set pp used most of time default to %d\n", mpdata->cfg_pp);
- mpdata->sc_mpp = mpdata->cfg_pp;
- }
- _dev_info(&pdev->dev, "num of pp used most of time %d\n", mpdata->sc_mpp);
-
- of_get_property(gpu_dn, "tbl", &length);
-
- length = length /sizeof(u32);
- _dev_info(&pdev->dev, "clock dvfs cfg table size is %d\n", length);
-
- mpdata->dvfs_table = devm_kzalloc(&pdev->dev,
- sizeof(struct mali_dvfs_threshold_table)*length,
- GFP_KERNEL);
- dvfs_tbl = mpdata->dvfs_table;
- if (mpdata->dvfs_table == NULL) {
- dev_err(&pdev->dev, "failed to alloc dvfs table\n");
- return -ENOMEM;
- }
- mpdata->clk_sample = devm_kzalloc(&pdev->dev, sizeof(u32)*length, GFP_KERNEL);
- if (mpdata->clk_sample == NULL) {
- dev_err(&pdev->dev, "failed to alloc clk_sample table\n");
- return -ENOMEM;
- }
- clk_sample = mpdata->clk_sample;
-///////////
- mpdata->clk_items = devm_kzalloc(&pdev->dev, sizeof(struct mali_gpu_clk_item) * length, GFP_KERNEL);
- if (mpdata->clk_items == NULL) {
- dev_err(&pdev->dev, "failed to alloc clk_item table\n");
- return -ENOMEM;
- }
- clk_item = mpdata->clk_items;
-//
- of_property_for_each_u32(gpu_dn, "tbl", prop, p, u) {
- dvfs_clk_hdl = (phandle) u;
- gpu_clk_dn = of_find_node_by_phandle(dvfs_clk_hdl);
- ret = of_property_read_u32(gpu_clk_dn,"clk_freq", &dvfs_tbl->clk_freq);
- if (ret) {
- dev_notice(&pdev->dev, "read clk_freq failed\n");
- }
-#if 0
-#ifdef MESON_CPU_VERSION_OPS
- if (is_meson_gxbbm_cpu()) {
- if (dvfs_tbl->clk_freq >= GXBBM_MAX_GPU_FREQ)
- continue;
- }
-#endif
-#endif
-#if 0
- ret = of_property_read_string(gpu_clk_dn,"clk_parent",
- &dvfs_tbl->clk_parent);
- if (ret) {
- dev_notice(&pdev->dev, "read clk_parent failed\n");
- }
- dvfs_tbl->clkp_handle = devm_clk_get(&pdev->dev, dvfs_tbl->clk_parent);
- if (IS_ERR(dvfs_tbl->clkp_handle)) {
- dev_notice(&pdev->dev, "failed to get %s's clock pointer\n", dvfs_tbl->clk_parent);
- }
- ret = of_property_read_u32(gpu_clk_dn,"clkp_freq", &dvfs_tbl->clkp_freq);
- if (ret) {
- dev_notice(&pdev->dev, "read clk_parent freq failed\n");
- }
-#endif
- ret = of_property_read_u32(gpu_clk_dn,"voltage", &dvfs_tbl->voltage);
- if (ret) {
- dev_notice(&pdev->dev, "read voltage failed\n");
- }
- ret = of_property_read_u32(gpu_clk_dn,"keep_count", &dvfs_tbl->keep_count);
- if (ret) {
- dev_notice(&pdev->dev, "read keep_count failed\n");
- }
- //downthreshold and upthreshold shall be u32
- ret = of_property_read_u32_array(gpu_clk_dn,"threshold",
- &dvfs_tbl->downthreshold, 2);
- if (ret) {
- dev_notice(&pdev->dev, "read threshold failed\n");
- }
- dvfs_tbl->freq_index = i;
- clk_item->clock = dvfs_tbl->clk_freq / 1000000;
- clk_item->vol = dvfs_tbl->voltage;
-
- *clk_sample = dvfs_tbl->clk_freq / 1000000;
-
- dvfs_tbl ++;
- clk_item ++;
- clk_sample ++;
- i++;
- mpdata->dvfs_table_size ++;
- }
-
- ret = of_property_read_u32(gpu_dn,"max_clk",
- &mpdata->cfg_clock);
- if (ret) {
- dev_notice(&pdev->dev, "max clk set %d\n", mpdata->dvfs_table_size-2);
- mpdata->cfg_clock = mpdata->dvfs_table_size-2;
- }
-
- mpdata->cfg_clock_bkup = mpdata->cfg_clock;
- mpdata->maxclk_sysfs = mpdata->cfg_clock;
- mpdata->scale_info.maxclk = mpdata->cfg_clock;
- _dev_info(&pdev->dev, "max clk is %d\n", mpdata->scale_info.maxclk);
-
- ret = of_property_read_u32(gpu_dn,"turbo_clk",
- &mpdata->turbo_clock);
- if (ret) {
- dev_notice(&pdev->dev, "turbo clk set to %d\n", mpdata->dvfs_table_size-1);
- mpdata->turbo_clock = mpdata->dvfs_table_size-1;
- }
- _dev_info(&pdev->dev, "turbo clk is %d\n", mpdata->turbo_clock);
-
- ret = of_property_read_u32(gpu_dn,"def_clk",
- &mpdata->def_clock);
- if (ret) {
- dev_notice(&pdev->dev, "default clk set to %d\n", mpdata->dvfs_table_size/2-1);
- mpdata->def_clock = mpdata->dvfs_table_size/2 - 1;
- }
- _dev_info(&pdev->dev, "default clk is %d\n", mpdata->def_clock);
-
- dvfs_tbl = mpdata->dvfs_table;
- clk_sample = mpdata->clk_sample;
- for (i = 0; i< mpdata->dvfs_table_size; i++) {
- _dev_info(&pdev->dev, "====================%d====================\n"
- "clk_freq=%10d, clk_parent=%9s, voltage=%d, keep_count=%d, threshod=<%d %d>, clk_sample=%d\n",
- i,
- dvfs_tbl->clk_freq, dvfs_tbl->clk_parent,
- dvfs_tbl->voltage, dvfs_tbl->keep_count,
- dvfs_tbl->downthreshold, dvfs_tbl->upthreshold, *clk_sample);
- dvfs_tbl ++;
- clk_sample ++;
- }
- _dev_info(&pdev->dev, "clock dvfs table size is %d\n", mpdata->dvfs_table_size);
-
- mpdata->clk_mali = devm_clk_get(&pdev->dev, "gpu_mux");
-#if 0
- mpdata->clk_mali_0 = devm_clk_get(&pdev->dev, "clk_mali_0");
- mpdata->clk_mali_1 = devm_clk_get(&pdev->dev, "clk_mali_1");
-#endif
- if (IS_ERR(mpdata->clk_mali)) {
- dev_err(&pdev->dev, "failed to get clock pointer\n");
- return -EFAULT;
- }
-
- pmali_plat = mpdata;
- mpdata->pdev = pdev;
- return 0;
-}
-
-#endif
+++ /dev/null
-#ifndef __MALI_CLOCK_H__
-#define __MALI_CLOCK_H__
-#include <linux/version.h>
-#include <linux/pm.h>
-#include <linux/io.h>
-#include <linux/types.h>
-#include <linux/of.h>
-
-#include <asm/io.h>
-#include <linux/clk.h>
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 29))
-#include <linux/amlogic/iomap.h>
-#endif
-
-#ifndef HHI_MALI_CLK_CNTL
-#define HHI_MALI_CLK_CNTL 0x6C
-#define mplt_read(r) readl((pmali_plat->reg_base_hiubus) + ((r)<<2))
-#define mplt_write(r, v) writel((v), ((pmali_plat->reg_base_hiubus) + ((r)<<2)))
-#define mplt_setbits(r, m) mplt_write((r), (mplt_read(r) | (m)));
-#define mplt_clrbits(r, m) mplt_write((r), (mplt_read(r) & (~(m))));
-#endif
-
-//extern int mali_clock_init(struct platform_device *dev);
-int mali_clock_init_clk_tree(struct platform_device *pdev);
-
-typedef int (*critical_t)(size_t param);
-int mali_clock_critical(critical_t critical, size_t param);
-
-int mali_clock_init(mali_plat_info_t*);
-int mali_clock_set(unsigned int index);
-void disable_clock(void);
-void enable_clock(void);
-u32 get_mali_freq(u32 idx);
-void set_str_src(u32 data);
-int mali_dt_info(struct platform_device *pdev,
- struct mali_plat_info_t *mpdata);
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2013 ARM Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
- *
- * A copy of the licence is included with the program, and can also be obtained from Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-/**
- * @file arm_core_scaling.c
- * Example core scaling policy.
- */
-
-#include <linux/version.h>
-#include <linux/module.h>
-#include <linux/workqueue.h>
-#include <linux/mali/mali_utgard.h>
-#include <mali_kernel_common.h>
-#include <mali_osk_profiling.h>
-#include <linux/time.h>
-
-//#include <linux/amlogic/amports/gp_pll.h>
-#include "meson_main2.h"
-
-
-static int currentStep;
-static int scaling_mode = MALI_PP_FS_SCALING;
-//static int scaling_mode = MALI_SCALING_DISABLE;
-//static int scaling_mode = MALI_PP_SCALING;
-
-//static struct gp_pll_user_handle_s *gp_pll_user_gpu;
-//static int is_gp_pll_get;
-//static int is_gp_pll_put;
-
-static unsigned scaling_dbg_level = 0;
-module_param(scaling_dbg_level, uint, 0644);
-MODULE_PARM_DESC(scaling_dbg_level , "scaling debug level");
-
-static mali_plat_info_t* pmali_plat = NULL;
-static struct workqueue_struct *mali_scaling_wq = NULL;
-//static DEFINE_SPINLOCK(lock);
-
-static int cur_gpu_clk_index = 0;
-static int exec_gpu_clk_index = 0;
-#define scalingdbg(level, fmt, arg...) \
- do { \
- if (scaling_dbg_level >= (level)) \
- printk(fmt , ## arg); \
- } while (0)
-
-struct mali_gpu_clock meson_gpu_clk_info = {
- .item = NULL,
- .num_of_steps = 0,
-};
-
-u32 revise_set_clk(u32 val, u32 flush)
-{
- u32 ret = 0;
- return ret;
-}
-
-void get_mali_rt_clkpp(u32* clk, u32* pp)
-{
-}
-
-u32 set_mali_rt_clkpp(u32 clk, u32 pp, u32 flush)
-{
- u32 ret = 0;
- return ret;
-}
-
-void revise_mali_rt(void)
-{
-}
-
-static void do_scaling(struct work_struct *work)
-{
- //unsigned long flags;
- mali_plat_info_t *pinfo = container_of(work, struct mali_plat_info_t, wq_work);
-
- *pinfo = *pinfo;
- //mali_dev_pause();
- //spin_lock_irqsave(&lock, flags);
- mali_clock_set(exec_gpu_clk_index);
- cur_gpu_clk_index = exec_gpu_clk_index;
- //spin_unlock_irqrestore(&lock, flags);
- //mali_dev_resume();
-}
-void flush_scaling_job(void)
-{
- if (mali_scaling_wq == NULL) return;
-
- flush_workqueue(mali_scaling_wq);
- printk("%s, %d\n", __func__, __LINE__);
-}
-
-
-int mali_core_scaling_init(mali_plat_info_t *mali_plat)
-{
- pmali_plat = mali_plat;
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)
- mali_scaling_wq = alloc_workqueue("gpu_scaling_wq", WQ_HIGHPRI | WQ_UNBOUND, 0);
-#else
- mali_scaling_wq = create_workqueue("gpu_scaling_wq");
-#endif
- INIT_WORK(&pmali_plat->wq_work, do_scaling);
- if (mali_scaling_wq == NULL) printk("Unable to create gpu scaling workqueue\n");
-
- meson_gpu_clk_info.num_of_steps = pmali_plat->scale_info.maxclk;
-
- return 0;
-}
-
-void mali_core_scaling_term(void)
-{
- flush_scaling_job();
- destroy_workqueue(mali_scaling_wq);
- mali_scaling_wq = NULL;
-}
-
-void mali_pp_scaling_update(struct mali_gpu_utilization_data *data)
-{
-}
-
-void mali_pp_fs_scaling_update(struct mali_gpu_utilization_data *data)
-{
-}
-
-u32 get_mali_schel_mode(void)
-{
- return scaling_mode;
-}
-
-void set_mali_schel_mode(u32 mode)
-{
- scaling_mode = mode;
- if (scaling_mode == MALI_TURBO_MODE) {
- printk ("turbo mode\n");
- pmali_plat->limit_on = 0;
- meson_gpu_clk_info.num_of_steps = pmali_plat->turbo_clock;
- } else {
- printk ("not turbo mode\n");
- pmali_plat->limit_on = 1;
- meson_gpu_clk_info.num_of_steps = pmali_plat->scale_info.maxclk;
- }
-
- printk("total_enable_steps = %d\n", meson_gpu_clk_info.num_of_steps);
-}
-
-u32 get_current_frequency(void)
-{
- return get_mali_freq(currentStep);
-}
-
-void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data)
-{
-}
-
-void mali_dev_restore(void)
-{
- //TO add this
- //mali_perf_set_num_pp_cores(num_cores_enabled);
- if (pmali_plat && pmali_plat->pdev) {
- mali_clock_init_clk_tree(pmali_plat->pdev);
- } else {
- printk("error: init clock failed, pmali_plat=%p, pmali_plat->pdev=%p\n",
- pmali_plat, pmali_plat == NULL ? NULL: pmali_plat->pdev);
- }
-}
-
-/* Function that platfrom report it's clock info which driver can set, needed when CONFIG_MALI_DVFS enabled */
-static void meson_platform_get_clock_info(struct mali_gpu_clock **data) {
- if (pmali_plat) {
- meson_gpu_clk_info.item = pmali_plat->clk_items;
- meson_gpu_clk_info.num_of_steps = pmali_plat->scale_info.maxclk;
- printk("get clock info\n");
- } else {
- printk("error pmali_plat is null");
- }
- *data = &meson_gpu_clk_info;
-}
-
-/* Function that get the current clock info, needed when CONFIG_MALI_DVFS enabled */
-static int meson_platform_get_freq(void) {
- scalingdbg(1, "cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
- //dynamically changed the num of steps;
- return cur_gpu_clk_index;
-}
-
-/* Fuction that platform callback for freq setting, needed when CONFIG_MALI_DVFS enabled */
-static int meson_platform_set_freq(int setting_clock_step) {
-
- if (exec_gpu_clk_index == setting_clock_step) {
- return 0;
- }
-
- queue_work(mali_scaling_wq, &pmali_plat->wq_work);
- exec_gpu_clk_index = setting_clock_step;
- scalingdbg(1, "set cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
- return 0;
-}
-
-int mali_meson_get_gpu_data(struct mali_gpu_device_data *mgpu_data)
-{
- mgpu_data->get_clock_info = meson_platform_get_clock_info,
- mgpu_data->get_freq = meson_platform_get_freq,
- mgpu_data->set_freq = meson_platform_set_freq,
- mgpu_data->utilization_callback = NULL;
- return 0;
-}
+++ /dev/null
-/*
- * mali_platform.h
- *
- * Created on: Nov 8, 2013
- * Author: amlogic
- */
-
-#include <linux/kernel.h>
-#ifndef MALI_PLATFORM_H_
-#define MALI_PLATFORM_H_
-
-extern u32 mali_gp_reset_fail;
-extern u32 mali_core_timeout;
-
-#endif /* MALI_PLATFORM_H_ */
+++ /dev/null
-../mali_scaling.h
\ No newline at end of file
+++ /dev/null
-/*
- * Copyright (C) 2010, 2012-2014 Amlogic Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
- *
- */
-
-/**
- * @file mali_platform.c
- * Platform specific Mali driver functions for:
- * meson8m2 and the newer chip
- */
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#ifdef CONFIG_PM_RUNTIME
-#include <linux/pm_runtime.h>
-#endif
-#include <asm/io.h>
-#include <linux/mali/mali_utgard.h>
-#include "mali_kernel_common.h"
-#include <linux/dma-mapping.h>
-#include <linux/moduleparam.h>
-
-#include "mali_executor.h"
-#include "mali_scaling.h"
-#include "mali_clock.h"
-#include "meson_main2.h"
-
-int mali_pm_statue = 0;
-extern void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data);
-
-u32 mali_gp_reset_fail = 0;
-module_param(mali_gp_reset_fail, int, S_IRUSR | S_IWUSR | S_IWGRP | S_IRGRP | S_IROTH); /* rw-rw-r-- */
-MODULE_PARM_DESC(mali_gp_reset_fail, "times of failed to reset GP");
-u32 mali_core_timeout = 0;
-module_param(mali_core_timeout, int, S_IRUSR | S_IWUSR | S_IWGRP | S_IRGRP | S_IROTH); /* rw-rw-r-- */
-MODULE_PARM_DESC(mali_core_timeout, "timeout of failed to reset GP");
-
-static struct mali_gpu_device_data mali_gpu_data = {
-
-#if defined(CONFIG_ARCH_REALVIEW)
- .dedicated_mem_start = 0x80000000, /* Physical start address (use 0xD0000000 for old indirect setup) */
- .dedicated_mem_size = 0x10000000, /* 256MB */
-#endif
-#if defined(CONFIG_ARM64)
- .fb_start = 0x5f000000,
- .fb_size = 0x91000000,
-#else
- .fb_start = 0xe0000000,
- .fb_size = 0x01000000,
-#endif
- .control_interval = 200, /* 1000ms */
-};
-
-int mali_platform_device_init(struct platform_device *device)
-{
- int err = -1;
-
- err = mali_meson_init_start(device);
- if (0 != err) printk("mali init failed\n");
- err = mali_meson_get_gpu_data(&mali_gpu_data);
- if (0 != err) printk("mali get gpu data failed\n");
-
- err = platform_device_add_data(device, &mali_gpu_data, sizeof(mali_gpu_data));
-
- if (0 == err) {
- device->dev.type = &mali_pm_device; /* We should probably use the pm_domain instead of type on newer kernels */
-#ifdef CONFIG_PM_RUNTIME
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
- pm_runtime_set_autosuspend_delay(&device->dev, 1000);
- pm_runtime_use_autosuspend(&device->dev);
-#endif
- pm_runtime_enable(&device->dev);
-#endif
- mali_meson_init_finish(device);
- }
-
- mali_gp_reset_fail = 0;
- mali_core_timeout = 0;
-
- return err;
-}
-
-int mali_platform_device_deinit(struct platform_device *device)
-{
- MALI_IGNORE(device);
-
- printk("%s, %d\n", __FILE__, __LINE__);
- MALI_DEBUG_PRINT(4, ("mali_platform_device_deinit() called\n"));
-
-
- mali_meson_uninit(device);
-
- return 0;
-}
-
-#if 0
-static int param_set_core_scaling(const char *val, const struct kernel_param *kp)
-{
- int ret = param_set_int(val, kp);
- printk("%s, %d\n", __FILE__, __LINE__);
-
- if (1 == mali_core_scaling_enable) {
- mali_core_scaling_sync(mali_executor_get_num_cores_enabled());
- }
- return ret;
-}
-
-static struct kernel_param_ops param_ops_core_scaling = {
- .set = param_set_core_scaling,
- .get = param_get_int,
-};
-
-module_param_cb(mali_core_scaling_enable, ¶m_ops_core_scaling, &mali_core_scaling_enable, 0644);
-MODULE_PARM_DESC(mali_core_scaling_enable, "1 means to enable core scaling policy, 0 means to disable core scaling policy");
-#endif
+++ /dev/null
-/*
- * mali_platform.h
- *
- * Created on: Nov 8, 2013
- * Author: amlogic
- */
-
-#ifndef MESON_MAIN_H_
-#define MESON_MAIN_H_
-#include <linux/version.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#ifdef CONFIG_PM_RUNTIME
-#include <linux/pm_runtime.h>
-#endif
-#include <linux/mali/mali_utgard.h>
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/cpu.h>
-#endif
-
-#include "mali_scaling.h"
-#include "mali_clock.h"
-
-extern struct device_type mali_pm_device;
-extern int mali_pm_statue;
-
-u32 set_max_mali_freq(u32 idx);
-u32 get_max_mali_freq(void);
-
-int mali_meson_init_start(struct platform_device* ptr_plt_dev);
-int mali_meson_get_gpu_data(struct mali_gpu_device_data *mgpu_data);
-int mali_meson_init_finish(struct platform_device* ptr_plt_dev);
-int mali_meson_uninit(struct platform_device* ptr_plt_dev);
-int mali_light_suspend(struct device *device);
-int mali_light_resume(struct device *device);
-int mali_deep_suspend(struct device *device);
-int mali_deep_resume(struct device *device);
-
-#endif /* MESON_MAIN_H_ */
+++ /dev/null
-/*******************************************************************
- *
- * Copyright C 2013 by Amlogic, Inc. All Rights Reserved.
- *
- * Description:
- *
- * Author: Amlogic Software
- * Created: 2010/4/1 19:46
- *
- *******************************************************************/
-/* Standard Linux headers */
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/string.h>
-#include <linux/slab.h>
-#include <linux/list.h>
-
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/io.h>
-#include <plat/io.h>
-#include <asm/io.h>
-#endif
-
-#include <linux/mali/mali_utgard.h>
-#include <common/mali_kernel_common.h>
-#include <common/mali_pmu.h>
-//#include "mali_pp_scheduler.h"
-#include "meson_main.h"
-
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
-static ssize_t domain_stat_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- unsigned int val;
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
-
- val = readl(pmali_plat->reg_base_aobus + 0xf0) & 0xff;
- return sprintf(buf, "%x\n", val>>4);
- return 0;
-}
-
-#define PREHEAT_CMD "preheat"
-#define PLL2_CMD "mpl2" /* mpl2 [11] or [0xxxxxxx] */
-#define SCMPP_CMD "scmpp" /* scmpp [number of pp your want in most of time]. */
-#define BSTGPU_CMD "bstgpu" /* bstgpu [0-256] */
-#define BSTPP_CMD "bstpp" /* bstpp [0-256] */
-#define LIMIT_CMD "lmt" /* lmt [0 or 1] */
-#define MAX_TOKEN 20
-#define FULL_UTILIZATION 256
-
-static ssize_t mpgpu_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- char *pstart, *cprt = NULL;
- u32 val = 0;
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
-
- cprt = skip_spaces(buf);
- pstart = strsep(&cprt," ");
- if (strlen(pstart) < 1)
- goto quit;
-
- if (!strncmp(pstart, PREHEAT_CMD, MAX_TOKEN)) {
- if (pmali_plat->plat_preheat) {
- pmali_plat->plat_preheat();
- }
- } else if (!strncmp(pstart, PLL2_CMD, MAX_TOKEN)) {
- int base = 10;
- if ((strlen(cprt) > 2) && (cprt[0] == '0') &&
- (cprt[1] == 'x' || cprt[1] == 'X'))
- base = 16;
- if (kstrtouint(cprt, base, &val) <0)
- goto quit;
- if (val < 11)
- pmali_plat->cfg_clock = pmali_plat->cfg_clock_bkup;
- else
- pmali_plat->cfg_clock = pmali_plat->turbo_clock;
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- set_str_src(val);
- } else if (!strncmp(pstart, SCMPP_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
- if ((val > 0) && (val < pmali_plat->cfg_pp)) {
- pmali_plat->sc_mpp = val;
- }
- } else if (!strncmp(pstart, BSTGPU_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
- if ((val > 0) && (val < FULL_UTILIZATION)) {
- pmali_plat->bst_gpu = val;
- }
- } else if (!strncmp(pstart, BSTPP_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
- if ((val > 0) && (val < FULL_UTILIZATION)) {
- pmali_plat->bst_pp = val;
- }
- } else if (!strncmp(pstart, LIMIT_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
-
- if (val < 2) {
- pmali_plat->limit_on = val;
- if (val == 0) {
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- pmali_plat->scale_info.maxpp = pmali_plat->cfg_pp;
- revise_mali_rt();
- }
- }
- }
-quit:
- return count;
-}
-
-static ssize_t scale_mode_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- return sprintf(buf, "%d\n", get_mali_schel_mode());
-}
-
-static ssize_t scale_mode_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
-
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- {
- return -EINVAL;
- }
-
- set_mali_schel_mode(val);
-
- return count;
-}
-
-static ssize_t max_pp_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- printk("maxpp:%d, maxpp_sysfs:%d, total=%d\n",
- pmali_plat->scale_info.maxpp, pmali_plat->maxpp_sysfs,
- pmali_plat->cfg_pp);
- return sprintf(buf, "%d\n", pmali_plat->cfg_pp);
-}
-
-static ssize_t max_pp_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pmali_plat->cfg_pp) || (val < pinfo->minpp))
- return -EINVAL;
-
- pmali_plat->maxpp_sysfs = val;
- pinfo->maxpp = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t min_pp_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- return sprintf(buf, "%d\n", pmali_plat->scale_info.minpp);
-}
-
-static ssize_t min_pp_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pinfo->maxpp) || (val < 1))
- return -EINVAL;
-
- pinfo->minpp = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t max_freq_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- printk("maxclk:%d, maxclk_sys:%d, max gpu level=%d\n",
- pmali_plat->scale_info.maxclk, pmali_plat->maxclk_sysfs, get_gpu_max_clk_level());
- return sprintf(buf, "%d\n", get_gpu_max_clk_level());
-}
-
-static ssize_t max_freq_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pmali_plat->cfg_clock) || (val < pinfo->minclk))
- return -EINVAL;
-
- pmali_plat->maxclk_sysfs = val;
- pinfo->maxclk = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t min_freq_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- return sprintf(buf, "%d\n", pmali_plat->scale_info.minclk);
-}
-
-static ssize_t min_freq_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pinfo->maxclk))
- return -EINVAL;
-
- pinfo->minclk = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t freq_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- return sprintf(buf, "%d\n", get_current_frequency());
-}
-
-static ssize_t freq_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- u32 clk, pp;
- get_mali_rt_clkpp(&clk, &pp);
-
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- return -EINVAL;
-
- set_mali_rt_clkpp(val, pp, 1);
-
- return count;
-}
-
-static ssize_t current_pp_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- u32 clk, pp;
- get_mali_rt_clkpp(&clk, &pp);
- return sprintf(buf, "%d\n", pp);
-}
-
-static ssize_t current_pp_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- u32 clk, pp;
-
- get_mali_rt_clkpp(&clk, &pp);
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- {
- return -EINVAL;
- }
-
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- return -EINVAL;
-
- set_mali_rt_clkpp(clk, val, 1);
-
- return count;
-}
-
-static struct class_attribute mali_class_attrs[] = {
- __ATTR(domain_stat, 0644, domain_stat_read, NULL),
- __ATTR(mpgpucmd, 0644, NULL, mpgpu_write),
- __ATTR(scale_mode, 0644, scale_mode_read, scale_mode_write),
- __ATTR(min_freq, 0644, min_freq_read, min_freq_write),
- __ATTR(max_freq, 0644, max_freq_read, max_freq_write),
- __ATTR(min_pp, 0644, min_pp_read, min_pp_write),
- __ATTR(max_pp, 0644, max_pp_read, max_pp_write),
- __ATTR(cur_freq, 0644, freq_read, freq_write),
- __ATTR(cur_pp, 0644, current_pp_read, current_pp_write),
-};
-
-static struct class mpgpu_class = {
- .name = "mpgpu",
-};
-#endif
-
-int mpgpu_class_init(void)
-{
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
- int ret = 0;
- int i;
- int attr_num = ARRAY_SIZE(mali_class_attrs);
-
- ret = class_register(&mpgpu_class);
- if (ret) {
- printk(KERN_ERR "%s: class_register failed\n", __func__);
- return ret;
- }
- for (i = 0; i< attr_num; i++) {
- ret = class_create_file(&mpgpu_class, &mali_class_attrs[i]);
- if (ret) {
- printk(KERN_ERR "%d ST: class item failed to register\n", i);
- }
- }
- return ret;
-#else
- return 0;
-#endif
-}
-
-void mpgpu_class_exit(void)
-{
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
- class_unregister(&mpgpu_class);
-#endif
-}
-
+++ /dev/null
-/*
- * platform.c
- *
- * clock source setting and resource config
- *
- * Created on: Dec 4, 2013
- * Author: amlogic
- */
-
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/module.h> /* kernel module definitions */
-#include <linux/ioport.h> /* request_mem_region */
-#include <linux/slab.h>
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#endif
-#include <asm/io.h>
-#include <linux/mali/mali_utgard.h>
-#ifdef CONFIG_GPU_THERMAL
-#include <linux/gpu_cooling.h>
-#include <linux/gpucore_cooling.h>
-#ifdef CONFIG_DEVFREQ_THERMAL
-#include <linux/amlogic/aml_thermal_hw.h>
-#include <common/mali_ukk.h>
-#endif
-#endif
-#include <common/mali_kernel_common.h>
-#include <common/mali_osk_profiling.h>
-#include <common/mali_pmu.h>
-
-#include "mali_scaling.h"
-#include "mali_clock.h"
-#include "meson_main.h"
-#include "mali_executor.h"
-
-/*
- * For Meson 8 M2.
- *
- */
-static void mali_plat_preheat(void);
-static mali_plat_info_t mali_plat_data = {
- .bst_gpu = 210, /* threshold for boosting gpu. */
- .bst_pp = 160, /* threshold for boosting PP. */
- .have_switch = 1,
- .limit_on = 1,
- .plat_preheat = mali_plat_preheat,
-};
-
-static void mali_plat_preheat(void)
-{
-#ifndef CONFIG_MALI_DVFS
- u32 pre_fs;
- u32 clk, pp;
-
- if (get_mali_schel_mode() != MALI_PP_FS_SCALING)
- return;
-
- get_mali_rt_clkpp(&clk, &pp);
- pre_fs = mali_plat_data.def_clock + 1;
- if (clk < pre_fs)
- clk = pre_fs;
- if (pp < mali_plat_data.sc_mpp)
- pp = mali_plat_data.sc_mpp;
- set_mali_rt_clkpp(clk, pp, 1);
-#endif
-}
-
-mali_plat_info_t* get_mali_plat_data(void) {
- return &mali_plat_data;
-}
-
-int get_mali_freq_level(int freq)
-{
- int i = 0, level = -1;
- int mali_freq_num;
-
- if (freq < 0)
- return level;
-
- mali_freq_num = mali_plat_data.dvfs_table_size - 1;
- if (freq < mali_plat_data.clk_sample[0])
- level = mali_freq_num-1;
- else if (freq >= mali_plat_data.clk_sample[mali_freq_num - 1])
- level = 0;
- else {
- for (i=0; i<mali_freq_num - 1 ;i++) {
- if (freq >= mali_plat_data.clk_sample[i] && freq < mali_plat_data.clk_sample[i + 1]) {
- level = i;
- level = mali_freq_num-level - 1;
- break;
- }
- }
- }
- return level;
-}
-
-unsigned int get_mali_max_level(void)
-{
- return mali_plat_data.dvfs_table_size - 1;
-}
-
-int get_gpu_max_clk_level(void)
-{
- return mali_plat_data.cfg_clock;
-}
-
-#ifdef CONFIG_GPU_THERMAL
-static void set_limit_mali_freq(u32 idx)
-{
- if (mali_plat_data.limit_on == 0)
- return;
- if (idx > mali_plat_data.turbo_clock || idx < mali_plat_data.scale_info.minclk)
- return;
- if (idx > mali_plat_data.maxclk_sysfs) {
- printk("idx > max freq\n");
- return;
- }
- mali_plat_data.scale_info.maxclk= idx;
- revise_mali_rt();
-}
-
-static u32 get_limit_mali_freq(void)
-{
- return mali_plat_data.scale_info.maxclk;
-}
-
-#ifdef CONFIG_DEVFREQ_THERMAL
-static u32 get_mali_utilization(void)
-{
- return (_mali_ukk_utilization_pp() * 100) / 256;
-}
-#endif
-#endif
-
-#ifdef CONFIG_GPU_THERMAL
-static u32 set_limit_pp_num(u32 num)
-{
- u32 ret = -1;
- if (mali_plat_data.limit_on == 0)
- goto quit;
- if (num > mali_plat_data.cfg_pp ||
- num < mali_plat_data.scale_info.minpp)
- goto quit;
-
- if (num > mali_plat_data.maxpp_sysfs) {
- printk("pp > sysfs set pp\n");
- goto quit;
- }
-
- mali_plat_data.scale_info.maxpp = num;
- revise_mali_rt();
- ret = 0;
-quit:
- return ret;
-}
-#ifdef CONFIG_DEVFREQ_THERMAL
-static u32 mali_get_online_pp(void)
-{
- unsigned int val;
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
-
- val = readl(pmali_plat->reg_base_aobus + 0xf0) & 0xff;
- if (val == 0x07) /* No pp is working */
- return 0;
-
- return mali_executor_get_num_cores_enabled();
-}
-#endif
-#endif
-
-void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data);
-int mali_meson_init_start(struct platform_device* ptr_plt_dev)
-{
- dev_set_drvdata(&ptr_plt_dev->dev, &mali_plat_data);
- mali_dt_info(ptr_plt_dev, &mali_plat_data);
- mali_clock_init_clk_tree(ptr_plt_dev);
- return 0;
-}
-
-int mali_meson_init_finish(struct platform_device* ptr_plt_dev)
-{
- if (mali_core_scaling_init(&mali_plat_data) < 0)
- return -1;
- return 0;
-}
-
-int mali_meson_uninit(struct platform_device* ptr_plt_dev)
-{
- mali_core_scaling_term();
- return 0;
-}
-
-static int mali_cri_light_suspend(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- mali_pm_statue = 1;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_suspend(device);
- }
- mali_pmu_power_down_all(pmu);
- return ret;
-}
-
-static int mali_cri_light_resume(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- mali_pmu_power_up_all(pmu);
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_resume(device);
- }
- mali_pm_statue = 0;
- return ret;
-}
-
-static int mali_cri_deep_suspend(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->suspend(device);
- }
- mali_pmu_power_down_all(pmu);
- return ret;
-}
-
-static int mali_cri_deep_resume(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- mali_pmu_power_up_all(pmu);
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->resume(device);
- }
- return ret;
-
-}
-
-int mali_light_suspend(struct device *device)
-{
- int ret = 0;
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- 0, 0, 0, 0, 0);
-#endif
-
- flush_scaling_job();
- /* clock scaling. Kasin..*/
- ret = mali_clock_critical(mali_cri_light_suspend, (size_t)device);
- disable_clock();
- return ret;
-}
-
-int mali_light_resume(struct device *device)
-{
- int ret = 0;
- enable_clock();
- ret = mali_clock_critical(mali_cri_light_resume, (size_t)device);
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- get_current_frequency(), 0, 0, 0, 0);
-#endif
- return ret;
-}
-
-int mali_deep_suspend(struct device *device)
-{
- int ret = 0;
-
- mali_pm_statue = 1;
- flush_scaling_job();
-
-
- /* clock scaling off. Kasin... */
- ret = mali_clock_critical(mali_cri_deep_suspend, (size_t)device);
- disable_clock();
- return ret;
-}
-
-int mali_deep_resume(struct device *device)
-{
- int ret = 0;
-
- /* clock scaling up. Kasin.. */
- enable_clock();
- ret = mali_clock_critical(mali_cri_deep_resume, (size_t)device);
- mali_pm_statue = 0;
- return ret;
-
-}
-
-void mali_post_init(void)
-{
-#ifdef CONFIG_GPU_THERMAL
- int err;
- struct gpufreq_cooling_device *gcdev = NULL;
- struct gpucore_cooling_device *gccdev = NULL;
-
- gcdev = gpufreq_cooling_alloc();
- register_gpu_freq_info(get_current_frequency);
- if (IS_ERR(gcdev))
- printk("malloc gpu cooling buffer error!!\n");
- else if (!gcdev)
- printk("system does not enable thermal driver\n");
- else {
- gcdev->get_gpu_freq_level = get_mali_freq_level;
- gcdev->get_gpu_max_level = get_mali_max_level;
- gcdev->set_gpu_freq_idx = set_limit_mali_freq;
- gcdev->get_gpu_current_max_level = get_limit_mali_freq;
-#ifdef CONFIG_DEVFREQ_THERMAL
- gcdev->get_gpu_freq = get_mali_freq;
- gcdev->get_gpu_loading = get_mali_utilization;
- gcdev->get_online_pp = mali_get_online_pp;
-#endif
- err = gpufreq_cooling_register(gcdev);
-#ifdef CONFIG_DEVFREQ_THERMAL
- aml_thermal_min_update(gcdev->cool_dev);
-#endif
- if (err < 0)
- printk("register GPU cooling error\n");
- printk("gpu cooling register okay with err=%d\n",err);
- }
-
- gccdev = gpucore_cooling_alloc();
- if (IS_ERR(gccdev))
- printk("malloc gpu core cooling buffer error!!\n");
- else if (!gccdev)
- printk("system does not enable thermal driver\n");
- else {
- gccdev->max_gpu_core_num=mali_plat_data.cfg_pp;
- gccdev->set_max_pp_num=set_limit_pp_num;
- err = (int)gpucore_cooling_register(gccdev);
-#ifdef CONFIG_DEVFREQ_THERMAL
- aml_thermal_min_update(gccdev->cool_dev);
-#endif
- if (err < 0)
- printk("register GPU cooling error\n");
- printk("gpu core cooling register okay with err=%d\n",err);
- }
-#endif
-}
+++ /dev/null
-/*
- * Copyright (C) 2013 ARM Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
- *
- * A copy of the licence is included with the program, and can also be obtained from Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-/**
- * @file arm_core_scaling.c
- * Example core scaling policy.
- */
-
-#include <linux/version.h>
-#include <linux/module.h>
-#include <linux/workqueue.h>
-#include <linux/mali/mali_utgard.h>
-#include <mali_kernel_common.h>
-#include <mali_osk_profiling.h>
-
-#if AMLOGIC_GPU_USE_GPPLL
-#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 16)
-#include <linux/amlogic/amports/gp_pll.h>
-#else
-#include <linux/amlogic/media/clk/gp_pll.h>
-#endif
-#endif
-#define LOG_MALI_SCALING 1
-#include "meson_main2.h"
-#include "mali_clock.h"
-
-static int currentStep;
-#ifndef CONFIG_MALI_DVFS
-static int num_cores_enabled;
-static int lastStep;
-static struct work_struct wq_work;
-static mali_plat_info_t* pmali_plat = NULL;
-#endif
-static int scaling_mode = MALI_PP_FS_SCALING;
-//static int scaling_mode = MALI_SCALING_DISABLE;
-//static int scaling_mode = MALI_PP_SCALING;
-
-#if AMLOGIC_GPU_USE_GPPLL
-static struct gp_pll_user_handle_s *gp_pll_user_gpu;
-static int is_gp_pll_get;
-static int is_gp_pll_put;
-#endif
-
-static unsigned scaling_dbg_level = 0;
-module_param(scaling_dbg_level, uint, 0644);
-MODULE_PARM_DESC(scaling_dbg_level , "scaling debug level");
-
-#define scalingdbg(level, fmt, arg...) \
- do { \
- if (scaling_dbg_level >= (level)) \
- printk(fmt , ## arg); \
- } while (0)
-
-#ifndef CONFIG_MALI_DVFS
-static inline void mali_clk_exected(void)
-{
- mali_dvfs_threshold_table * pdvfs = pmali_plat->dvfs_table;
- uint32_t execStep = currentStep;
-#if AMLOGIC_GPU_USE_GPPLL
- mali_dvfs_threshold_table *dvfs_tbl = &pmali_plat->dvfs_table[currentStep];
-#endif
-
- //if (pdvfs[currentStep].freq_index == pdvfs[lastStep].freq_index) return;
- if ((pdvfs[execStep].freq_index == pdvfs[lastStep].freq_index) ||
- (pdvfs[execStep].clk_freq == pdvfs[lastStep].clk_freq)){
- return;
- }
-
-#if AMLOGIC_GPU_USE_GPPLL
- if (0 == strcmp(dvfs_tbl->clk_parent, "gp0_pll")) {
- gp_pll_request(gp_pll_user_gpu);
- if (!is_gp_pll_get) {
- //printk("not get pll\n");
- execStep = currentStep - 1;
- }
- } else {
- //not get the gp pll, do need put
- is_gp_pll_get = 0;
- is_gp_pll_put = 0;
- gp_pll_release(gp_pll_user_gpu);
- }
-#endif
-
- //mali_dev_pause();
- mali_clock_set(pdvfs[execStep].freq_index);
- //mali_dev_resume();
- lastStep = execStep;
-#if AMLOGIC_GPU_USE_GPPLL
- if (is_gp_pll_put) {
- //printk("release gp0 pll\n");
- gp_pll_release(gp_pll_user_gpu);
- gp_pll_request(gp_pll_user_gpu);
- is_gp_pll_get = 0;
- is_gp_pll_put = 0;
- }
-#endif
-
-}
-#if AMLOGIC_GPU_USE_GPPLL
-static int gp_pll_user_cb_gpu(struct gp_pll_user_handle_s *user,
- int event)
-{
- if (event == GP_PLL_USER_EVENT_GRANT) {
- //printk("granted\n");
- is_gp_pll_get = 1;
- is_gp_pll_put = 0;
- schedule_work(&wq_work);
- } else if (event == GP_PLL_USER_EVENT_YIELD) {
- //printk("ask for yield\n");
- is_gp_pll_get = 0;
- is_gp_pll_put = 1;
- schedule_work(&wq_work);
- }
-
- return 0;
-}
-#endif
-
-static void do_scaling(struct work_struct *work)
-{
- mali_dvfs_threshold_table * pdvfs = pmali_plat->dvfs_table;
- int err = mali_perf_set_num_pp_cores(num_cores_enabled);
- scalingdbg(1, "set pp cores to %d\n", num_cores_enabled);
- MALI_DEBUG_ASSERT(0 == err);
- MALI_IGNORE(err);
- scalingdbg(1, "pdvfs[%d].freq_index=%d, pdvfs[%d].freq_index=%d\n",
- currentStep, pdvfs[currentStep].freq_index,
- lastStep, pdvfs[lastStep].freq_index);
- mali_clk_exected();
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- get_current_frequency(),
- 0, 0, 0, 0);
-#endif
-}
-#endif
-
-u32 revise_set_clk(u32 val, u32 flush)
-{
- u32 ret = 0;
-#ifndef CONFIG_MALI_DVFS
- mali_scale_info_t* pinfo;
-
- pinfo = &pmali_plat->scale_info;
-
- if (val < pinfo->minclk)
- val = pinfo->minclk;
- else if (val > pinfo->maxclk)
- val = pinfo->maxclk;
-
- if (val != currentStep) {
- currentStep = val;
- if (flush)
- schedule_work(&wq_work);
- else
- ret = 1;
- }
-#endif
- return ret;
-}
-
-void get_mali_rt_clkpp(u32* clk, u32* pp)
-{
-#ifndef CONFIG_MALI_DVFS
- *clk = currentStep;
- *pp = num_cores_enabled;
-#endif
-}
-
-u32 set_mali_rt_clkpp(u32 clk, u32 pp, u32 flush)
-{
- u32 ret = 0;
-#ifndef CONFIG_MALI_DVFS
- mali_scale_info_t* pinfo;
- u32 flush_work = 0;
-
- pinfo = &pmali_plat->scale_info;
- if (clk < pinfo->minclk)
- clk = pinfo->minclk;
- else if (clk > pinfo->maxclk)
- clk = pinfo->maxclk;
-
- if (clk != currentStep) {
- currentStep = clk;
- if (flush)
- flush_work++;
- else
- ret = 1;
- }
- if (pp < pinfo->minpp)
- pp = pinfo->minpp;
- else if (pp > pinfo->maxpp)
- pp = pinfo->maxpp;
-
- if (pp != num_cores_enabled) {
- num_cores_enabled = pp;
- if (flush)
- flush_work++;
- else
- ret = 1;
- }
-
- if (flush_work)
- schedule_work(&wq_work);
-#endif
- return ret;
-}
-
-void revise_mali_rt(void)
-{
-#ifndef CONFIG_MALI_DVFS
- set_mali_rt_clkpp(currentStep, num_cores_enabled, 1);
-#endif
-}
-
-void flush_scaling_job(void)
-{
-#ifndef CONFIG_MALI_DVFS
- cancel_work_sync(&wq_work);
-#endif
-}
-
-#ifndef CONFIG_MALI_DVFS
-static u32 enable_one_core(void)
-{
- scalingdbg(2, "meson: one more pp, curent has %d pp cores\n", num_cores_enabled + 1);
- return set_mali_rt_clkpp(currentStep, num_cores_enabled + 1, 0);
-}
-
-static u32 disable_one_core(void)
-{
- scalingdbg(2, "meson: disable one pp, current has %d pp cores\n", num_cores_enabled - 1);
- return set_mali_rt_clkpp(currentStep, num_cores_enabled - 1, 0);
-}
-
-static u32 enable_max_num_cores(void)
-{
- return set_mali_rt_clkpp(currentStep, pmali_plat->scale_info.maxpp, 0);
-}
-
-static u32 enable_pp_cores(u32 val)
-{
- scalingdbg(2, "meson: enable %d pp cores\n", val);
- return set_mali_rt_clkpp(currentStep, val, 0);
-}
-#endif
-
-int mali_core_scaling_init(mali_plat_info_t *mali_plat)
-{
-#ifndef CONFIG_MALI_DVFS
- if (mali_plat == NULL) {
- scalingdbg(2, " Mali platform data is NULL!!!\n");
- return -1;
- }
-
- pmali_plat = mali_plat;
- num_cores_enabled = pmali_plat->sc_mpp;
-#if AMLOGIC_GPU_USE_GPPLL
- gp_pll_user_gpu = gp_pll_user_register("gpu", 1,
- gp_pll_user_cb_gpu);
- //not get the gp pll, do need put
- is_gp_pll_get = 0;
- is_gp_pll_put = 0;
- if (gp_pll_user_gpu == NULL) printk("register gp pll user for gpu failed\n");
-#endif
-
- currentStep = pmali_plat->def_clock;
- lastStep = currentStep;
- INIT_WORK(&wq_work, do_scaling);
-#endif
- return 0;
- /* NOTE: Mali is not fully initialized at this point. */
-}
-
-void mali_core_scaling_term(void)
-{
-#ifndef CONFIG_MALI_DVFS
- flush_scheduled_work();
-#if AMLOGIC_GPU_USE_GPPLL
- gp_pll_user_unregister(gp_pll_user_gpu);
-#endif
-#endif
-}
-
-#ifndef CONFIG_MALI_DVFS
-static u32 mali_threshold [] = {
- 102, /* 40% */
- 128, /* 50% */
- 230, /* 90% */
-};
-#endif
-
-void mali_pp_scaling_update(struct mali_gpu_utilization_data *data)
-{
-#ifndef CONFIG_MALI_DVFS
- int ret = 0;
-
- if (mali_threshold[2] < data->utilization_pp)
- ret = enable_max_num_cores();
- else if (mali_threshold[1]< data->utilization_pp)
- ret = enable_one_core();
- else if (0 < data->utilization_pp)
- ret = disable_one_core();
- if (ret == 1)
- schedule_work(&wq_work);
-#endif
-}
-
-#if LOG_MALI_SCALING
-void trace_utilization(struct mali_gpu_utilization_data *data, u32 current_idx, u32 next,
- u32 current_pp, u32 next_pp)
-{
- char direction;
- if (next > current_idx)
- direction = '>';
- else if ((current_idx > pmali_plat->scale_info.minpp) && (next < current_idx))
- direction = '<';
- else
- direction = '~';
-
- scalingdbg(2, "[SCALING]%c (%3d-->%3d)@%3d{%3d - %3d}. pp:(%d-->%d)\n",
- direction,
- get_mali_freq(current_idx),
- get_mali_freq(next),
- data->utilization_gpu,
- pmali_plat->dvfs_table[current_idx].downthreshold,
- pmali_plat->dvfs_table[current_idx].upthreshold,
- current_pp, next_pp);
-}
-#endif
-
-#ifndef CONFIG_MALI_DVFS
-static int mali_stay_count = 0;
-static void mali_decide_next_status(struct mali_gpu_utilization_data *data, int* next_fs_idx,
- int* pp_change_flag)
-{
- u32 utilization, mali_up_limit, decided_fs_idx;
- u32 ld_left, ld_right;
- u32 ld_up, ld_down;
- u32 change_mode;
-
- *pp_change_flag = 0;
- change_mode = 0;
- utilization = data->utilization_gpu;
-
- scalingdbg(5, "line(%d), scaling_mode=%d, MALI_TURBO_MODE=%d, turbo=%d, maxclk=%d\n",
- __LINE__, scaling_mode, MALI_TURBO_MODE,
- pmali_plat->turbo_clock, pmali_plat->scale_info.maxclk);
-
- mali_up_limit = (scaling_mode == MALI_TURBO_MODE) ?
- pmali_plat->turbo_clock : pmali_plat->scale_info.maxclk;
- decided_fs_idx = currentStep;
-
- ld_up = pmali_plat->dvfs_table[currentStep].upthreshold;
- ld_down = pmali_plat->dvfs_table[currentStep].downthreshold;
-
- scalingdbg(2, "utilization=%d, ld_up=%d\n ", utilization, ld_up);
- if (utilization >= ld_up) { /* go up */
-
- scalingdbg(2, "currentStep=%d, mali_up_limit=%d\n ", currentStep, mali_up_limit);
- if (currentStep < mali_up_limit) {
- change_mode = 1;
- if ((currentStep < pmali_plat->def_clock) && (utilization > pmali_plat->bst_gpu))
- decided_fs_idx = pmali_plat->def_clock;
- else
- decided_fs_idx++;
- }
- if ((data->utilization_pp >= ld_up) &&
- (num_cores_enabled < pmali_plat->scale_info.maxpp)) {
- if ((num_cores_enabled < pmali_plat->sc_mpp) && (data->utilization_pp >= pmali_plat->bst_pp)) {
- *pp_change_flag = 1;
- change_mode = 1;
- } else if (change_mode == 0) {
- *pp_change_flag = 2;
- change_mode = 1;
- }
- }
-#if LOG_MALI_SCALING
- scalingdbg(2, "[nexting..] [LD:%d]-> FS[CRNT:%d LMT:%d NEXT:%d] PP[NUM:%d LMT:%d MD:%d][F:%d]\n",
- data->utilization_pp, currentStep, mali_up_limit, decided_fs_idx,
- num_cores_enabled, pmali_plat->scale_info.maxpp, *pp_change_flag, change_mode);
-#endif
- } else if (utilization <= ld_down) { /* go down */
- if (mali_stay_count > 0) {
- *next_fs_idx = decided_fs_idx;
- mali_stay_count--;
- return;
- }
-
- if (num_cores_enabled > pmali_plat->sc_mpp) {
- change_mode = 1;
- if (data->utilization_pp <= ld_down) {
- ld_left = data->utilization_pp * num_cores_enabled;
- ld_right = (pmali_plat->dvfs_table[currentStep].upthreshold) *
- (num_cores_enabled - 1);
- if (ld_left < ld_right) {
- change_mode = 2;
- }
- }
- } else if (currentStep > pmali_plat->scale_info.minclk) {
- change_mode = 1;
- } else if (num_cores_enabled > 1) { /* decrease PPS */
- if (data->utilization_pp <= ld_down) {
- ld_left = data->utilization_pp * num_cores_enabled;
- ld_right = (pmali_plat->dvfs_table[currentStep].upthreshold) *
- (num_cores_enabled - 1);
- scalingdbg(2, "ld_left=%d, ld_right=%d\n", ld_left, ld_right);
- if (ld_left < ld_right) {
- change_mode = 2;
- }
- }
- }
-
- if (change_mode == 1) {
- decided_fs_idx--;
- } else if (change_mode == 2) { /* decrease PPS */
- *pp_change_flag = -1;
- }
- }
-
- if (decided_fs_idx < 0 ) {
- printk("gpu debug, next index below 0\n");
- decided_fs_idx = 0;
- }
- if (decided_fs_idx > pmali_plat->scale_info.maxclk) {
- decided_fs_idx = pmali_plat->scale_info.maxclk;
- printk("gpu debug, next index above max, set to %d\n", decided_fs_idx);
- }
-
- if (change_mode)
- mali_stay_count = pmali_plat->dvfs_table[decided_fs_idx].keep_count;
- *next_fs_idx = decided_fs_idx;
-}
-#endif
-
-void mali_pp_fs_scaling_update(struct mali_gpu_utilization_data *data)
-{
-#ifndef CONFIG_MALI_DVFS
- int ret = 0;
- int pp_change_flag = 0;
- u32 next_idx = 0;
-
-#if LOG_MALI_SCALING
- u32 last_pp = num_cores_enabled;
-#endif
- mali_decide_next_status(data, &next_idx, &pp_change_flag);
-
- if (pp_change_flag == 1)
- ret = enable_pp_cores(pmali_plat->sc_mpp);
- else if (pp_change_flag == 2)
- ret = enable_one_core();
- else if (pp_change_flag == -1) {
- ret = disable_one_core();
- }
-
-#if LOG_MALI_SCALING
- if (pp_change_flag || (next_idx != currentStep))
- trace_utilization(data, currentStep, next_idx, last_pp, num_cores_enabled);
-#endif
-
- if (next_idx != currentStep) {
- ret = 1;
- currentStep = next_idx;
- }
-
- if (ret == 1)
- schedule_work(&wq_work);
-#ifdef CONFIG_MALI400_PROFILING
- else
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- get_current_frequency(),
- 0, 0, 0, 0);
-#endif
-#endif
-}
-
-u32 get_mali_schel_mode(void)
-{
- return scaling_mode;
-}
-
-void set_mali_schel_mode(u32 mode)
-{
-#ifndef CONFIG_MALI_DVFS
- MALI_DEBUG_ASSERT(mode < MALI_SCALING_MODE_MAX);
- if (mode >= MALI_SCALING_MODE_MAX)
- return;
- scaling_mode = mode;
-
- //disable thermal in turbo mode
- if (scaling_mode == MALI_TURBO_MODE) {
- pmali_plat->limit_on = 0;
- } else {
- pmali_plat->limit_on = 1;
- }
- /* set default performance range. */
- pmali_plat->scale_info.minclk = pmali_plat->cfg_min_clock;
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- pmali_plat->scale_info.minpp = pmali_plat->cfg_min_pp;
- pmali_plat->scale_info.maxpp = pmali_plat->cfg_pp;
-
- /* set current status and tune max freq */
- if (scaling_mode == MALI_PP_FS_SCALING) {
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- enable_pp_cores(pmali_plat->sc_mpp);
- } else if (scaling_mode == MALI_SCALING_DISABLE) {
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- enable_max_num_cores();
- } else if (scaling_mode == MALI_TURBO_MODE) {
- pmali_plat->scale_info.maxclk = pmali_plat->turbo_clock;
- enable_max_num_cores();
- }
- currentStep = pmali_plat->scale_info.maxclk;
- schedule_work(&wq_work);
-#endif
-}
-
-u32 get_current_frequency(void)
-{
- return get_mali_freq(currentStep);
-}
-
-void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data)
-{
-#ifndef CONFIG_MALI_DVFS
- if (mali_pm_statue)
- return;
-
- switch (scaling_mode) {
- case MALI_PP_FS_SCALING:
- mali_pp_fs_scaling_update(data);
- break;
- case MALI_PP_SCALING:
- mali_pp_scaling_update(data);
- break;
- default:
- break;
- }
-#endif
-}
-static u32 clk_cntl_save = 0;
-void mali_dev_freeze(void)
-{
- clk_cntl_save = mplt_read(HHI_MALI_CLK_CNTL);
-}
-
-void mali_dev_restore(void)
-{
-
- mplt_write(HHI_MALI_CLK_CNTL, clk_cntl_save);
- if (pmali_plat && pmali_plat->pdev) {
- mali_clock_init_clk_tree(pmali_plat->pdev);
- } else {
- printk("error: init clock failed, pmali_plat=%p, pmali_plat->pdev=%p\n",
- pmali_plat, pmali_plat == NULL ? NULL: pmali_plat->pdev);
- }
-}
-
-int mali_meson_get_gpu_data(struct mali_gpu_device_data *mgpu_data)
-{
- mgpu_data->get_clock_info = NULL;
- mgpu_data->get_freq = NULL;
- mgpu_data->set_freq = NULL;
- mgpu_data->utilization_callback = mali_gpu_utilization_callback;
- return 0;
-}
+++ /dev/null
-/*
- * AMLOGIC Mali fix driver.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the named License,
- * or any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
- *
- * Author: Tim Yao <timyao@amlogic.com>
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/timer.h>
-#include <asm/io.h>
-#include <linux/ioport.h>
-#include <linux/dma-mapping.h>
-
-#include <linux/module.h>
-
-#include <mach/am_regs.h>
-#include <mach/clock.h>
-#include <linux/io.h>
-#include <mach/io.h>
-#include <plat/io.h>
-#include <asm/io.h>
-
-#include "mali_kernel_common.h"
-#include "mali_osk.h"
-#include "mali_platform.h"
-#include "mali_fix.h"
-
-#define MALI_MM1_REG_ADDR 0xd0064000
-#define MALI_MMU_REGISTER_INT_STATUS 0x0008
-#define MALI_MM2_REG_ADDR 0xd0065000
-#define MALI_MMU_REGISTER_INT_STATUS 0x0008
-#define MALI_MM_REG_SIZE 0x1000
-
-#define READ_MALI_MMU1_REG(r) (ioread32(((u8*)mali_mm1_regs) + r))
-#define READ_MALI_MMU2_REG(r) (ioread32(((u8*)mali_mm2_regs) + r))
-
-extern int mali_PP0_int_cnt(void);
-extern int mali_PP1_int_cnt(void);
-
-#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
-static ulong * mali_mm1_regs = NULL;
-static ulong * mali_mm2_regs = NULL;
-static struct timer_list timer;
-
-static u32 mali_pp1_int_count = 0;
-static u32 mali_pp2_int_count = 0;
-static u32 mali_pp1_mmu_int_count = 0;
-static u32 mali_pp2_mmu_int_count = 0;
-static u32 mali_mmu_int_process_state[2];
-
-static void timer_callback(ulong data)
-{
- unsigned long mali_flags;
-
- mali_pp1_int_count = mali_PP0_int_cnt();
- mali_pp2_int_count = mali_PP1_int_cnt();
-
- /* lock mali_clock_gating when access Mali registers */
- mali_flags = mali_clock_gating_lock();
-
- if (readl((u32 *)P_HHI_MALI_CLK_CNTL) & 0x100) {
- /* polling for PP1 MMU interrupt */
- if (mali_mmu_int_process_state[0] == MMU_INT_NONE) {
- if (READ_MALI_MMU1_REG(MALI_MMU_REGISTER_INT_STATUS) != 0) {
- mali_pp1_mmu_int_count++;
- MALI_DEBUG_PRINT(3, ("Mali MMU: core0 page fault emit \n"));
- mali_mmu_int_process_state[0] = MMU_INT_HIT;
- __raw_writel(1, (volatile void *)P_ISA_TIMERC);
- }
- }
-
- /* polling for PP2 MMU interrupt */
- if (mali_mmu_int_process_state[1] == MMU_INT_NONE) {
- if (READ_MALI_MMU2_REG(MALI_MMU_REGISTER_INT_STATUS) != 0) {
- mali_pp2_mmu_int_count++;
- MALI_DEBUG_PRINT(3, ("Mali MMU: core1 page fault emit \n"));
- mali_mmu_int_process_state[1] = MMU_INT_HIT;
- __raw_writel(1, (volatile void *)P_ISA_TIMERC);
- }
- }
- }
-
- mali_clock_gating_unlock(mali_flags);
-
- timer.expires = jiffies + HZ/100;
-
- add_timer(&timer);
-}
-
-void malifix_set_mmu_int_process_state(int index, int state)
-{
- if (index < 2)
- mali_mmu_int_process_state[index] = state;
-}
-
-int malifix_get_mmu_int_process_state(int index)
-{
- if (index < 2)
- return mali_mmu_int_process_state[index];
- return 0;
-}
-#endif
-
-void malifix_init(void)
-{
-#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
- if (!mali_meson_is_revb())
- return;
-
- if ((mali_mm1_regs) && (mali_mm2_regs)) return;
- mali_mmu_int_process_state[0] = 0;
- mali_mmu_int_process_state[1] = 0;
-
- /* set up Timer C as a 1uS one-shot timer */
- aml_clr_reg32_mask(P_ISA_TIMER_MUX, (1<<18)|(1<<14)|(3<<4));
- aml_set_reg32_mask(P_ISA_TIMER_MUX, (1<<18)|(0<<14)|(0<<4));
-
- setup_timer(&timer, timer_callback, 0);
-
- mali_mm1_regs = (ulong *)ioremap_nocache(MALI_MM1_REG_ADDR, MALI_MM_REG_SIZE);
- if (mali_mm1_regs)
- printk("Mali pp1 MMU register mapped at %p...\n", mali_mm1_regs);
-
- mali_mm2_regs = (ulong *)ioremap_nocache(MALI_MM2_REG_ADDR, MALI_MM_REG_SIZE);
- if (mali_mm2_regs)
- printk("Mali pp2 MMU register mapped at %p...\n", mali_mm2_regs);
-
- if ((mali_mm1_regs != NULL) && (mali_mm2_regs != NULL))
- mod_timer(&timer, jiffies + HZ/100);
-#endif
-}
-
-void malifix_exit(void)
-{
-#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
- if (!mali_meson_is_revb())
- return;
-
- del_timer(&timer);
-
- if (mali_mm1_regs != NULL)
- iounmap(mali_mm1_regs);
- mali_mm1_regs = NULL;
-
- if (mali_mm2_regs != NULL)
- iounmap(mali_mm2_regs);
- mali_mm2_regs = NULL;
-
-#endif
- return;
-}
-
-#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
-module_param(mali_pp1_int_count, uint, 0664);
-MODULE_PARM_DESC(mali_pp1_int_count, "Mali PP1 interrupt count\n");
-
-module_param(mali_pp2_int_count, uint, 0664);
-MODULE_PARM_DESC(mali_pp2_int_count, "Mali PP1 interrupt count\n");
-
-module_param(mali_pp1_mmu_int_count, uint, 0664);
-MODULE_PARM_DESC(mali_pp1_mmu_int_count, "Mali PP1 mmu interrupt count\n");
-
-module_param(mali_pp2_mmu_int_count, uint, 0664);
-MODULE_PARM_DESC(mali_pp2_mmu_int_count, "Mali PP2 mmu interrupt count\n");
-#endif
-
-MODULE_DESCRIPTION("AMLOGIC mali fix driver");
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Tim Yao <timyao@amlogic.com>");
+++ /dev/null
-#ifndef MALI_FIX_H
-#define MALI_FIX_H
-
-#define MMU_INT_NONE 0
-#define MMU_INT_HIT 1
-#define MMU_INT_TOP 2
-#define MMU_INT_BOT 3
-
-extern void malifix_init(void);
-extern void malifix_exit(void);
-extern void malifix_set_mmu_int_process_state(int, int);
-extern int malifix_get_mmu_int_process_state(int);
-extern int mali_meson_is_revb(void);
-#endif /* MALI_FIX_H */
+++ /dev/null
-/*
- * This confidential and proprietary software may be used only as
- * authorised by a licensing agreement from AMLOGIC, INC.
- * (C) COPYRIGHT 2011 AMLOGIC, INC.
- * ALL RIGHTS RESERVED
- * The entire notice above must be reproduced on all authorised
- * copies and copies may only be made to the extent permitted
- * by a licensing agreement from AMLOGIC, INC.
- */
-
-/**
- * @file mali_platform.c
- * Platform specific Mali driver functions for meson platform
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/dma-mapping.h>
-#include <linux/spinlock.h>
-#include <linux/spinlock_types.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <mach/am_regs.h>
-#include <mach/clock.h>
-
-#include "mali_kernel_common.h"
-#include "mali_osk.h"
-#include "mali_platform.h"
-#include "mali_poweron_reg.h"
-#include "mali_fix.h"
-#include "mali_platform.h"
-
-static int last_power_mode = -1;
-static int mali_init_flag = 0;
-static const u32 poweron_data[] =
-{
-/* commands */
-/* 000 */ 0x00000040, 0x20400000, 0x00000300, 0x30040000,
-/* 010 */ 0x00000400, 0x400a0000, 0x0f000033, 0x10000042,
-/* 020 */ 0x00300c00, 0x10000040, 0x4c000001, 0x00000000,
-/* 030 */ 0x00000000, 0x60000000, 0x00000000, 0x00000000,
-/* 040 */ 0x00004000, 0x00002000, 0x00000210, 0x0000203f,
-/* 050 */ 0x00000220, 0x0000203f, 0x00000230, 0x0000203f,
-/* 060 */ 0x00000240, 0x0000203f, 0x00000250, 0x0000203f,
-/* 070 */ 0x00000260, 0x0000203f, 0x00000270, 0x0000203f,
-/* 080 */ 0x00000280, 0x0000203f, 0x00000290, 0x0000203f,
-/* 090 */ 0x000002a0, 0x0000203f, 0x000002b0, 0x0000203f,
-/* 0a0 */ 0x000002c0, 0x0000203f, 0x000002d0, 0x0000203f,
-/* 0b0 */ 0x000002e0, 0x0000203f, 0x000002f0, 0x0000203f,
-/* 0c0 */ 0x00002000, 0x00002000, 0x00002010, 0x0000203f,
-/* 0d0 */ 0x00002020, 0x0000203f, 0x00002030, 0x0000203f,
-/* 0e0 */ 0x00002040, 0x0000203f, 0x00002050, 0x0000203f,
-/* 0f0 */ 0x00002060, 0x0000203f, 0x00002070, 0x0000203f,
-/* 100 */ 0x00002080, 0x0000203f, 0x00002090, 0x0000203f,
-/* 110 */ 0x000020a0, 0x0000203f, 0x000020b0, 0x0000203f,
-/* 120 */ 0x000020c0, 0x0000203f, 0x000020d0, 0x0000203f,
-/* 130 */ 0x000020e0, 0x0000203f, 0x000020f0, 0x0000203f,
-/* 140 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 150 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 160 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 170 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 180 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 190 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 1a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 1b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 1c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 1d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 1e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 1f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 200 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 210 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 220 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 230 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 240 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 250 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 260 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 270 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 280 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 290 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 2a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 2b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 2c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 2d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 2e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 2f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* const */
-/* 300 */ 0x3f2a6400, 0xbf317600, 0x3e8d8e00, 0x00000000,
-/* 310 */ 0x3f2f7000, 0x3f36e200, 0x3e10c500, 0x00000000,
-/* 320 */ 0xbe974e00, 0x3dc35300, 0x3f735800, 0x00000000,
-/* 330 */ 0x00000000, 0x00000000, 0x00000000, 0x3f800000,
-/* 340 */ 0x42b00000, 0x42dc0000, 0x3f800000, 0x3f800000,
-/* 350 */ 0x42b00000, 0x42dc0000, 0x00000000, 0x00000000,
-/* 360 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 370 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 380 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 390 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 3a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 3b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 3c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 3d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 3e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 3f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* inst */
-/* 400 */ 0xad4ad6b5, 0x438002b5, 0x0007ffe0, 0x00001e00,
-/* 410 */ 0xad4ad694, 0x038002b5, 0x0087ffe0, 0x00005030,
-/* 420 */ 0xad4bda56, 0x038002b5, 0x0007ffe0, 0x00001c10,
-/* 430 */ 0xad4ad6b5, 0x038002b5, 0x4007fee0, 0x00001c00
-};
-
-static struct clk *mali_clk = NULL;
-
-#if MESON_CPU_TYPE <= MESON_CPU_TYPE_MESON6
-
-#define OFFSET_MMU_DTE 0
-#define OFFSET_MMU_PTE 4096
-#define OFFSET_MMU_VIRTUAL_ZERO 8192
-
-#define INT_MALI_GP_BITS (1<<16)
-#define INT_MALI_PP_BITS (1<<18)
-#define INT_MALI_PP_MMU_BITS (1<<19)
-#define INT_ALL (0xffffffff)
-
-#define INT_MALI_PP_MMU_PAGE_FAULT (1<<0)
-
-#define MMU_FLAG_DTE_PRESENT 0x01
-#define MMU_FLAG_PTE_PAGE_PRESENT 0x01
-#define MMU_FLAG_PTE_RD_PERMISSION 0x02
-#define MMU_FLAG_PTE_WR_PERMISSION 0x04
-
-//static int mali_revb_flag = -1;
-static DEFINE_SPINLOCK(lock);
-extern int mali_revb_flag;
-int mali_meson_is_revb(void)
-{
- printk("mail version=%d\n",mali_revb_flag);
- if (mali_revb_flag == -1)
- mali_revb_flag = 1;
- else if (mali_revb_flag == 0)
- panic("rev-a! you should neet earlier version of mali_driver.!\n");
-
- return mali_revb_flag;
-}
-
-static void mali_meson_poweron(int first_poweron)
-{
- unsigned long flags;
- u32 p, p_aligned;
- dma_addr_t p_phy;
- int i;
- unsigned int_mask;
-
- if(!first_poweron) {
- if ((last_power_mode != -1) && (last_power_mode != MALI_POWER_MODE_DEEP_SLEEP)) {
- MALI_DEBUG_PRINT(3, ("Maybe your system not deep sleep now.......\n"));
- //printk("Maybe your system not deep sleep now.......\n");
- return;
- }
- }
-
- MALI_DEBUG_PRINT(2, ("mali_meson_poweron: Mali APB bus accessing\n"));
- if (READ_MALI_REG(MALI_PP_PP_VERSION) != MALI_PP_PP_VERSION_MAGIC) {
- MALI_DEBUG_PRINT(3, ("mali_meson_poweron: Mali APB bus access failed\n"));
- //printk("mali_meson_poweron: Mali APB bus access failed.");
- return;
- }
- MALI_DEBUG_PRINT(2, ("..........accessing done.\n"));
- if (READ_MALI_REG(MALI_MMU_DTE_ADDR) != 0) {
- MALI_DEBUG_PRINT(3, ("mali_meson_poweron: Mali is not really powered off\n"));
- //printk("mali_meson_poweron: Mali is not really powered off.");
- return;
- }
-
- p = (u32)kcalloc(4096 * 4, 1, GFP_KERNEL);
- if (!p) {
- printk("mali_meson_poweron: NOMEM in meson_poweron\n");
- return;
- }
-
- p_aligned = __ALIGN_MASK(p, 4096);
-
- /* DTE */
- *(u32 *)(p_aligned) = (virt_to_phys((void *)p_aligned) + OFFSET_MMU_PTE) | MMU_FLAG_DTE_PRESENT;
- /* PTE */
- for (i=0; i<1024; i++) {
- *(u32 *)(p_aligned + OFFSET_MMU_PTE + i*4) =
- (virt_to_phys((void *)p_aligned) + OFFSET_MMU_VIRTUAL_ZERO + 4096 * i) |
- MMU_FLAG_PTE_PAGE_PRESENT |
- MMU_FLAG_PTE_RD_PERMISSION;
- }
-
- /* command & data */
- memcpy((void *)(p_aligned + OFFSET_MMU_VIRTUAL_ZERO), poweron_data, 4096);
-
- p_phy = dma_map_single(NULL, (void *)p_aligned, 4096 * 3, DMA_TO_DEVICE);
-
- /* Set up Mali GP MMU */
- WRITE_MALI_REG(MALI_MMU_DTE_ADDR, p_phy);
- WRITE_MALI_REG(MALI_MMU_CMD, 0);
-
- if ((READ_MALI_REG(MALI_MMU_STATUS) & 1) != 1)
- printk("mali_meson_poweron: MMU enabling failed.\n");
-
- /* Set up Mali command registers */
- WRITE_MALI_REG(MALI_APB_GP_VSCL_START, 0);
- WRITE_MALI_REG(MALI_APB_GP_VSCL_END, 0x38);
-
- spin_lock_irqsave(&lock, flags);
-
- int_mask = READ_MALI_REG(MALI_APB_GP_INT_MASK);
- WRITE_MALI_REG(MALI_APB_GP_INT_CLEAR, 0x707bff);
- WRITE_MALI_REG(MALI_APB_GP_INT_MASK, 0);
-
- /* Start GP */
- WRITE_MALI_REG(MALI_APB_GP_CMD, 1);
-
- for (i = 0; i<100; i++)
- udelay(500);
-
- /* check Mali GP interrupt */
- if (READ_MALI_REG(MALI_APB_GP_INT_RAWSTAT) & 0x707bff)
- printk("mali_meson_poweron: Interrupt received.\n");
- else
- printk("mali_meson_poweron: No interrupt received.\n");
-
- /* force reset GP */
- WRITE_MALI_REG(MALI_APB_GP_CMD, 1 << 5);
-
- /* stop MMU paging and reset */
- WRITE_MALI_REG(MALI_MMU_CMD, 1);
- WRITE_MALI_REG(MALI_MMU_CMD, 6);
-
- for (i = 0; i<100; i++)
- udelay(500);
-
- WRITE_MALI_REG(MALI_APB_GP_INT_CLEAR, 0x3ff);
- WRITE_MALI_REG(MALI_MMU_INT_CLEAR, INT_ALL);
- WRITE_MALI_REG(MALI_MMU_INT_MASK, 0);
-
- WRITE_MALI_REG(MALI_APB_GP_INT_CLEAR, 0x707bff);
- WRITE_MALI_REG(MALI_APB_GP_INT_MASK, int_mask);
-
- spin_unlock_irqrestore(&lock, flags);
-
- dma_unmap_single(NULL, p_phy, 4096 * 3, DMA_TO_DEVICE);
-
- kfree((void *)p);
-
- /* Mali revision detection */
- if (last_power_mode == -1)
- mali_revb_flag = mali_meson_is_revb();
-}
-#else
-static void mali_meson_poweron(int first_poweron) {
- return;
-}
-#endif /*MESON_CPU_TYPE <= MESON_CPU_TYPE_MESON6 */
-
-_mali_osk_errcode_t mali_platform_init(void)
-{
- mali_clk = clk_get_sys("mali", "pll_fixed");
-
- if (mali_clk ) {
- if (!mali_init_flag) {
- clk_set_rate(mali_clk, 333000000);
- mali_clk->enable(mali_clk);
- malifix_init();
- mali_meson_poweron(1);
- mali_init_flag = 1;
- }
- MALI_SUCCESS;
- } else
- panic("linux kernel should > 3.0\n");
-
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6
- MALI_PRINT_ERROR(("Failed to lookup mali clock"));
- MALI_ERROR(_MALI_OSK_ERR_FAULT);
-#else
- MALI_SUCCESS;
-#endif /* CONFIG_ARCH_MESON6 */
-}
-
-_mali_osk_errcode_t mali_platform_deinit(void)
-{
- mali_init_flag =0;
- printk("MALI:mali_platform_deinit\n");
- malifix_exit();
-
- MALI_SUCCESS;
-}
-
-_mali_osk_errcode_t mali_platform_power_mode_change(mali_power_mode power_mode)
-{
- MALI_DEBUG_PRINT(3, ( "mali_platform_power_mode_change power_mode=%d\n", power_mode));
-
- switch (power_mode) {
- case MALI_POWER_MODE_LIGHT_SLEEP:
- case MALI_POWER_MODE_DEEP_SLEEP:
- /* Turn off mali clock gating */
- mali_clk->disable(mali_clk);
- break;
-
- case MALI_POWER_MODE_ON:
- /* Turn on MALI clock gating */
- mali_clk->enable(mali_clk);
- mali_meson_poweron(0);
- break;
- }
- last_power_mode = power_mode;
- MALI_SUCCESS;
-}
-
+++ /dev/null
-/*
- * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
- *
- * A copy of the licence is included with the program, and can also be obtained from Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-/**
- * @file mali_platform.h
- * Platform specific Mali driver functions
- */
-
-#ifndef __MALI_PLATFORM_H__
-#define __MALI_PLATFORM_H__
-
-#include "mali_osk.h"
-
-/** @brief description of power change reasons
- */
-typedef enum mali_power_mode_tag
-{
- MALI_POWER_MODE_ON, /**< Power Mali on */
- MALI_POWER_MODE_LIGHT_SLEEP, /**< Mali has been idle for a short time, or runtime PM suspend */
- MALI_POWER_MODE_DEEP_SLEEP, /**< Mali has been idle for a long time, or OS suspend */
-} mali_power_mode;
-
-/** @brief Platform specific setup and initialisation of MALI
- *
- * This is called from the entrypoint of the driver to initialize the platform
- *
- * @return _MALI_OSK_ERR_OK on success otherwise, a suitable _mali_osk_errcode_t error.
- */
-_mali_osk_errcode_t mali_platform_init(void);
-
-/** @brief Platform specific deinitialisation of MALI
- *
- * This is called on the exit of the driver to terminate the platform
- *
- * @return _MALI_OSK_ERR_OK on success otherwise, a suitable _mali_osk_errcode_t error.
- */
-_mali_osk_errcode_t mali_platform_deinit(void);
-
-/** @brief Platform specific powerdown sequence of MALI
- *
- * Notification from the Mali device driver stating the new desired power mode.
- * MALI_POWER_MODE_ON must be obeyed, while the other modes are optional.
- * @param power_mode defines the power modes
- * @return _MALI_OSK_ERR_OK on success otherwise, a suitable _mali_osk_errcode_t error.
- */
-_mali_osk_errcode_t mali_platform_power_mode_change(mali_power_mode power_mode);
-
-
-/** @brief Platform specific handling of GPU utilization data
- *
- * When GPU utilization data is enabled, this function will be
- * periodically called.
- *
- * @param utilization The workload utilization of the Mali GPU. 0 = no utilization, 256 = full utilization.
- */
-void mali_gpu_utilization_handler(u32 utilization);
-
-/** @brief Setting the power domain of MALI
- *
- * This function sets the power domain of MALI if Linux run time power management is enabled
- *
- * @param dev Reference to struct platform_device (defined in linux) used by MALI GPU
- */
-void set_mali_parent_power_domain(void* dev);
-
-#endif
+++ /dev/null
-/*
- * This confidential and proprietary software may be used only as
- * authorised by a licensing agreement from AMLOGIC, INC.
- * (C) COPYRIGHT 2011 AMLOGIC, INC.
- * ALL RIGHTS RESERVED
- * The entire notice above must be reproduced on all authorised
- * copies and copies may only be made to the extent permitted
- * by a licensing agreement from AMLOGIC, INC.
- */
-
-#ifndef MALI_POWERON_REG_H
-#define MALI_POWERON_REG_H
-
-#define MALI_PP_PP_VERSION_MAGIC 0xCD070100UL
-
-#if defined(IO_APB2_BUS_PHY_BASE)
-#define WRITE_MALI_REG(reg, val) \
- __raw_writel(val, (volatile void *)(reg - IO_APB2_BUS_PHY_BASE + IO_APB2_BUS_BASE))
-#define READ_MALI_REG(reg) \
- __raw_readl((volatile void *)(reg - IO_APB2_BUS_PHY_BASE + IO_APB2_BUS_BASE))
-#else
-#define WRITE_MALI_REG(reg, val) \
- __raw_writel(val, (volatile void *)(reg - IO_APB_BUS_PHY_BASE + IO_APB_BUS_BASE))
-#define READ_MALI_REG(reg) \
- __raw_readl((volatile void *)(reg - IO_APB_BUS_PHY_BASE + IO_APB_BUS_BASE))
-#endif
-
-#define MALI_APB_GP_VSCL_START 0xd0060000
-#define MALI_APB_GP_VSCL_END 0xd0060004
-#define MALI_APB_GP_CMD 0xd0060020
-#define MALI_APB_GP_INT_RAWSTAT 0xd0060024
-#define MALI_APB_GP_INT_CLEAR 0xd0060028
-#define MALI_APB_GP_INT_MASK 0xd006002c
-#define MALI_APB_GP_INT_STAT 0xd0060030
-
-#define MALI_MMU_DTE_ADDR 0xd0063000
-#define MALI_MMU_STATUS 0xd0063004
-#define MALI_MMU_CMD 0xd0063008
-#define MALI_MMU_RAW_STATUS 0xd0064014
-#define MALI_MMU_INT_CLEAR 0xd0064018
-#define MALI_MMU_INT_MASK 0xd006401c
-#define MALI_MMU_INT_STATUS 0xd0064020
-
-#define MALI_PP_MMU_DTE_ADDR 0xd0064000
-#define MALI_PP_MMU_STATUS 0xd0064004
-#define MALI_PP_MMU_CMD 0xd0064008
-#define MALI_PP_MMU_RAW_STATUS 0xd0064014
-#define MALI_PP_MMU_INT_CLEAR 0xd0064018
-#define MALI_PP_MMU_INT_MASK 0xd006401c
-#define MALI_PP_MMU_INT_STATUS 0xd0064020
-
-#define MALI_APB_PP_REND_LIST_ADDR 0xd0068000
-#define MALI_APB_PP_REND_RSW_BASE 0xd0068004
-#define MALI_APB_PP_REND_VERTEX_BASE 0xd0068008
-#define MALI_APB_PPSUBPIXEL_SPECIFIER 0xd0068048
-#define MALI_APB_WB0_SOURCE_SELECT 0xd0068100
-#define MALI_APB_WB0_TARGET_ADDR 0xd0068104
-#define MALI_APB_WB0_TARGET_SCANLINE_LENGTH 0xd0068114
-
-#define MALI_PP_PP_VERSION 0xd0069000
-#define MALI_PP_STATUS 0xd0069008
-#define MALI_PP_CTRL_MGMT 0xd006900C
-#define MALI_PP_INT_RAWSTAT 0xd0069020
-#define MALI_PP_INT_CLEAR 0xd0069024
-#define MALI_PP_INT_MASK 0xd0069028
-#define MALI_PP_INT_STAT 0xd006902C
-
-#endif /* MALI_POWERON_REG_H */
+++ /dev/null
-/*
- * platform.c
- *
- * clock source setting and resource config
- *
- * Created on: Dec 4, 2013
- * Author: amlogic
- */
-
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/module.h>
-#include <linux/ioport.h>
-#include <linux/slab.h>
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#include <asm/io.h>
-#include <linux/mali/mali_utgard.h>
-
-#include <common/mali_kernel_common.h>
-#include <common/mali_osk_profiling.h>
-#include <common/mali_pmu.h>
-
-#include "meson_main.h"
-#include "mali_fix.h"
-#include "mali_platform.h"
-
-/**
- * For Meson 6tvd.
- *
- */
-
-#if MESON_CPU_TYPE <= MESON_CPU_TYPE_MESON6TV
-
-u32 mali_dvfs_clk[1];
-u32 mali_dvfs_clk_sample[1];
-
-#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6TV
-#undef INT_MALI_GP
-#undef INT_MALI_GP_MMU
-#undef INT_MALI_PP
-#undef INT_MALI_PP2
-#undef INT_MALI_PP3
-#undef INT_MALI_PP4
-#undef INT_MALI_PP_MMU
-#undef INT_MALI_PP2_MMU
-#undef INT_MALI_PP3_MMU
-#undef INT_MALI_PP4_MMU
-
-#define INT_MALI_GP (48+32)
-#define INT_MALI_GP_MMU (49+32)
-#define INT_MALI_PP (50+32)
-#define INT_MALI_PP2 (58+32)
-#define INT_MALI_PP3 (60+32)
-#define INT_MALI_PP4 (62+32)
-#define INT_MALI_PP_MMU (51+32)
-#define INT_MALI_PP2_MMU (59+32)
-#define INT_MALI_PP3_MMU (61+32)
-#define INT_MALI_PP4_MMU (63+32)
-
-#ifndef CONFIG_MALI400_4_PP
-static struct resource meson_mali_resources[] =
-{
- MALI_GPU_RESOURCES_MALI400_MP2(0xd0060000,
- INT_MALI_GP, INT_MALI_GP_MMU,
- INT_MALI_PP, INT_MALI_PP_MMU,
- INT_MALI_PP2, INT_MALI_PP2_MMU)
-};
-#else
-static struct resource meson_mali_resources[] =
-{
- MALI_GPU_RESOURCES_MALI400_MP4(0xd0060000,
- INT_MALI_GP, INT_MALI_GP_MMU,
- INT_MALI_PP, INT_MALI_PP_MMU,
- INT_MALI_PP2, INT_MALI_PP2_MMU,
- INT_MALI_PP3, INT_MALI_PP3_MMU,
- INT_MALI_PP4, INT_MALI_PP4_MMU
- )
-};
-#endif
-
-#elif MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
-
-#undef INT_MALI_GP
-#undef INT_MALI_GP_MMU
-#undef INT_MALI_PP
-#undef INT_MALI_PP2
-#undef INT_MALI_PP_MMU
-#undef INT_MALI_PP2_MMU
-
-#define INT_MALI_GP (48+32)
-#define INT_MALI_GP_MMU (49+32)
-#define INT_MALI_PP (50+32)
-#define INT_MALI_PP_MMU (51+32)
-#define INT_MALI_PP2_MMU ( 6+32)
-
-static struct resource meson_mali_resources[] =
-{
- MALI_GPU_RESOURCES_MALI400_MP2(0xd0060000,
- INT_MALI_GP, INT_MALI_GP_MMU,
- INT_MALI_PP, INT_MALI_PP2_MMU,
- INT_MALI_PP_MMU, INT_MALI_PP2_MMU)
-};
-
-#else /* MESON_CPU_TYPE == MESON_CPU_TYPE_MESON3 */
-
-#undef INT_MALI_GP
-#undef INT_MALI_GP_MMU
-#undef INT_MALI_PP
-#undef INT_MALI_PP_MMU
-
-#define INT_MALI_GP 48
-#define INT_MALI_GP_MMU 49
-#define INT_MALI_PP 50
-#define INT_MALI_PP_MMU 51
-
-static struct resource meson_mali_resources[] =
-{
- MALI_GPU_RESOURCES_MALI400_MP1(0xd0060000,
- INT_MALI_GP, INT_MALI_GP_MMU, INT_MALI_PP, INT_MALI_PP_MMU)
-};
-#endif /* MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6TV */
-
-void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data)
-{
-
-}
-
-mali_plat_info_t mali_plat_data = {
-
-};
-
-int mali_meson_init_start(struct platform_device* ptr_plt_dev)
-{
- /* for mali platform data. */
- struct mali_gpu_device_data* pdev = ptr_plt_dev->dev.platform_data;
-
- pdev->control_interval = 1000;
- pdev->utilization_callback = mali_gpu_utilization_callback;
-
- /* for resource data. */
- ptr_plt_dev->num_resources = ARRAY_SIZE(meson_mali_resources);
- ptr_plt_dev->resource = meson_mali_resources;
- return 0;
-}
-
-int mali_meson_init_finish(struct platform_device* ptr_plt_dev)
-{
- mali_platform_init();
- return 0;
-}
-
-int mali_meson_uninit(struct platform_device* ptr_plt_dev)
-{
- mali_platform_deinit();
- return 0;
-}
-
-int mali_light_suspend(struct device *device)
-{
- int ret = 0;
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_suspend(device);
- }
-
- mali_platform_power_mode_change(MALI_POWER_MODE_LIGHT_SLEEP);
- return ret;
-}
-
-int mali_light_resume(struct device *device)
-{
- int ret = 0;
-
- mali_platform_power_mode_change(MALI_POWER_MODE_ON);
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_resume(device);
- }
- return ret;
-}
-
-int mali_deep_suspend(struct device *device)
-{
- int ret = 0;
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->suspend(device);
- }
-
- mali_platform_power_mode_change(MALI_POWER_MODE_DEEP_SLEEP);
- return ret;
-}
-
-int mali_deep_resume(struct device *device)
-{
- int ret = 0;
-
- mali_platform_power_mode_change(MALI_POWER_MODE_ON);
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->resume(device);
- }
- return ret;
-
-}
-
-void mali_core_scaling_term(void)
-{
-
-}
-
-int get_gpu_max_clk_level(void)
-{
- return 0;
-}
-
-void mali_post_init(void)
-{
-}
-#endif /* MESON_CPU_TYPE <= MESON_CPU_TYPE_MESON6 */
+++ /dev/null
-/*
- * platform.c
- *
- * clock source setting and resource config
- *
- * Created on: Dec 4, 2013
- * Author: amlogic
- */
-
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/module.h> /* kernel module definitions */
-#include <linux/ioport.h> /* request_mem_region */
-#include <linux/slab.h>
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#include <asm/io.h>
-#include <linux/mali/mali_utgard.h>
-
-#include <common/mali_kernel_common.h>
-#include <common/mali_osk_profiling.h>
-#include <common/mali_pmu.h>
-
-#include "meson_main.h"
-
-/*
- * For Meson 8TVD.
- *
- */
-
-#define CFG_PP 2
-#define CFG_CLOCK 3
-#define CFG_MIN_PP 1
-#define CFG_MIN_CLOCK 0
-
-/* fclk is 2Ghz. */
-#define FCLK_DEV5 (7 << 9) /* 400 Mhz */
-#define FCLK_DEV3 (6 << 9) /* 666 Mhz */
-#define FCLK_DEV2 (5 << 9) /* 1000 Mhz */
-#define FCLK_DEV7 (4 << 9) /* 285 Mhz */
-
-u32 mali_dvfs_clk[] = {
- FCLK_DEV7 | 9, /* 100 Mhz */
- FCLK_DEV2 | 4, /* 200 Mhz */
- FCLK_DEV3 | 1, /* 333 Mhz */
- FCLK_DEV5 | 0, /* 400 Mhz */
-};
-
-u32 mali_dvfs_clk_sample[] = {
- 100, /* 182.1 Mhz */
- 200, /* 318.7 Mhz */
- 333, /* 425 Mhz */
- 400, /* 510 Mhz */
-};
-
-static mali_plat_info_t mali_plat_data = {
- .cfg_pp = CFG_PP, /* number of pp. */
- .cfg_min_pp = CFG_MIN_PP,
- .def_clock = CFG_CLOCK, /* gpu clock used most of time.*/
- .cfg_clock = CFG_CLOCK, /* max gpu clock. */
- .cfg_min_clock = CFG_MIN_CLOCK,
-
- .clk = mali_dvfs_clk, /* clock source table. */
- .clk_sample = mali_dvfs_clk_sample, /* freqency table for show. */
- .clk_len = sizeof(mali_dvfs_clk) / sizeof(mali_dvfs_clk[0]),
- .have_switch = 0,
-};
-
-#define MALI_USER_PP0 AM_IRQ4(31)
-
-static struct resource mali_gpu_resources[] =
-{
-MALI_GPU_RESOURCES_MALI450_MP2_PMU(0xC9140000, INT_MALI_GP, INT_MALI_GP_MMU,
- MALI_USER_PP0, INT_MALI_PP_MMU,
- INT_MALI_PP1, INT_MALI_PP_MMU1,
- INT_MALI_PP)
-};
-
-int mali_meson_init_start(struct platform_device* ptr_plt_dev)
-{
- ptr_plt_dev->num_resources = ARRAY_SIZE(mali_gpu_resources);
- ptr_plt_dev->resource = mali_gpu_resources;
- return mali_clock_init(&mali_plat_data);
-}
-
-int mali_meson_init_finish(struct platform_device* ptr_plt_dev)
-{
- return 0;
-}
-
-int mali_meson_uninit(struct platform_device* ptr_plt_dev)
-{
- return 0;
-}
-
-static int mali_cri_pmu_on_off(size_t param)
-{
- struct mali_pmu_core *pmu;
-
- MALI_DEBUG_PRINT(4, ("mali_os_suspend() called\n"));
- pmu = mali_pmu_get_global_pmu_core();
- if (param == 0)
- mali_pmu_power_down_all(pmu);
- else
- mali_pmu_power_up_all(pmu);
- return 0;
-}
-
-int mali_light_suspend(struct device *device)
-{
- int ret = 0;
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- 0, 0, 0, 0, 0);
-#endif
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_suspend(device);
- }
-
- /* clock scaling. Kasin..*/
- mali_clock_critical(mali_cri_pmu_on_off, 0);
- disable_clock();
- return ret;
-}
-
-int mali_light_resume(struct device *device)
-{
- int ret = 0;
- /* clock scaling. Kasin..*/
- enable_clock();
-
- mali_clock_critical(mali_cri_pmu_on_off, 1);
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- 0, 0, 0, 0, 0);
-#endif
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_resume(device);
- }
- return ret;
-}
-
-int mali_deep_suspend(struct device *device)
-{
- int ret = 0;
- //enable_clock();
- //flush_scaling_job();
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->suspend(device);
- }
-
- /* clock scaling off. Kasin... */
- mali_clock_critical(mali_cri_pmu_on_off, 0);
- disable_clock();
- return ret;
-}
-
-int mali_deep_resume(struct device *device)
-{
- int ret = 0;
- /* clock scaling up. Kasin.. */
- enable_clock();
- mali_clock_critical(mali_cri_pmu_on_off, 1);
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->resume(device);
- }
- return ret;
-
-}
-
-void mali_post_init(void)
-{
-}
+++ /dev/null
-/*
- * platform.c
- *
- * clock source setting and resource config
- *
- * Created on: Dec 4, 2013
- * Author: amlogic
- */
-
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/module.h> /* kernel module definitions */
-#include <linux/ioport.h> /* request_mem_region */
-#include <linux/slab.h>
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#endif
-#include <asm/io.h>
-#include <linux/mali/mali_utgard.h>
-#ifdef CONFIG_GPU_THERMAL
-#include <linux/gpu_cooling.h>
-#include <linux/gpucore_cooling.h>
-#endif
-#include <common/mali_kernel_common.h>
-#include <common/mali_osk_profiling.h>
-#include <common/mali_pmu.h>
-
-#include "meson_main.h"
-
-/*
- * For Meson 8 M2.
- *
- */
-
-#define CFG_PP 6
-#define CFG_CLOCK 3
-#define CFG_MIN_PP 1
-#define CFG_MIN_CLOCK 0
-
-/* fclk is 2550Mhz. */
-#define FCLK_DEV3 (6 << 9) /* 850 Mhz */
-#define FCLK_DEV4 (5 << 9) /* 637.5 Mhz */
-#define FCLK_DEV5 (7 << 9) /* 510 Mhz */
-#define FCLK_DEV7 (4 << 9) /* 364.3 Mhz */
-
-static u32 mali_dvfs_clk[] = {
- FCLK_DEV7 | 1, /* 182.1 Mhz */
- FCLK_DEV4 | 1, /* 318.7 Mhz */
- FCLK_DEV3 | 1, /* 425 Mhz */
- FCLK_DEV5 | 0, /* 510 Mhz */
- FCLK_DEV4 | 0, /* 637.5 Mhz */
-};
-
-static u32 mali_dvfs_clk_sample[] = {
- 182, /* 182.1 Mhz */
- 319, /* 318.7 Mhz */
- 425, /* 425 Mhz */
- 510, /* 510 Mhz */
- 637, /* 637.5 Mhz */
-};
-//////////////////////////////////////
-//for dvfs
-struct mali_gpu_clk_item meson_gpu_clk[] = {
- {182, 1150}, /* 182.1 Mhz, 1150mV */
- {319, 1150}, /* 318.7 Mhz */
- {425, 1150}, /* 425 Mhz */
- {510, 1150}, /* 510 Mhz */
- {637, 1150}, /* 637.5 Mhz */
-};
-struct mali_gpu_clock meson_gpu_clk_info = {
- .item = meson_gpu_clk,
- .num_of_steps = ARRAY_SIZE(meson_gpu_clk),
-};
-static int cur_gpu_clk_index = 0;
-//////////////////////////////////////
-static mali_dvfs_threshold_table mali_dvfs_table[]={
- { 0, 0, 3, 30, 80}, /* for 182.1 */
- { 1, 1, 3, 40, 205}, /* for 318.7 */
- { 2, 2, 3, 150, 215}, /* for 425.0 */
- { 3, 3, 3, 170, 253}, /* for 510.0 */
- { 4, 4, 3, 230, 255}, /* for 637.5 */
- { 0, 0, 3, 0, 0}
-};
-
-static void mali_plat_preheat(void);
-static mali_plat_info_t mali_plat_data = {
- .cfg_pp = CFG_PP, /* number of pp. */
- .cfg_min_pp = CFG_MIN_PP,
- .turbo_clock = 4, /* reserved clock src. */
- .def_clock = 2, /* gpu clock used most of time.*/
- .cfg_clock = CFG_CLOCK, /* max gpu clock. */
- .cfg_clock_bkup = CFG_CLOCK,
- .cfg_min_clock = CFG_MIN_CLOCK,
-
- .sc_mpp = 3, /* number of pp used most of time.*/
- .bst_gpu = 210, /* threshold for boosting gpu. */
- .bst_pp = 160, /* threshold for boosting PP. */
-
- .clk = mali_dvfs_clk, /* clock source table. */
- .clk_sample = mali_dvfs_clk_sample, /* freqency table for show. */
- .clk_len = sizeof(mali_dvfs_clk) / sizeof(mali_dvfs_clk[0]),
- .have_switch = 1,
-
- .dvfs_table = mali_dvfs_table, /* DVFS table. */
- .dvfs_table_size = sizeof(mali_dvfs_table) / sizeof(mali_dvfs_threshold_table),
-
- .scale_info = {
- CFG_MIN_PP, /* minpp */
- CFG_PP, /* maxpp, should be same as cfg_pp */
- CFG_MIN_CLOCK, /* minclk */
- CFG_CLOCK, /* maxclk should be same as cfg_clock */
- },
-
- .limit_on = 1,
- .plat_preheat = mali_plat_preheat,
-};
-
-static void mali_plat_preheat(void)
-{
-#ifndef CONFIG_MALI_DVFS
- u32 pre_fs;
- u32 clk, pp;
-
- if (get_mali_schel_mode() != MALI_PP_FS_SCALING)
- return;
-
- get_mali_rt_clkpp(&clk, &pp);
- pre_fs = mali_plat_data.def_clock + 1;
- if (clk < pre_fs)
- clk = pre_fs;
- if (pp < mali_plat_data.sc_mpp)
- pp = mali_plat_data.sc_mpp;
- set_mali_rt_clkpp(clk, pp, 1);
-#endif
-}
-
-mali_plat_info_t* get_mali_plat_data(void) {
- return &mali_plat_data;
-}
-
-int get_mali_freq_level(int freq)
-{
- int i = 0, level = -1;
- int mali_freq_num;
-
- if (freq < 0)
- return level;
-
- mali_freq_num = mali_plat_data.dvfs_table_size - 1;
- if (freq <= mali_plat_data.clk_sample[0])
- level = mali_freq_num-1;
- if (freq >= mali_plat_data.clk_sample[mali_freq_num - 1])
- level = 0;
- for (i=0; i<mali_freq_num - 1 ;i++) {
- if (freq >= mali_plat_data.clk_sample[i] && freq <= mali_plat_data.clk_sample[i + 1]) {
- level = i;
- level = mali_freq_num-level - 1;
- }
- }
- return level;
-}
-
-unsigned int get_mali_max_level(void)
-{
- return mali_plat_data.dvfs_table_size - 1;
-}
-
-#if 0
-static struct resource mali_gpu_resources[] =
-{
- MALI_GPU_RESOURCES_MALI450_MP6_PMU(IO_MALI_APB_PHY_BASE, INT_MALI_GP, INT_MALI_GP_MMU,
- INT_MALI_PP0, INT_MALI_PP0_MMU,
- INT_MALI_PP1, INT_MALI_PP1_MMU,
- INT_MALI_PP2, INT_MALI_PP2_MMU,
- INT_MALI_PP4, INT_MALI_PP4_MMU,
- INT_MALI_PP5, INT_MALI_PP5_MMU,
- INT_MALI_PP6, INT_MALI_PP6_MMU,
- INT_MALI_PP)
-};
-#else
-static struct resource mali_gpu_resources[] =
-{
- { .name = "Mali_L2", .flags = 0x00000200, .start = 0xd00c0000 + 0x10000, .end = 0xd00c0000 + 0x10000 + 0x200, },
- { .name = "Mali_GP", .flags = 0x00000200, .start = 0xd00c0000 + 0x00000, .end = 0xd00c0000 + 0x00000 + 0x100, },
- { .name = "Mali_GP_IRQ", .flags = 0x00000400, .start = (160 + 32), .end = (160 + 32), },
- { .name = "Mali_GP_MMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x03000, .end = 0xd00c0000 + 0x03000 + 0x100, },
- { .name = "Mali_GP_MMU_IRQ", .flags = 0x00000400, .start = (161 + 32), .end = (161 + 32), },
- { .name = "Mali_L2", .flags = 0x00000200, .start = 0xd00c0000 + 0x01000, .end = 0xd00c0000 + 0x01000 + 0x200, },
- { .name = "Mali_PP" "0", .flags = 0x00000200, .start = 0xd00c0000 + 0x08000, .end = 0xd00c0000 + 0x08000 + 0x1100, },
- { .name = "Mali_PP" "0" "_IRQ", .flags = 0x00000400, .start = (164 + 32), .end = (164 + 32), },
- { .name = "Mali_PP" "0" "_MMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x04000, .end = 0xd00c0000 + 0x04000 + 0x100, },
- { .name = "Mali_PP" "0" "_MMU_IRQ", .flags = 0x00000400, .start = (165 + 32), .end = (165 + 32), },
- { .name = "Mali_PP" "1", .flags = 0x00000200, .start = 0xd00c0000 + 0x0A000, .end = 0xd00c0000 + 0x0A000 + 0x1100, },
- { .name = "Mali_PP" "1" "_IRQ", .flags = 0x00000400, .start = (166 + 32), .end = (166 + 32), },
- { .name = "Mali_PP" "1" "_MMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x05000, .end = 0xd00c0000 + 0x05000 + 0x100, },
- { .name = "Mali_PP" "1" "_MMU_IRQ", .flags = 0x00000400, .start = (167 + 32), .end = (167 + 32), },
- { .name = "Mali_PP" "2", .flags = 0x00000200, .start = 0xd00c0000 + 0x0C000, .end = 0xd00c0000 + 0x0C000 + 0x1100, },
- { .name = "Mali_PP" "2" "_IRQ", .flags = 0x00000400, .start = (168 + 32), .end = (168 + 32), },
- { .name = "Mali_PP" "2" "_MMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x06000, .end = 0xd00c0000 + 0x06000 + 0x100, },
- { .name = "Mali_PP" "2" "_MMU_IRQ", .flags = 0x00000400, .start = (169 + 32), .end = (169 + 32), },
- { .name = "Mali_L2", .flags = 0x00000200, .start = 0xd00c0000 + 0x11000, .end = 0xd00c0000 + 0x11000 + 0x200, },
- { .name = "Mali_PP" "3", .flags = 0x00000200, .start = 0xd00c0000 + 0x28000, .end = 0xd00c0000 + 0x28000 + 0x1100, },
- { .name = "Mali_PP" "3" "_IRQ", .flags = 0x00000400, .start = (172 + 32), .end = (172 + 32), },
- { .name = "Mali_PP" "3" "_MMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x1C000, .end = 0xd00c0000 + 0x1C000 + 0x100, },
- { .name = "Mali_PP" "3" "_MMU_IRQ", .flags = 0x00000400, .start = (173 + 32), .end = (173 + 32), },
- { .name = "Mali_PP" "4", .flags = 0x00000200, .start = 0xd00c0000 + 0x2A000, .end = 0xd00c0000 + 0x2A000 + 0x1100, },
- { .name = "Mali_PP" "4" "_IRQ", .flags = 0x00000400, .start = (174 + 32), .end = (174 + 32), },
- { .name = "Mali_PP" "4" "_MMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x1D000, .end = 0xd00c0000 + 0x1D000 + 0x100, },
- { .name = "Mali_PP" "4" "_MMU_IRQ", .flags = 0x00000400, .start = (175 + 32), .end = (175 + 32), },
- { .name = "Mali_PP" "5", .flags = 0x00000200, .start = 0xd00c0000 + 0x2C000, .end = 0xd00c0000 + 0x2C000 + 0x1100, },
- { .name = "Mali_PP" "5" "_IRQ", .flags = 0x00000400, .start = (176 + 32), .end = (176 + 32), },
- { .name = "Mali_PP" "5" "_MMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x1E000, .end = 0xd00c0000 + 0x1E000 + 0x100, },
- { .name = "Mali_PP" "5" "_MMU_IRQ", .flags = 0x00000400, .start = (177 + 32), .end = (177 + 32), },
- { .name = "Mali_Broadcast", .flags = 0x00000200, .start = 0xd00c0000 + 0x13000, .end = 0xd00c0000 + 0x13000 + 0x100, },
- { .name = "Mali_DLBU", .flags = 0x00000200, .start = 0xd00c0000 + 0x14000, .end = 0xd00c0000 + 0x14000 + 0x100, },
- { .name = "Mali_PP_Broadcast", .flags = 0x00000200, .start = 0xd00c0000 + 0x16000, .end = 0xd00c0000 + 0x16000 + 0x1100, },
- { .name = "Mali_PP_Broadcast_IRQ", .flags = 0x00000400, .start = (162 + 32), .end = (162 + 32), },
- { .name = "Mali_PP_MMU_Broadcast", .flags = 0x00000200, .start = 0xd00c0000 + 0x15000, .end = 0xd00c0000 + 0x15000 + 0x100, },
- { .name = "Mali_DMA", .flags = 0x00000200, .start = 0xd00c0000 + 0x12000, .end = 0xd00c0000 + 0x12000 + 0x100, },
- { .name = "Mali_PMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x02000, .end = 0xd00c0000 + 0x02000 + 0x100, },
-};
-#endif
-#ifdef CONFIG_GPU_THERMAL
-static void set_limit_mali_freq(u32 idx)
-{
- if (mali_plat_data.limit_on == 0)
- return;
- if (idx > mali_plat_data.turbo_clock || idx < mali_plat_data.scale_info.minclk)
- return;
- mali_plat_data.scale_info.maxclk= idx;
- revise_mali_rt();
-}
-
-static u32 get_limit_mali_freq(void)
-{
- return mali_plat_data.scale_info.maxclk;
-}
-#endif
-
-#ifdef CONFIG_GPU_THERMAL
-static u32 set_limit_pp_num(u32 num)
-{
- u32 ret = -1;
- if (mali_plat_data.limit_on == 0)
- goto quit;
- if (num > mali_plat_data.cfg_pp ||
- num < mali_plat_data.scale_info.minpp)
- goto quit;
- mali_plat_data.scale_info.maxpp = num;
- revise_mali_rt();
- ret = 0;
-quit:
- return ret;
-}
-#endif
-
-void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data);
-
-#if 0
-struct mali_gpu_clk_item {
- unsigned int clock; /* unit(MHz) */
- unsigned int vol;
-};
-
-struct mali_gpu_clock {
- struct mali_gpu_clk_item *item;
- unsigned int num_of_steps;
-};
-#endif
-
-/* Function that platfrom report it's clock info which driver can set, needed when CONFIG_MALI_DVFS enabled */
-void meson_platform_get_clock_info(struct mali_gpu_clock **data) {
- *data = &meson_gpu_clk_info;
-}
-
-/* Function that get the current clock info, needed when CONFIG_MALI_DVFS enabled */
-int meson_platform_get_freq(void) {
- printk("get cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
- return cur_gpu_clk_index;
-}
-
-/* Fuction that platform callback for freq setting, needed when CONFIG_MALI_DVFS enabled */
-int meson_platform_set_freq(int setting_clock_step) {
-
- if (cur_gpu_clk_index == setting_clock_step) {
- return 0;
- }
-
- mali_clock_set(setting_clock_step);
-
- cur_gpu_clk_index = setting_clock_step;
- printk("set cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
-
- return 0;
-}
-
-int mali_meson_init_start(struct platform_device* ptr_plt_dev)
-{
- struct mali_gpu_device_data* pdev = ptr_plt_dev->dev.platform_data;
-
- /* chip mark detect. */
-#ifdef IS_MESON_M8_CPU
- if (IS_MESON_M8_CPU) {
- mali_plat_data.have_switch = 0;
- }
-#endif
-
- /* for resource data. */
- ptr_plt_dev->num_resources = ARRAY_SIZE(mali_gpu_resources);
- ptr_plt_dev->resource = mali_gpu_resources;
-
- /*for dvfs*/
-#ifndef CONFIG_MALI_DVFS
- /* for mali platform data. */
- pdev->control_interval = 300;
- pdev->utilization_callback = mali_gpu_utilization_callback;
-#else
- pdev->get_clock_info = meson_platform_get_clock_info;
- pdev->get_freq = meson_platform_get_freq;
- pdev->set_freq = meson_platform_set_freq;
-#endif
-
- return mali_clock_init(&mali_plat_data);
-}
-
-int mali_meson_init_finish(struct platform_device* ptr_plt_dev)
-{
-#ifndef CONFIG_MALI_DVFS
- if (mali_core_scaling_init(&mali_plat_data) < 0)
- return -1;
-#else
- printk("disable meson own dvfs\n");
-#endif
- return 0;
-}
-
-int mali_meson_uninit(struct platform_device* ptr_plt_dev)
-{
- return 0;
-}
-
-static int mali_cri_light_suspend(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- mali_pm_statue = 1;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_suspend(device);
- }
- mali_pmu_power_down_all(pmu);
- return ret;
-}
-
-static int mali_cri_light_resume(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- mali_pmu_power_up_all(pmu);
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_resume(device);
- }
- mali_pm_statue = 0;
- return ret;
-}
-
-static int mali_cri_deep_suspend(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->suspend(device);
- }
- mali_pmu_power_down_all(pmu);
- return ret;
-}
-
-static int mali_cri_deep_resume(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- mali_pmu_power_up_all(pmu);
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->resume(device);
- }
- return ret;
-
-}
-
-int mali_light_suspend(struct device *device)
-{
- int ret = 0;
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- 0, 0, 0, 0, 0);
-#endif
-
- /* clock scaling. Kasin..*/
- ret = mali_clock_critical(mali_cri_light_suspend, (size_t)device);
- disable_clock();
- return ret;
-}
-
-int mali_light_resume(struct device *device)
-{
- int ret = 0;
- enable_clock();
- ret = mali_clock_critical(mali_cri_light_resume, (size_t)device);
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- get_current_frequency(), 0, 0, 0, 0);
-#endif
- return ret;
-}
-
-int mali_deep_suspend(struct device *device)
-{
- int ret = 0;
-
- mali_pm_statue = 1;
- enable_clock();
-#ifndef CONFIG_MALI_DVFS
- flush_scaling_job();
-#endif
-
- /* clock scaling off. Kasin... */
- ret = mali_clock_critical(mali_cri_deep_suspend, (size_t)device);
- disable_clock();
- return ret;
-}
-
-int mali_deep_resume(struct device *device)
-{
- int ret = 0;
-
- /* clock scaling up. Kasin.. */
- enable_clock();
- ret = mali_clock_critical(mali_cri_deep_resume, (size_t)device);
- mali_pm_statue = 0;
- return ret;
-
-}
-
-void mali_post_init(void)
-{
-#ifdef CONFIG_GPU_THERMAL
- int err;
- struct gpufreq_cooling_device *gcdev = NULL;
- struct gpucore_cooling_device *gccdev = NULL;
-
- gcdev = gpufreq_cooling_alloc();
- register_gpu_freq_info(get_current_frequency);
- if (IS_ERR(gcdev))
- printk("malloc gpu cooling buffer error!!\n");
- else if (!gcdev)
- printk("system does not enable thermal driver\n");
- else {
- gcdev->get_gpu_freq_level = get_mali_freq_level;
- gcdev->get_gpu_max_level = get_mali_max_level;
- gcdev->set_gpu_freq_idx = set_limit_mali_freq;
- gcdev->get_gpu_current_max_level = get_limit_mali_freq;
- err = gpufreq_cooling_register(gcdev);
- if (err < 0)
- printk("register GPU cooling error\n");
- printk("gpu cooling register okay with err=%d\n",err);
- }
-
- gccdev = gpucore_cooling_alloc();
- if (IS_ERR(gccdev))
- printk("malloc gpu core cooling buffer error!!\n");
- else if (!gccdev)
- printk("system does not enable thermal driver\n");
- else {
- gccdev->max_gpu_core_num=mali_plat_data.cfg_pp;
- gccdev->set_max_pp_num=set_limit_pp_num;
- err = (int)gpucore_cooling_register(gccdev);
- if (err < 0)
- printk("register GPU cooling error\n");
- printk("gpu core cooling register okay with err=%d\n",err);
- }
-#endif
-}
+++ /dev/null
-/*
- * platform.c
- *
- * clock source setting and resource config
- *
- * Created on: Dec 4, 2013
- * Author: amlogic
- */
-
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/module.h> /* kernel module definitions */
-#include <linux/ioport.h> /* request_mem_region */
-#include <linux/slab.h>
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#include <asm/io.h>
-#include <linux/mali/mali_utgard.h>
-#include <linux/gpu_cooling.h>
-#include <linux/gpucore_cooling.h>
-#include <common/mali_kernel_common.h>
-#include <common/mali_osk_profiling.h>
-#include <common/mali_pmu.h>
-
-#include "meson_main.h"
-
-/*
- * For Meson 8B.
- *
- */
-
-#define CFG_PP 2
-#define CFG_CLOCK 3
-#define CFG_MIN_PP 1
-#define CFG_MIN_CLOCK 0
-
-/* fclk is 2550Mhz. */
-#define FCLK_DEV3 (6 << 9) /* 850 Mhz */
-#define FCLK_DEV4 (5 << 9) /* 637.5 Mhz */
-#define FCLK_DEV5 (7 << 9) /* 510 Mhz */
-#define FCLK_DEV7 (4 << 9) /* 364.3 Mhz */
-
-static u32 mali_dvfs_clk[] = {
- FCLK_DEV5 | 1, /* 255 Mhz */
- FCLK_DEV7 | 0, /* 364 Mhz */
- FCLK_DEV3 | 1, /* 425 Mhz */
- FCLK_DEV5 | 0, /* 510 Mhz */
- FCLK_DEV4 | 0, /* 637.5 Mhz */
-};
-
-static u32 mali_dvfs_clk_sample[] = {
- 255, /* 182.1 Mhz */
- 364, /* 318.7 Mhz */
- 425, /* 425 Mhz */
- 510, /* 510 Mhz */
- 637, /* 637.5 Mhz */
-};
-
-//////////////////////////////////////
-//for dvfs
-struct mali_gpu_clk_item meson_gpu_clk[] = {
- {255, 1150}, /* 182.1 Mhz, 1150mV */
- {364, 1150}, /* 318.7 Mhz */
- {425, 1150}, /* 425 Mhz */
- {510, 1150}, /* 510 Mhz */
- {637, 1150}, /* 637.5 Mhz */
-};
-struct mali_gpu_clock meson_gpu_clk_info = {
- .item = meson_gpu_clk,
- .num_of_steps = ARRAY_SIZE(meson_gpu_clk),
-};
-static int cur_gpu_clk_index = 0;
-//////////////////////////////////////
-
-static mali_dvfs_threshold_table mali_dvfs_table[]={
- { 0, 0, 5, 30 , 180}, /* for 255 */
- { 1, 1, 5, 152, 205}, /* for 364 */
- { 2, 2, 5, 180, 212}, /* for 425 */
- { 3, 3, 5, 205, 236}, /* for 510 */
- { 4, 4, 5, 230, 255}, /* for 637 */
- { 0, 0, 5, 0, 0}
-};
-
-static void mali_plat_preheat(void);
-static mali_plat_info_t mali_plat_data = {
- .cfg_pp = CFG_PP, /* number of pp. */
- .cfg_min_pp = CFG_MIN_PP,
- .turbo_clock = 4, /* reserved clock src. */
- .def_clock = 2, /* gpu clock used most of time.*/
- .cfg_clock = CFG_CLOCK, /* max gpu clock. */
- .cfg_clock_bkup = CFG_CLOCK,
- .cfg_min_clock = CFG_MIN_CLOCK,
-
- .sc_mpp = 2, /* number of pp used most of time.*/
- .bst_gpu = 210, /* threshold for boosting gpu. */
- .bst_pp = 160, /* threshold for boosting PP. */
-
- .clk = mali_dvfs_clk, /* clock source table. */
- .clk_sample = mali_dvfs_clk_sample, /* freqency table for show. */
- .clk_len = sizeof(mali_dvfs_clk) / sizeof(mali_dvfs_clk[0]),
- .have_switch = 1,
-
- .dvfs_table = mali_dvfs_table, /* DVFS table. */
- .dvfs_table_size = sizeof(mali_dvfs_table) / sizeof(mali_dvfs_threshold_table),
-
- .scale_info = {
- CFG_MIN_PP, /* minpp */
- CFG_PP, /* maxpp, should be same as cfg_pp */
- CFG_MIN_CLOCK, /* minclk */
- CFG_CLOCK, /* maxclk should be same as cfg_clock */
- },
-
- .limit_on = 1,
- .plat_preheat = mali_plat_preheat,
-};
-
-static void mali_plat_preheat(void)
-{
-#ifndef CONFIG_MALI_DVFS
- u32 pre_fs;
- u32 clk, pp;
-
- if (get_mali_schel_mode() != MALI_PP_FS_SCALING)
- return;
-
- get_mali_rt_clkpp(&clk, &pp);
- pre_fs = mali_plat_data.def_clock + 1;
- if (clk < pre_fs)
- clk = pre_fs;
- if (pp < mali_plat_data.sc_mpp)
- pp = mali_plat_data.sc_mpp;
- set_mali_rt_clkpp(clk, pp, 1);
-#endif
-}
-
-mali_plat_info_t* get_mali_plat_data(void) {
- return &mali_plat_data;
-}
-
-int get_mali_freq_level(int freq)
-{
- int i = 0, level = -1;
- int mali_freq_num;
-
- if (freq < 0)
- return level;
- mali_freq_num = mali_plat_data.dvfs_table_size - 1;
- if (freq <= mali_plat_data.clk_sample[0])
- level = mali_freq_num-1;
- if (freq >= mali_plat_data.clk_sample[mali_freq_num - 1])
- level = 0;
- for (i=0; i<mali_freq_num - 1 ;i++) {
- if (freq >= mali_plat_data.clk_sample[i] && freq <= mali_plat_data.clk_sample[i + 1]) {
- level = i;
- level = mali_freq_num-level - 1;
- }
- }
- return level;
-}
-
-unsigned int get_mali_max_level(void)
-{
- return mali_plat_data.dvfs_table_size - 1;
-}
-
-static struct resource mali_gpu_resources[] =
-{
- MALI_GPU_RESOURCES_MALI450_MP2_PMU(IO_MALI_APB_PHY_BASE, INT_MALI_GP, INT_MALI_GP_MMU,
- INT_MALI_PP0, INT_MALI_PP0_MMU,
- INT_MALI_PP1, INT_MALI_PP1_MMU,
- INT_MALI_PP)
-};
-
-static void set_limit_mali_freq(u32 idx)
-{
- if (mali_plat_data.limit_on == 0)
- return;
- if (idx > mali_plat_data.turbo_clock || idx < mali_plat_data.scale_info.minclk)
- return;
- mali_plat_data.scale_info.maxclk= idx;
-
- revise_mali_rt();
-}
-
-static u32 get_limit_mali_freq(void)
-{
- return mali_plat_data.scale_info.maxclk;
-}
-
-static u32 set_limit_pp_num(u32 num)
-{
- u32 ret = -1;
- if (mali_plat_data.limit_on == 0)
- goto quit;
- if (num > mali_plat_data.cfg_pp ||
- num < mali_plat_data.scale_info.minpp)
- goto quit;
- mali_plat_data.scale_info.maxpp = num;
- revise_mali_rt();
- ret = 0;
-quit:
- return ret;
-}
-
-void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data);
-
-#if 0
-struct mali_gpu_clk_item {
- unsigned int clock; /* unit(MHz) */
- unsigned int vol;
-};
-
-struct mali_gpu_clock {
- struct mali_gpu_clk_item *item;
- unsigned int num_of_steps;
-};
-#endif
-
-/* Function that platfrom report it's clock info which driver can set, needed when CONFIG_MALI_DVFS enabled */
-void meson_platform_get_clock_info(struct mali_gpu_clock **data) {
- *data = &meson_gpu_clk_info;
-}
-
-/* Function that get the current clock info, needed when CONFIG_MALI_DVFS enabled */
-int meson_platform_get_freq(void) {
- printk("get cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
- return cur_gpu_clk_index;
-}
-
-/* Fuction that platform callback for freq setting, needed when CONFIG_MALI_DVFS enabled */
-int meson_platform_set_freq(int setting_clock_step) {
-
- if (cur_gpu_clk_index == setting_clock_step) {
- return 0;
- }
-
- mali_clock_set(setting_clock_step);
-
- cur_gpu_clk_index = setting_clock_step;
- printk("set cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
-
- return 0;
-}
-int mali_meson_init_start(struct platform_device* ptr_plt_dev)
-{
- struct mali_gpu_device_data* pdev = ptr_plt_dev->dev.platform_data;
-
-
- /* for resource data. */
- ptr_plt_dev->num_resources = ARRAY_SIZE(mali_gpu_resources);
- ptr_plt_dev->resource = mali_gpu_resources;
-
- /*for dvfs*/
-#ifndef CONFIG_MALI_DVFS
- /* for mali platform data. */
- pdev->control_interval = 200;
- pdev->utilization_callback = mali_gpu_utilization_callback;
-#else
- pdev->get_clock_info = meson_platform_get_clock_info;
- pdev->get_freq = meson_platform_get_freq;
- pdev->set_freq = meson_platform_set_freq;
-#endif
-
- return mali_clock_init(&mali_plat_data);
-}
-
-int mali_meson_init_finish(struct platform_device* ptr_plt_dev)
-{
-#ifndef CONFIG_MALI_DVFS
- if (mali_core_scaling_init(&mali_plat_data) < 0)
- return -1;
-#endif
- return 0;
-}
-
-int mali_meson_uninit(struct platform_device* ptr_plt_dev)
-{
- return 0;
-}
-
-static int mali_cri_light_suspend(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- mali_pm_statue = 1;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_suspend(device);
- }
- mali_pmu_power_down_all(pmu);
- return ret;
-}
-
-static int mali_cri_light_resume(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- mali_pmu_power_up_all(pmu);
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_resume(device);
- }
- mali_pm_statue = 0;
- return ret;
-}
-
-static int mali_cri_deep_suspend(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->suspend(device);
- }
- mali_pmu_power_down_all(pmu);
- return ret;
-}
-
-static int mali_cri_deep_resume(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- mali_pmu_power_up_all(pmu);
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->resume(device);
- }
- return ret;
-
-}
-
-int mali_light_suspend(struct device *device)
-{
- int ret = 0;
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- 0, 0, 0, 0, 0);
-#endif
-
- /* clock scaling. Kasin..*/
- ret = mali_clock_critical(mali_cri_light_suspend, (size_t)device);
- disable_clock();
- return ret;
-}
-
-int mali_light_resume(struct device *device)
-{
- int ret = 0;
- enable_clock();
- ret = mali_clock_critical(mali_cri_light_resume, (size_t)device);
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- get_current_frequency(), 0, 0, 0, 0);
-#endif
- return ret;
-}
-
-int mali_deep_suspend(struct device *device)
-{
- int ret = 0;
- struct mali_pmu_core *pmu;
-
- mali_pm_statue = 1;
- pmu = mali_pmu_get_global_pmu_core();
- enable_clock();
-#ifndef CONFIG_MALI_DVFS
- flush_scaling_job();
-#endif
-
- /* clock scaling off. Kasin... */
- ret = mali_clock_critical(mali_cri_deep_suspend, (size_t)device);
- disable_clock();
- return ret;
-}
-
-int mali_deep_resume(struct device *device)
-{
- int ret = 0;
-
- /* clock scaling up. Kasin.. */
- enable_clock();
- ret = mali_clock_critical(mali_cri_deep_resume, (size_t)device);
- mali_pm_statue = 0;
- return ret;
-}
-
-void mali_post_init(void)
-{
-#ifdef CONFIG_GPU_THERMAL
- int err;
- struct gpufreq_cooling_device *gcdev = NULL;
- struct gpucore_cooling_device *gccdev = NULL;
-
- gcdev = gpufreq_cooling_alloc();
- register_gpu_freq_info(get_current_frequency);
- if (IS_ERR(gcdev))
- printk("malloc gpu cooling buffer error!!\n");
- else if (!gcdev)
- printk("system does not enable thermal driver\n");
- else {
- gcdev->get_gpu_freq_level = get_mali_freq_level;
- gcdev->get_gpu_max_level = get_mali_max_level;
- gcdev->set_gpu_freq_idx = set_limit_mali_freq;
- gcdev->get_gpu_current_max_level = get_limit_mali_freq;
- err = gpufreq_cooling_register(gcdev);
- if (err < 0)
- printk("register GPU cooling error\n");
- printk("gpu cooling register okay with err=%d\n",err);
- }
-
- gccdev = gpucore_cooling_alloc();
- if (IS_ERR(gccdev))
- printk("malloc gpu core cooling buffer error!!\n");
- else if (!gccdev)
- printk("system does not enable thermal driver\n");
- else {
- gccdev->max_gpu_core_num=mali_plat_data.cfg_pp;
- gccdev->set_max_pp_num=set_limit_pp_num;
- err = (int)gpucore_cooling_register(gccdev);
- if (err < 0)
- printk("register GPU cooling error\n");
- printk("gpu core cooling register okay with err=%d\n",err);
- }
-#endif
-}
+++ /dev/null
-/*
- * Copyright (C) 2013 ARM Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
- *
- * A copy of the licence is included with the program, and can also be obtained from Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-/**
- * @file arm_core_scaling.c
- * Example core scaling policy.
- */
-
-#include <linux/version.h>
-#include <linux/module.h>
-#include <linux/workqueue.h>
-#include <linux/mali/mali_utgard.h>
-#include <mali_kernel_common.h>
-#include <mali_osk_profiling.h>
-
-#include <meson_main.h>
-
-#define LOG_MALI_SCALING 0
-
-
-static int currentStep;
-#ifndef CONFIG_MALI_DVFS
-static int num_cores_enabled;
-static int lastStep;
-static struct work_struct wq_work;
-static mali_plat_info_t* pmali_plat = NULL;
-#endif
-static int scaling_mode = MALI_PP_FS_SCALING;
-
-
-static unsigned scaling_dbg_level = 0;
-module_param(scaling_dbg_level, uint, 0644);
-MODULE_PARM_DESC(scaling_dbg_level , "scaling debug level");
-
-#define scalingdbg(level, fmt, arg...) \
- do { \
- if (scaling_dbg_level >= (level)) \
- printk(fmt , ## arg); \
- } while (0)
-
-#ifndef CONFIG_MALI_DVFS
-static void do_scaling(struct work_struct *work)
-{
- mali_dvfs_threshold_table * pdvfs = pmali_plat->dvfs_table;
- int err = mali_perf_set_num_pp_cores(num_cores_enabled);
- scalingdbg(1, "set pp cores to %d\n", num_cores_enabled);
- MALI_DEBUG_ASSERT(0 == err);
- MALI_IGNORE(err);
- if (pdvfs[currentStep].freq_index != pdvfs[lastStep].freq_index) {
- mali_dev_pause();
- mali_clock_set(pdvfs[currentStep].freq_index);
- mali_dev_resume();
- lastStep = currentStep;
- }
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- get_current_frequency(),
- 0, 0, 0, 0);
-#endif
-}
-#endif
-
-u32 revise_set_clk(u32 val, u32 flush)
-{
- u32 ret = 0;
-#ifndef CONFIG_MALI_DVFS
- mali_scale_info_t* pinfo;
-
- pinfo = &pmali_plat->scale_info;
-
- if (val < pinfo->minclk)
- val = pinfo->minclk;
- else if (val > pinfo->maxclk)
- val = pinfo->maxclk;
-
- if (val != currentStep) {
- currentStep = val;
- if (flush)
- schedule_work(&wq_work);
- else
- ret = 1;
- }
-#endif
- return ret;
-}
-
-void get_mali_rt_clkpp(u32* clk, u32* pp)
-{
-#ifndef CONFIG_MALI_DVFS
- *clk = currentStep;
- *pp = num_cores_enabled;
-#endif
-}
-
-u32 set_mali_rt_clkpp(u32 clk, u32 pp, u32 flush)
-{
- u32 ret = 0;
-#ifndef CONFIG_MALI_DVFS
- mali_scale_info_t* pinfo;
- u32 flush_work = 0;
-
- pinfo = &pmali_plat->scale_info;
- if (clk < pinfo->minclk)
- clk = pinfo->minclk;
- else if (clk > pinfo->maxclk)
- clk = pinfo->maxclk;
-
- if (clk != currentStep) {
- currentStep = clk;
- if (flush)
- flush_work++;
- else
- ret = 1;
- }
- if (pp < pinfo->minpp)
- pp = pinfo->minpp;
- else if (pp > pinfo->maxpp)
- pp = pinfo->maxpp;
-
- if (pp != num_cores_enabled) {
- num_cores_enabled = pp;
- if (flush)
- flush_work++;
- else
- ret = 1;
- }
-
- if (flush_work)
- schedule_work(&wq_work);
-#endif
- return ret;
-}
-
-void revise_mali_rt(void)
-{
-#ifndef CONFIG_MALI_DVFS
- set_mali_rt_clkpp(currentStep, num_cores_enabled, 1);
-#endif
-}
-
-void flush_scaling_job(void)
-{
-#ifndef CONFIG_MALI_DVFS
- cancel_work_sync(&wq_work);
-#endif
-}
-
-#ifndef CONFIG_MALI_DVFS
-static u32 enable_one_core(void)
-{
- scalingdbg(2, "meson: one more pp, curent has %d pp cores\n", num_cores_enabled + 1);
- return set_mali_rt_clkpp(currentStep, num_cores_enabled + 1, 0);
-}
-
-static u32 disable_one_core(void)
-{
- scalingdbg(2, "meson: disable one pp, current has %d pp cores\n", num_cores_enabled - 1);
- return set_mali_rt_clkpp(currentStep, num_cores_enabled - 1, 0);
-}
-
-static u32 enable_max_num_cores(void)
-{
- return set_mali_rt_clkpp(currentStep, pmali_plat->scale_info.maxpp, 0);
-}
-
-static u32 enable_pp_cores(u32 val)
-{
- scalingdbg(2, "meson: enable %d pp cores\n", val);
- return set_mali_rt_clkpp(currentStep, val, 0);
-}
-#endif
-
-int mali_core_scaling_init(mali_plat_info_t *mali_plat)
-{
-#ifndef CONFIG_MALI_DVFS
- if (mali_plat == NULL) {
- scalingdbg(2, " Mali platform data is NULL!!!\n");
- return -1;
- }
-
- pmali_plat = mali_plat;
- num_cores_enabled = pmali_plat->sc_mpp;
-
- currentStep = pmali_plat->def_clock;
- lastStep = currentStep;
- INIT_WORK(&wq_work, do_scaling);
-#endif
- return 0;
- /* NOTE: Mali is not fully initialized at this point. */
-}
-
-void mali_core_scaling_term(void)
-{
-#ifndef CONFIG_MALI_DVFS
- flush_scheduled_work();
-#endif
-}
-
-#ifndef CONFIG_MALI_DVFS
-static u32 mali_threshold [] = {
- 102, /* 40% */
- 128, /* 50% */
- 230, /* 90% */
-};
-#endif
-
-void mali_pp_scaling_update(struct mali_gpu_utilization_data *data)
-{
-#ifndef CONFIG_MALI_DVFS
- int ret = 0;
-
- if (mali_threshold[2] < data->utilization_pp)
- ret = enable_max_num_cores();
- else if (mali_threshold[1]< data->utilization_pp)
- ret = enable_one_core();
- else if (0 < data->utilization_pp)
- ret = disable_one_core();
- if (ret == 1)
- schedule_work(&wq_work);
-#endif
-}
-
-#if LOG_MALI_SCALING
-void trace_utilization(struct mali_gpu_utilization_data *data, u32 current_idx, u32 next,
- u32 current_pp, u32 next_pp)
-{
- char direction;
- if (next > current_idx)
- direction = '>';
- else if ((current_idx > pmali_plat->scale_info.minpp) && (next < current_idx))
- direction = '<';
- else
- direction = '~';
-
- scalingdbg(2, "[SCALING]%c (%3d-->%3d)@%3d{%3d - %3d}. pp:(%d-->%d)\n",
- direction,
- get_mali_freq(current_idx),
- get_mali_freq(next),
- data->utilization_gpu,
- pmali_plat->dvfs_table[current_idx].downthreshold,
- pmali_plat->dvfs_table[current_idx].upthreshold,
- current_pp, next_pp);
-}
-#endif
-
-#ifndef CONFIG_MALI_DVFS
-static int mali_stay_count = 0;
-static void mali_decide_next_status(struct mali_gpu_utilization_data *data, int* next_fs_idx,
- int* pp_change_flag)
-{
- u32 utilization, mali_up_limit, decided_fs_idx;
- u32 ld_left, ld_right;
- u32 ld_up, ld_down;
- u32 change_mode;
-
- *pp_change_flag = 0;
- change_mode = 0;
- utilization = data->utilization_gpu;
-
- mali_up_limit = (scaling_mode == MALI_TURBO_MODE) ?
- pmali_plat->turbo_clock : pmali_plat->scale_info.maxclk;
- decided_fs_idx = currentStep;
-
- ld_up = pmali_plat->dvfs_table[currentStep].upthreshold;
- ld_down = pmali_plat->dvfs_table[currentStep].downthreshold;
-
- scalingdbg(2, "utilization=%d, ld_up=%d\n ", utilization, ld_up);
- if (utilization >= ld_up) { /* go up */
-
- scalingdbg(2, "currentStep=%d, mali_up_limit=%d\n ", currentStep, mali_up_limit);
- if (currentStep < mali_up_limit) {
- change_mode = 1;
- if ((currentStep < pmali_plat->def_clock) && (utilization > pmali_plat->bst_gpu))
- decided_fs_idx = pmali_plat->def_clock;
- else
- decided_fs_idx++;
- }
- if ((data->utilization_pp >= ld_up) &&
- (num_cores_enabled < pmali_plat->scale_info.maxpp)) {
- if ((num_cores_enabled < pmali_plat->sc_mpp) && (data->utilization_pp >= pmali_plat->bst_pp)) {
- *pp_change_flag = 1;
- change_mode = 1;
- } else if (change_mode == 0) {
- *pp_change_flag = 2;
- change_mode = 1;
- }
- }
-#if LOG_MALI_SCALING
- scalingdbg(2, "[nexting..] [LD:%d]-> FS[CRNT:%d LMT:%d NEXT:%d] PP[NUM:%d LMT:%d MD:%d][F:%d]\n",
- data->utilization_pp, currentStep, mali_up_limit, decided_fs_idx,
- num_cores_enabled, pmali_plat->scale_info.maxpp, *pp_change_flag, change_mode);
-#endif
- } else if (utilization <= ld_down) { /* go down */
- if (mali_stay_count > 0) {
- *next_fs_idx = decided_fs_idx;
- mali_stay_count--;
- return;
- }
-
- if (num_cores_enabled > pmali_plat->sc_mpp) {
- change_mode = 1;
- if (data->utilization_pp <= ld_down) {
- ld_left = data->utilization_pp * num_cores_enabled;
- ld_right = (pmali_plat->dvfs_table[currentStep].upthreshold) *
- (num_cores_enabled - 1);
- if (ld_left < ld_right) {
- change_mode = 2;
- }
- }
- } else if (currentStep > pmali_plat->scale_info.minclk) {
- change_mode = 1;
- } else if (num_cores_enabled > 1) { /* decrease PPS */
- if (data->utilization_pp <= ld_down) {
- ld_left = data->utilization_pp * num_cores_enabled;
- ld_right = (pmali_plat->dvfs_table[currentStep].upthreshold) *
- (num_cores_enabled - 1);
- scalingdbg(2, "ld_left=%d, ld_right=%d\n", ld_left, ld_right);
- if (ld_left < ld_right) {
- change_mode = 2;
- }
- }
- }
-
- if (change_mode == 1) {
- decided_fs_idx--;
- } else if (change_mode == 2) { /* decrease PPS */
- *pp_change_flag = -1;
- }
- }
- if (change_mode)
- mali_stay_count = pmali_plat->dvfs_table[decided_fs_idx].keep_count;
- *next_fs_idx = decided_fs_idx;
-}
-#endif
-
-void mali_pp_fs_scaling_update(struct mali_gpu_utilization_data *data)
-{
-#ifndef CONFIG_MALI_DVFS
- int ret = 0;
- int pp_change_flag = 0;
- u32 next_idx = 0;
-
-#if LOG_MALI_SCALING
- u32 last_pp = num_cores_enabled;
-#endif
- mali_decide_next_status(data, &next_idx, &pp_change_flag);
-
- if (pp_change_flag == 1)
- ret = enable_pp_cores(pmali_plat->sc_mpp);
- else if (pp_change_flag == 2)
- ret = enable_one_core();
- else if (pp_change_flag == -1) {
- ret = disable_one_core();
- }
-
-#if LOG_MALI_SCALING
- if (pp_change_flag || (next_idx != currentStep))
- trace_utilization(data, currentStep, next_idx, last_pp, num_cores_enabled);
-#endif
-
- if (next_idx != currentStep) {
- ret = 1;
- currentStep = next_idx;
- }
-
- if (ret == 1)
- schedule_work(&wq_work);
-#ifdef CONFIG_MALI400_PROFILING
- else
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- get_current_frequency(),
- 0, 0, 0, 0);
-#endif
-#endif
-}
-
-u32 get_mali_schel_mode(void)
-{
- return scaling_mode;
-}
-
-void set_mali_schel_mode(u32 mode)
-{
-#ifndef CONFIG_MALI_DVFS
- MALI_DEBUG_ASSERT(mode < MALI_SCALING_MODE_MAX);
- if (mode >= MALI_SCALING_MODE_MAX)
- return;
- scaling_mode = mode;
-
- /* set default performance range. */
- pmali_plat->scale_info.minclk = pmali_plat->cfg_min_clock;
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- pmali_plat->scale_info.minpp = pmali_plat->cfg_min_pp;
- pmali_plat->scale_info.maxpp = pmali_plat->cfg_pp;
-
- /* set current status and tune max freq */
- if (scaling_mode == MALI_PP_FS_SCALING) {
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- enable_pp_cores(pmali_plat->sc_mpp);
- } else if (scaling_mode == MALI_SCALING_DISABLE) {
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- enable_max_num_cores();
- } else if (scaling_mode == MALI_TURBO_MODE) {
- pmali_plat->scale_info.maxclk = pmali_plat->turbo_clock;
- enable_max_num_cores();
- }
- currentStep = pmali_plat->scale_info.maxclk;
- schedule_work(&wq_work);
-#endif
-}
-
-u32 get_current_frequency(void)
-{
- return get_mali_freq(currentStep);
-}
-
-void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data)
-{
-#ifndef CONFIG_MALI_DVFS
- if (mali_pm_statue)
- return;
-
- switch (scaling_mode) {
- case MALI_PP_FS_SCALING:
- mali_pp_fs_scaling_update(data);
- break;
- case MALI_PP_SCALING:
- mali_pp_scaling_update(data);
- break;
- default:
- break;
- }
-#endif
-}
-
-void mali_dev_restore(void)
-{
-#ifndef CONFIG_MALI_DVFS
- mali_dvfs_threshold_table * pdvfs = pmali_plat->dvfs_table;
-
- //mali_perf_set_num_pp_cores(num_cores_enabled);
- mali_clock_set(pdvfs[currentStep].freq_index);
-#endif
-}
+++ /dev/null
-/*
- * Copyright (C) 2010, 2012-2013 ARM Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
- *
- * A copy of the licence is included with the program, and can also be obtained from Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-#include <linux/version.h>
-#include <linux/dma-mapping.h>
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/ioport.h>
-#include <linux/slab.h>
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#endif
-#include <asm/io.h>
-
-#include "meson_main.h"
-#include <linux/mali/mali_utgard.h>
-#include "mali_kernel_common.h"
-#include "common/mali_pmu.h"
-#include "common/mali_osk_profiling.h"
-
-int mali_pm_statue = 0;
-u32 mali_gp_reset_fail = 0;
-module_param(mali_gp_reset_fail, int, S_IRUSR | S_IWUSR | S_IWGRP | S_IRGRP | S_IROTH); /* rw-rw-r-- */
-MODULE_PARM_DESC(mali_gp_reset_fail, "times of failed to reset GP");
-u32 mali_core_timeout = 0;
-module_param(mali_core_timeout, int, S_IRUSR | S_IWUSR | S_IWGRP | S_IRGRP | S_IROTH); /* rw-rw-r-- */
-MODULE_PARM_DESC(mali_core_timeout, "times of failed to reset GP");
-
-static struct mali_gpu_device_data mali_gpu_data =
-{
- .shared_mem_size = 1024 * 1024 * 1024,
- .max_job_runtime = 60000, /* 60 seconds */
- .pmu_switch_delay = 0xFFFF, /* do not have to be this high on FPGA, but it is good for testing to have a delay */
-#if defined(CONFIG_ARCH_MESON8B)||defined(CONFIG_ARCH_MESONG9BB)
- .pmu_domain_config = {0x1, 0x2, 0x4, 0x0,
- 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x1, 0x2, 0x0},
-#else
- .pmu_domain_config = {0x1, 0x2, 0x4, 0x4,
- 0x0, 0x8, 0x8, 0x8,
- 0x0, 0x1, 0x2, 0x8},
-#endif
-};
-
-static void mali_platform_device_release(struct device *device);
-static struct platform_device mali_gpu_device =
-{
- .name = MALI_GPU_NAME_UTGARD,
- .id = 0,
- .dev.release = mali_platform_device_release,
- .dev.coherent_dma_mask = DMA_BIT_MASK(32),
- .dev.platform_data = &mali_gpu_data,
- .dev.type = &mali_pm_device, /* We should probably use the pm_domain instead of type on newer kernels */
-};
-
-int mali_pdev_pre_init(struct platform_device* ptr_plt_dev)
-{
- MALI_DEBUG_PRINT(4, ("mali_platform_device_register() called\n"));
- if (mali_gpu_data.shared_mem_size < 10) {
- MALI_DEBUG_PRINT(2, ("mali os memory didn't configered, set to default(512M)\n"));
- mali_gpu_data.shared_mem_size = 1024 * 1024 *1024;
- }
- return mali_meson_init_start(ptr_plt_dev);
-}
-
-void mali_pdev_post_init(struct platform_device* pdev)
-{
- mali_gp_reset_fail = 0;
- mali_core_timeout = 0;
-#ifdef CONFIG_PM_RUNTIME
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
- pm_runtime_set_autosuspend_delay(&(pdev->dev), 1000);
- pm_runtime_use_autosuspend(&(pdev->dev));
-#endif
- pm_runtime_enable(&(pdev->dev));
-#endif
- mali_meson_init_finish(pdev);
-}
-
-int mali_pdev_dts_init(struct platform_device* mali_gpu_device)
-{
- struct device_node *cfg_node = mali_gpu_device->dev.of_node;
- struct device_node *child;
- u32 prop_value;
- int err;
-
- for_each_child_of_node(cfg_node, child) {
- err = of_property_read_u32(child, "shared_memory", &prop_value);
- if (err == 0) {
- MALI_DEBUG_PRINT(2, ("shared_memory configurate %d\n", prop_value));
- mali_gpu_data.shared_mem_size = prop_value * 1024 * 1024;
- }
- }
-
- err = mali_pdev_pre_init(mali_gpu_device);
- if (err == 0)
- mali_pdev_post_init(mali_gpu_device);
- return err;
-}
-
-int mali_platform_device_register(void)
-{
- int err = -1;
- err = mali_pdev_pre_init(&mali_gpu_device);
- if (err == 0) {
- err = platform_device_register(&mali_gpu_device);
- if (0 == err)
- mali_pdev_post_init(&mali_gpu_device);
- }
- return err;
-}
-
-void mali_platform_device_unregister(void)
-{
- MALI_DEBUG_PRINT(4, ("mali_platform_device_unregister() called\n"));
- mali_core_scaling_term();
- platform_device_unregister(&mali_gpu_device);
- platform_device_put(&mali_gpu_device);
-}
-
-static void mali_platform_device_release(struct device *device)
-{
- MALI_DEBUG_PRINT(4, ("mali_platform_device_release() called\n"));
-}
-
-
+++ /dev/null
-/*
- * mali_platform.h
- *
- * Created on: Nov 8, 2013
- * Author: amlogic
- */
-
-#ifndef MESON_MAIN_H_
-#define MESON_MAIN_H_
-#include <linux/version.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#ifdef CONFIG_PM_RUNTIME
-#include <linux/pm_runtime.h>
-#endif
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/cpu.h>
-#endif
-
-#include "mali_scaling.h"
-#include "mali_clock.h"
-
-extern struct device_type mali_pm_device;
-extern int mali_pm_statue;
-
-u32 set_max_mali_freq(u32 idx);
-u32 get_max_mali_freq(void);
-
-int mali_meson_init_start(struct platform_device* ptr_plt_dev);
-int mali_meson_init_finish(struct platform_device* ptr_plt_dev);
-int mali_meson_uninit(struct platform_device* ptr_plt_dev);
-int mali_light_suspend(struct device *device);
-int mali_light_resume(struct device *device);
-int mali_deep_suspend(struct device *device);
-int mali_deep_resume(struct device *device);
-
-#endif /* MESON_MAIN_H_ */
+++ /dev/null
-/*******************************************************************
- *
- * Copyright C 2013 by Amlogic, Inc. All Rights Reserved.
- *
- * Description:
- *
- * Author: Amlogic Software
- * Created: 2010/4/1 19:46
- *
- *******************************************************************/
-/* Standard Linux headers */
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/string.h>
-#include <linux/slab.h>
-#include <linux/list.h>
-
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/io.h>
-#include <plat/io.h>
-#include <asm/io.h>
-#endif
-
-#include <linux/mali/mali_utgard.h>
-#include <common/mali_kernel_common.h>
-#include <common/mali_pmu.h>
-#include "mali_pp_scheduler.h"
-#include "meson_main.h"
-
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
-static ssize_t domain_stat_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
-#if 0
- unsigned int val;
-
- val = readl((u32 *)(IO_AOBUS_BASE + 0xf0)) & 0xff;
- return sprintf(buf, "%x\n", val>>4);
-#else
- return 0;
-#endif
-}
-
-#define PREHEAT_CMD "preheat"
-#define PLL2_CMD "mpl2" /* mpl2 [11] or [0xxxxxxx] */
-#define SCMPP_CMD "scmpp" /* scmpp [number of pp your want in most of time]. */
-#define BSTGPU_CMD "bstgpu" /* bstgpu [0-256] */
-#define BSTPP_CMD "bstpp" /* bstpp [0-256] */
-#define LIMIT_CMD "lmt" /* lmt [0 or 1] */
-#define MAX_TOKEN 20
-#define FULL_UTILIZATION 256
-
-static ssize_t mpgpu_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- char *pstart, *cprt = NULL;
- u32 val = 0;
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
-
- cprt = skip_spaces(buf);
- pstart = strsep(&cprt," ");
- if (strlen(pstart) < 1)
- goto quit;
-
- if(!strncmp(pstart, PREHEAT_CMD, MAX_TOKEN)) {
- if (pmali_plat->plat_preheat) {
- pmali_plat->plat_preheat();
- }
- } else if (!strncmp(pstart, PLL2_CMD, MAX_TOKEN)) {
- int base = 10;
- if ((strlen(cprt) > 2) && (cprt[0] == '0') &&
- (cprt[1] == 'x' || cprt[1] == 'X'))
- base = 16;
- if (kstrtouint(cprt, base, &val) <0)
- goto quit;
- if (val < 11)
- pmali_plat->cfg_clock = pmali_plat->cfg_clock_bkup;
- else
- pmali_plat->cfg_clock = pmali_plat->turbo_clock;
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- set_str_src(val);
- } else if (!strncmp(pstart, SCMPP_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
- if ((val > 0) && (val < pmali_plat->cfg_pp)) {
- pmali_plat->sc_mpp = val;
- }
- } else if (!strncmp(pstart, BSTGPU_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
- if ((val > 0) && (val < FULL_UTILIZATION)) {
- pmali_plat->bst_gpu = val;
- }
- } else if (!strncmp(pstart, BSTPP_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
- if ((val > 0) && (val < FULL_UTILIZATION)) {
- pmali_plat->bst_pp = val;
- }
- } else if (!strncmp(pstart, LIMIT_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
-
- if (val < 2) {
- pmali_plat->limit_on = val;
- if (val == 0) {
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- pmali_plat->scale_info.maxpp = pmali_plat->cfg_pp;
- revise_mali_rt();
- }
- }
- }
-quit:
- return count;
-}
-
-static ssize_t scale_mode_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- return sprintf(buf, "%d\n", get_mali_schel_mode());
-}
-
-static ssize_t scale_mode_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
-
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- {
- return -EINVAL;
- }
-
- set_mali_schel_mode(val);
-
- return count;
-}
-
-static ssize_t max_pp_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- printk("maxpp:%d, maxpp_sysfs:%d, total=%d\n",
- pmali_plat->scale_info.maxpp, pmali_plat->maxpp_sysfs,
- mali_pp_scheduler_get_num_cores_total());
- return sprintf(buf, "%d\n", mali_pp_scheduler_get_num_cores_total());
-}
-
-static ssize_t max_pp_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pmali_plat->cfg_pp) || (val < pinfo->minpp))
- return -EINVAL;
-
- pmali_plat->maxpp_sysfs = val;
- pinfo->maxpp = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t min_pp_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- return sprintf(buf, "%d\n", pmali_plat->scale_info.minpp);
-}
-
-static ssize_t min_pp_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pinfo->maxpp) || (val < 1))
- return -EINVAL;
-
- pinfo->minpp = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t max_freq_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- printk("maxclk:%d, maxclk_sys:%d, max gpu level=%d\n",
- pmali_plat->scale_info.maxclk, pmali_plat->maxclk_sysfs, get_gpu_max_clk_level());
- return sprintf(buf, "%d\n", get_gpu_max_clk_level());
-}
-
-static ssize_t max_freq_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pmali_plat->cfg_clock) || (val < pinfo->minclk))
- return -EINVAL;
-
- pmali_plat->maxclk_sysfs = val;
- pinfo->maxclk = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t min_freq_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- return sprintf(buf, "%d\n", pmali_plat->scale_info.minclk);
-}
-
-static ssize_t min_freq_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pinfo->maxclk))
- return -EINVAL;
-
- pinfo->minclk = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t freq_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- return sprintf(buf, "%d\n", get_current_frequency());
-}
-
-static ssize_t freq_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- u32 clk, pp;
- get_mali_rt_clkpp(&clk, &pp);
-
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- return -EINVAL;
-
- set_mali_rt_clkpp(val, pp, 1);
-
- return count;
-}
-
-static ssize_t current_pp_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- u32 clk, pp;
- get_mali_rt_clkpp(&clk, &pp);
- return sprintf(buf, "%d\n", pp);
-}
-
-static ssize_t current_pp_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- u32 clk, pp;
-
- get_mali_rt_clkpp(&clk, &pp);
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- {
- return -EINVAL;
- }
-
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- return -EINVAL;
-
- set_mali_rt_clkpp(clk, val, 1);
-
- return count;
-}
-
-static struct class_attribute mali_class_attrs[] = {
- __ATTR(domain_stat, 0644, domain_stat_read, NULL),
- __ATTR(mpgpucmd, 0644, NULL, mpgpu_write),
- __ATTR(scale_mode, 0644, scale_mode_read, scale_mode_write),
- __ATTR(min_freq, 0644, min_freq_read, min_freq_write),
- __ATTR(max_freq, 0644, max_freq_read, max_freq_write),
- __ATTR(min_pp, 0644, min_pp_read, min_pp_write),
- __ATTR(max_pp, 0644, max_pp_read, max_pp_write),
- __ATTR(cur_freq, 0644, freq_read, freq_write),
- __ATTR(cur_pp, 0644, current_pp_read, current_pp_write),
-};
-
-static struct class mpgpu_class = {
- .name = "mpgpu",
-};
-#endif
-
-int mpgpu_class_init(void)
-{
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
- int ret = 0;
- int i;
- int attr_num = ARRAY_SIZE(mali_class_attrs);
-
- ret = class_register(&mpgpu_class);
- if (ret) {
- printk(KERN_ERR "%s: class_register failed\n", __func__);
- return ret;
- }
- for (i = 0; i< attr_num; i++) {
- ret = class_create_file(&mpgpu_class, &mali_class_attrs[i]);
- if (ret) {
- printk(KERN_ERR "%d ST: class item failed to register\n", i);
- }
- }
- return ret;
-#else
- return 0;
-#endif
-}
-
-void mpgpu_class_exit(void)
-{
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
- class_unregister(&mpgpu_class);
-#endif
-}
-
--- /dev/null
+$(warning src is $(src))
+$(warning MAKEFILE_LIST is $(MAKEFILE_LIST))
+
+GPU_DRV_VERSION?=r7p0
+
+KDIR?=/home/jiyu.yang/source/br-wayland/output/meson8b_m201/build/linux/
+ARCH?=arm
+CROSS_COMPILE?=arm-linux-gnueabihf-
+MALI400?=m
+EXTRA_CFLAGS+="-DCONFIG_MALI400=m"
+UTGARD_MAKEFILE:=$(shell pwd)/$(lastword $(MAKEFILE_LIST))
+UTGARD_DIR=$(dir $(UTGARD_MAKEFILE))
+
+.ONESHELL:
+gpu:
+ echo "utgard makefile dir is $(UTGARD_MAKEFILE)"; \
+ echo "utgard dir is $(UTGARD_DIR)"; \
+ echo "gpu build"; \
+ echo "MAKE is $(MAKE)"; \
+ echo "MAKE1 is $(MAKE1)"; \
+ if [ ! -d $(GPU_DRV_VERSION) ]; then \
+ ln -s $(UTGARD_DIR)../mali $(GPU_DRV_VERSION); \
+ fi ;\
+ cd $(GPU_DRV_VERSION); \
+ if [ ! -d platform ]; then \
+ ln -s $(UTGARD_DIR)platform platform; \
+ fi ;\
+ $(MAKE) -C $(KDIR) M=`pwd` CONFIG_MALI400=$(MALI400) modules
+
+clean:
+ echo "clean this module"
+ cd $(UTGARD_DIR)
+ -cd $(GPU_DRV_VERSION)
+ find . -name "*.o" -o -name "*.cmd" -o -name "*~" | xargs rm -rf
+ find . -name "Module.symvers" -o -name "*.ko" -o -name "*.mod.c" \
+ -o -name "modules.order" -o -name "*pyc" -o -name __malidrv_build_info.c | xargs rm -f
+ -cd $(UTGARD_DIR)
+ find . -name "*.o" -o -name "*.cmd" -o -name "*~" | xargs rm -rf
+ find . -name "Module.symvers" -o -name "*.ko" -o -name "*.mod.c" \
+ -o -name "modules.order" -o -name "*pyc" -o -name __malidrv_build_info.c | xargs rm -f
--- /dev/null
+ifeq ($(CONFIG_MALI_DVFS),y)
+ EXTRA_DEFINES += -DCONFIG_MALI_DVFS
+ USING_GPU_UTILIZATION=0
+ USING_DVFS=1
+else
+ USING_GPU_UTILIZATION=1
+ USING_DVFS=0
+endif
+
+ifeq ($(CONFIG_MALI400_DEBUG),y)
+ BUILD ?= debug
+else
+ BUILD ?= release
+ ldflags-y += --strip-debug
+endif
+
+#########
+TARGET_PLATFORM:=meson_bu
+ifeq ($(CONFIG_ARCH_MESON1),y)
+TARGET_PLATFORM:= meson_m400
+endif
+ifeq ($(CONFIG_ARCH_MESON3),y)
+TARGET_PLATFORM:= meson_m400
+endif
+ifeq ($(CONFIG_ARCH_MESON6),y)
+TARGET_PLATFORM:= meson_m400
+endif
+ifeq ($(CONFIG_ARCH_MESON6TV),y)
+TARGET_PLATFORM:= meson_m400
+endif
+
+ifeq ($(CONFIG_ARCH_MESON8),y)
+TARGET_PLATFORM:= meson_m450
+endif
+ifeq ($(CONFIG_ARCH_MESON6TVD),y)
+TARGET_PLATFORM:= meson_m450
+endif
+ifeq ($(CONFIG_ARCH_MESON8B),y)
+TARGET_PLATFORM:= meson_m450
+endif
+ifeq ($(CONFIG_ARCH_MESONG9TV),y)
+TARGET_PLATFORM:= meson_m450
+endif
+ifeq ($(CONFIG_ARCH_MESONG9BB),y)
+TARGET_PLATFORM:= meson_m450
+endif
+#########
+$(platform Kbuild.amlogic warning TARGET_PLATFORM is $(TARGET_PLATFORM))
+ifeq ($(TARGET_PLATFORM),meson_m400)
+MALI_PLATFORM_FILES:= \
+ platform/meson_m400/mali_fix.c \
+ platform/meson_m400/mali_platform.c \
+ platform/meson_m400/platform_mx.c
+endif
+
+ifeq ($(TARGET_PLATFORM),meson_m450)
+EXTRA_DEFINES += -DCONFIG_MALI450=y
+MALI_PLATFORM_FILES:= \
+ platform/meson_m450/meson_main.c \
+ platform/meson_m450/mali_pm_device.c \
+ platform/meson_m450/mali_clock.c \
+ platform/meson_m450/mpgpu.c \
+ platform/meson_m450/scaling.c
+
+ifeq ($(CONFIG_ARCH_MESON),y)
+MALI_PLATFORM_FILES+= \
+ platform/meson_m450/platform_m8.c
+endif
+ifeq ($(CONFIG_ARCH_MESON8),y)
+MALI_PLATFORM_FILES+= \
+ platform/meson_m450/platform_m8.c
+endif
+ifeq ($(CONFIG_ARCH_MESON6TVD),y)
+MALI_PLATFORM_FILES+= \
+ platform/meson_m450/platform_m6tvd.c
+endif
+ifeq ($(CONFIG_ARCH_MESON8B),y)
+MALI_PLATFORM_FILES+= \
+ platform/meson_m450/platform_m8b.c
+endif
+ifeq ($(CONFIG_ARCH_MESONG9TV),y)
+MALI_PLATFORM_FILES+= \
+ platform/meson_m450/platform_m8.c
+endif
+ifeq ($(CONFIG_ARCH_MESONG9BB),y)
+MALI_PLATFORM_FILES+= \
+ platform/meson_m450/platform_m8b.c
+endif
+
+endif
+
+ifeq ($(TARGET_PLATFORM),meson_bu)
+ifndef CONFIG_MALI450
+EXTRA_DEFINES += -DCONFIG_MALI450=y
+endif
+
+ccflags-y += -DCONFIG_MALI_DT=y
+ccflags-y += -DMESON_CPU_TYPE=0x80
+ccflags-y += -DMESON_CPU_TYPE_MESON6=0x60
+ccflags-y += -DMESON_CPU_TYPE_MESON6TVD=0x75
+ccflags-y += -DMESON_CPU_TYPE_MESON8=0x80
+ccflags-y += -DMESON_CPU_TYPE_MESON8B=0x8B
+
+USE_GPPLL?=0
+ifdef CONFIG_AM_VIDEO
+ USE_GPPLL:=1
+endif
+
+ccflags-y += -DAMLOGIC_GPU_USE_GPPLL=$(USE_GPPLL)
+
+MALI_PLATFORM_FILES:= \
+ platform/meson_bu/mali_pm_device.c \
+ platform/meson_bu/meson_main2.c \
+ platform/meson_bu/mali_clock.c \
+ platform/meson_bu/mpgpu.c \
+ platform/meson_bu/platform_gx.c
+
+ifeq ($(CONFIG_MALI_DVFS),y)
+MALI_PLATFORM_FILES+= \
+ meson_bu/mali_dvfs.c
+else
+MALI_PLATFORM_FILES+= \
+ platform/meson_bu/scaling.c
+endif
+endif
+
+ifndef CONFIG_DMA_SHARED_BUFFER
+ ccflags-y += -DCONFIG_DMA_SHARED_BUFFER=y
+endif
+
+ifndef CONFIG_MALI_DMA_BUF_MAP_ON_ATTACH
+ ccflags-y += -DCONFIG_MALI_DMA_BUF_MAP_ON_ATTACH=y
+endif
+
+ccflags-y += -I$(src)/platform/$(TARGET_PLATFORM)
+ccflags-y += -DMALI_FAKE_PLATFORM_DEVICE=1
+#$(warning r7p0/Kbuild.plat ccflags-y is $(ccflags-y))
+
+
+#####################################################
+ifeq (true,false)
+ifndef CONFIG_MALI_DMA_BUF_MAP_ON_ATTACH
+ ccflags-y += -DCONFIG_MALI_DMA_BUF_MAP_ON_ATTACH=y
+endif
+
+ccflags-y += -DCONFIG_MALI_DT=y
+ccflags-y += -DMESON_CPU_TYPE=0x80
+ccflags-y += -DMESON_CPU_TYPE_MESON6=0x60
+ccflags-y += -DMESON_CPU_TYPE_MESON6TVD=0x75
+ccflags-y += -DMESON_CPU_TYPE_MESON8=0x80
+ccflags-y += -DMESON_CPU_TYPE_MESON8B=0x8B
+
+USE_GPPLL?=0
+ifdef CONFIG_AM_VIDEO
+ USE_GPPLL:=1
+endif
+
+ccflags-y += -DAMLOGIC_GPU_USE_GPPLL=$(USE_GPPLL)
+endif
--- /dev/null
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/clk-provider.h>
+#include <linux/clk.h>
+#include <linux/of_address.h>
+#include <linux/delay.h>
+#include <linux/mali/mali_utgard.h>
+#include <linux/amlogic/cpu_version.h>
+#include "mali_scaling.h"
+#include "mali_clock.h"
+
+#ifndef AML_CLK_LOCK_ERROR
+#define AML_CLK_LOCK_ERROR 1
+#endif
+#define GXBBM_MAX_GPU_FREQ 700000000UL
+struct clk;
+static unsigned gpu_dbg_level = 0;
+module_param(gpu_dbg_level, uint, 0644);
+MODULE_PARM_DESC(gpu_dbg_level, "gpu debug level");
+
+#define gpu_dbg(level, fmt, arg...) \
+ do { \
+ if (gpu_dbg_level >= (level)) \
+ printk("gpu_debug"fmt , ## arg); \
+ } while (0)
+
+#define GPU_CLK_DBG(fmt, arg...)
+
+//disable print
+#define _dev_info(...)
+
+//static DEFINE_SPINLOCK(lock);
+static mali_plat_info_t* pmali_plat = NULL;
+//static u32 mali_extr_backup = 0;
+//static u32 mali_extr_sample_backup = 0;
+struct timeval start;
+struct timeval end;
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 16))
+int mali_clock_init_clk_tree(struct platform_device* pdev)
+{
+ mali_dvfs_threshold_table *dvfs_tbl = &pmali_plat->dvfs_table[pmali_plat->def_clock];
+ struct clk *clk_mali_0_parent = dvfs_tbl->clkp_handle;
+ struct clk *clk_mali_0 = pmali_plat->clk_mali_0;
+#ifdef AML_CLK_LOCK_ERROR
+ struct clk *clk_mali_1 = pmali_plat->clk_mali_1;
+#endif
+ struct clk *clk_mali = pmali_plat->clk_mali;
+
+ clk_set_parent(clk_mali_0, clk_mali_0_parent);
+
+ clk_prepare_enable(clk_mali_0);
+
+ clk_set_parent(clk_mali, clk_mali_0);
+
+#ifdef AML_CLK_LOCK_ERROR
+ clk_set_parent(clk_mali_1, clk_mali_0_parent);
+ clk_prepare_enable(clk_mali_1);
+#endif
+
+ GPU_CLK_DBG("%s:enable(%d), %s:enable(%d)\n",
+ clk_mali_0->name, clk_mali_0->enable_count,
+ clk_mali_0_parent->name, clk_mali_0_parent->enable_count);
+
+ return 0;
+}
+
+int mali_clock_init(mali_plat_info_t *pdev)
+{
+ *pdev = *pdev;
+ return 0;
+}
+
+int mali_clock_critical(critical_t critical, size_t param)
+{
+ int ret = 0;
+
+ ret = critical(param);
+
+ return ret;
+}
+
+static int critical_clock_set(size_t param)
+{
+ int ret = 0;
+ unsigned int idx = param;
+ mali_dvfs_threshold_table *dvfs_tbl = &pmali_plat->dvfs_table[idx];
+
+ struct clk *clk_mali_0 = pmali_plat->clk_mali_0;
+ struct clk *clk_mali_1 = pmali_plat->clk_mali_1;
+ struct clk *clk_mali_x = NULL;
+ struct clk *clk_mali_x_parent = NULL;
+ struct clk *clk_mali_x_old = NULL;
+ struct clk *clk_mali = pmali_plat->clk_mali;
+ unsigned long time_use=0;
+
+ clk_mali_x_old = clk_get_parent(clk_mali);
+
+ if (!clk_mali_x_old) {
+ printk("gpu: could not get clk_mali_x_old or clk_mali_x_old\n");
+ return 0;
+ }
+ if (clk_mali_x_old == clk_mali_0) {
+ clk_mali_x = clk_mali_1;
+ } else if (clk_mali_x_old == clk_mali_1) {
+ clk_mali_x = clk_mali_0;
+ } else {
+ printk("gpu: unmatched clk_mali_x_old\n");
+ return 0;
+ }
+
+ GPU_CLK_DBG("idx=%d, clk_freq=%d\n", idx, dvfs_tbl->clk_freq);
+ clk_mali_x_parent = dvfs_tbl->clkp_handle;
+ if (!clk_mali_x_parent) {
+ printk("gpu: could not get clk_mali_x_parent\n");
+ return 0;
+ }
+
+ GPU_CLK_DBG();
+ ret = clk_set_rate(clk_mali_x_parent, dvfs_tbl->clkp_freq);
+ GPU_CLK_DBG();
+ ret = clk_set_parent(clk_mali_x, clk_mali_x_parent);
+ GPU_CLK_DBG();
+ ret = clk_set_rate(clk_mali_x, dvfs_tbl->clk_freq);
+ GPU_CLK_DBG();
+#ifndef AML_CLK_LOCK_ERROR
+ ret = clk_prepare_enable(clk_mali_x);
+#endif
+ GPU_CLK_DBG("new %s:enable(%d)\n", clk_mali_x->name, clk_mali_x->enable_count);
+ do_gettimeofday(&start);
+ udelay(1);// delay 10ns
+ do_gettimeofday(&end);
+ ret = clk_set_parent(clk_mali, clk_mali_x);
+ GPU_CLK_DBG();
+
+#ifndef AML_CLK_LOCK_ERROR
+ clk_disable_unprepare(clk_mali_x_old);
+#endif
+ GPU_CLK_DBG("old %s:enable(%d)\n", clk_mali_x_old->name, clk_mali_x_old->enable_count);
+ time_use = (end.tv_sec - start.tv_sec)*1000000 + end.tv_usec - start.tv_usec;
+ GPU_CLK_DBG("step 1, mali_mux use: %ld us\n", time_use);
+
+ return 0;
+}
+
+int mali_clock_set(unsigned int clock)
+{
+ return mali_clock_critical(critical_clock_set, (size_t)clock);
+}
+
+void disable_clock(void)
+{
+ struct clk *clk_mali = pmali_plat->clk_mali;
+ struct clk *clk_mali_x = NULL;
+
+ clk_mali_x = clk_get_parent(clk_mali);
+ GPU_CLK_DBG();
+#ifndef AML_CLK_LOCK_ERROR
+ clk_disable_unprepare(clk_mali_x);
+#endif
+ GPU_CLK_DBG();
+}
+
+void enable_clock(void)
+{
+ struct clk *clk_mali = pmali_plat->clk_mali;
+ struct clk *clk_mali_x = NULL;
+
+ clk_mali_x = clk_get_parent(clk_mali);
+ GPU_CLK_DBG();
+#ifndef AML_CLK_LOCK_ERROR
+ clk_prepare_enable(clk_mali_x);
+#endif
+ GPU_CLK_DBG();
+}
+
+u32 get_mali_freq(u32 idx)
+{
+ if (!mali_pm_statue) {
+ return pmali_plat->clk_sample[idx];
+ } else {
+ return 0;
+ }
+}
+
+void set_str_src(u32 data)
+{
+ printk("gpu: %s, %s, %d\n", __FILE__, __func__, __LINE__);
+}
+
+int mali_dt_info(struct platform_device *pdev, struct mali_plat_info_t *mpdata)
+{
+ struct device_node *gpu_dn = pdev->dev.of_node;
+ struct device_node *gpu_clk_dn;
+ struct mali_gpu_clk_item *clk_item;
+ phandle dvfs_clk_hdl;
+ mali_dvfs_threshold_table *dvfs_tbl = NULL;
+ uint32_t *clk_sample = NULL;
+
+ struct property *prop;
+ const __be32 *p;
+ int length = 0, i = 0;
+ u32 u;
+
+ int ret = 0;
+ if (!gpu_dn) {
+ dev_notice(&pdev->dev, "gpu device node not right\n");
+ return -ENODEV;
+ }
+
+ ret = of_property_read_u32(gpu_dn,"num_of_pp",
+ &mpdata->cfg_pp);
+ if (ret) {
+ dev_notice(&pdev->dev, "set max pp to default 6\n");
+ mpdata->cfg_pp = 6;
+ }
+ mpdata->scale_info.maxpp = mpdata->cfg_pp;
+ mpdata->maxpp_sysfs = mpdata->cfg_pp;
+ _dev_info(&pdev->dev, "max pp is %d\n", mpdata->scale_info.maxpp);
+
+ ret = of_property_read_u32(gpu_dn,"min_pp",
+ &mpdata->cfg_min_pp);
+ if (ret) {
+ dev_notice(&pdev->dev, "set min pp to default 1\n");
+ mpdata->cfg_min_pp = 1;
+ }
+ mpdata->scale_info.minpp = mpdata->cfg_min_pp;
+ _dev_info(&pdev->dev, "min pp is %d\n", mpdata->scale_info.minpp);
+
+ ret = of_property_read_u32(gpu_dn,"min_clk",
+ &mpdata->cfg_min_clock);
+ if (ret) {
+ dev_notice(&pdev->dev, "set min clk default to 0\n");
+ mpdata->cfg_min_clock = 0;
+ }
+ mpdata->scale_info.minclk = mpdata->cfg_min_clock;
+ _dev_info(&pdev->dev, "min clk is %d\n", mpdata->scale_info.minclk);
+
+ mpdata->reg_base_hiubus = of_iomap(gpu_dn, 1);
+ _dev_info(&pdev->dev, "hiu io source 0x%p\n", mpdata->reg_base_hiubus);
+
+ mpdata->reg_base_aobus = of_iomap(gpu_dn, 2);
+ _dev_info(&pdev->dev, "hiu io source 0x%p\n", mpdata->reg_base_aobus);
+
+ ret = of_property_read_u32(gpu_dn,"sc_mpp",
+ &mpdata->sc_mpp);
+ if (ret) {
+ dev_notice(&pdev->dev, "set pp used most of time default to %d\n", mpdata->cfg_pp);
+ mpdata->sc_mpp = mpdata->cfg_pp;
+ }
+ _dev_info(&pdev->dev, "num of pp used most of time %d\n", mpdata->sc_mpp);
+
+ of_get_property(gpu_dn, "tbl", &length);
+
+ length = length /sizeof(u32);
+ _dev_info(&pdev->dev, "clock dvfs cfg table size is %d\n", length);
+
+ mpdata->dvfs_table = devm_kzalloc(&pdev->dev,
+ sizeof(struct mali_dvfs_threshold_table)*length,
+ GFP_KERNEL);
+ dvfs_tbl = mpdata->dvfs_table;
+ if (mpdata->dvfs_table == NULL) {
+ dev_err(&pdev->dev, "failed to alloc dvfs table\n");
+ return -ENOMEM;
+ }
+ mpdata->clk_sample = devm_kzalloc(&pdev->dev, sizeof(u32)*length, GFP_KERNEL);
+ if (mpdata->clk_sample == NULL) {
+ dev_err(&pdev->dev, "failed to alloc clk_sample table\n");
+ return -ENOMEM;
+ }
+ clk_sample = mpdata->clk_sample;
+///////////
+ mpdata->clk_items = devm_kzalloc(&pdev->dev, sizeof(struct mali_gpu_clk_item) * length, GFP_KERNEL);
+ if (mpdata->clk_items == NULL) {
+ dev_err(&pdev->dev, "failed to alloc clk_item table\n");
+ return -ENOMEM;
+ }
+ clk_item = mpdata->clk_items;
+//
+ of_property_for_each_u32(gpu_dn, "tbl", prop, p, u) {
+ dvfs_clk_hdl = (phandle) u;
+ gpu_clk_dn = of_find_node_by_phandle(dvfs_clk_hdl);
+ ret = of_property_read_u32(gpu_clk_dn,"clk_freq", &dvfs_tbl->clk_freq);
+ if (ret) {
+ dev_notice(&pdev->dev, "read clk_freq failed\n");
+ }
+#if 0
+#ifdef MESON_CPU_VERSION_OPS
+ if (is_meson_gxbbm_cpu()) {
+ if (dvfs_tbl->clk_freq >= GXBBM_MAX_GPU_FREQ)
+ continue;
+ }
+#endif
+#endif
+ ret = of_property_read_string(gpu_clk_dn,"clk_parent",
+ &dvfs_tbl->clk_parent);
+ if (ret) {
+ dev_notice(&pdev->dev, "read clk_parent failed\n");
+ }
+ dvfs_tbl->clkp_handle = devm_clk_get(&pdev->dev, dvfs_tbl->clk_parent);
+ if (IS_ERR(dvfs_tbl->clkp_handle)) {
+ dev_notice(&pdev->dev, "failed to get %s's clock pointer\n", dvfs_tbl->clk_parent);
+ }
+ ret = of_property_read_u32(gpu_clk_dn,"clkp_freq", &dvfs_tbl->clkp_freq);
+ if (ret) {
+ dev_notice(&pdev->dev, "read clk_parent freq failed\n");
+ }
+ ret = of_property_read_u32(gpu_clk_dn,"voltage", &dvfs_tbl->voltage);
+ if (ret) {
+ dev_notice(&pdev->dev, "read voltage failed\n");
+ }
+ ret = of_property_read_u32(gpu_clk_dn,"keep_count", &dvfs_tbl->keep_count);
+ if (ret) {
+ dev_notice(&pdev->dev, "read keep_count failed\n");
+ }
+ //downthreshold and upthreshold shall be u32
+ ret = of_property_read_u32_array(gpu_clk_dn,"threshold",
+ &dvfs_tbl->downthreshold, 2);
+ if (ret) {
+ dev_notice(&pdev->dev, "read threshold failed\n");
+ }
+ dvfs_tbl->freq_index = i;
+ clk_item->clock = dvfs_tbl->clk_freq / 1000000;
+ clk_item->vol = dvfs_tbl->voltage;
+
+ *clk_sample = dvfs_tbl->clk_freq / 1000000;
+
+ dvfs_tbl ++;
+ clk_item ++;
+ clk_sample ++;
+ i++;
+ mpdata->dvfs_table_size ++;
+ }
+
+ ret = of_property_read_u32(gpu_dn,"max_clk",
+ &mpdata->cfg_clock);
+ if (ret) {
+ dev_notice(&pdev->dev, "max clk set %d\n", mpdata->dvfs_table_size-2);
+ mpdata->cfg_clock = mpdata->dvfs_table_size-2;
+ }
+
+ mpdata->cfg_clock_bkup = mpdata->cfg_clock;
+ mpdata->maxclk_sysfs = mpdata->cfg_clock;
+ mpdata->scale_info.maxclk = mpdata->cfg_clock;
+ _dev_info(&pdev->dev, "max clk is %d\n", mpdata->scale_info.maxclk);
+
+ ret = of_property_read_u32(gpu_dn,"turbo_clk",
+ &mpdata->turbo_clock);
+ if (ret) {
+ dev_notice(&pdev->dev, "turbo clk set to %d\n", mpdata->dvfs_table_size-1);
+ mpdata->turbo_clock = mpdata->dvfs_table_size-1;
+ }
+ _dev_info(&pdev->dev, "turbo clk is %d\n", mpdata->turbo_clock);
+
+ ret = of_property_read_u32(gpu_dn,"def_clk",
+ &mpdata->def_clock);
+ if (ret) {
+ dev_notice(&pdev->dev, "default clk set to %d\n", mpdata->dvfs_table_size/2-1);
+ mpdata->def_clock = mpdata->dvfs_table_size/2 - 1;
+ }
+ _dev_info(&pdev->dev, "default clk is %d\n", mpdata->def_clock);
+
+ dvfs_tbl = mpdata->dvfs_table;
+ clk_sample = mpdata->clk_sample;
+ for (i = 0; i< mpdata->dvfs_table_size; i++) {
+ _dev_info(&pdev->dev, "====================%d====================\n"
+ "clk_freq=%10d, clk_parent=%9s, voltage=%d, keep_count=%d, threshod=<%d %d>, clk_sample=%d\n",
+ i,
+ dvfs_tbl->clk_freq, dvfs_tbl->clk_parent,
+ dvfs_tbl->voltage, dvfs_tbl->keep_count,
+ dvfs_tbl->downthreshold, dvfs_tbl->upthreshold, *clk_sample);
+ dvfs_tbl ++;
+ clk_sample ++;
+ }
+ _dev_info(&pdev->dev, "clock dvfs table size is %d\n", mpdata->dvfs_table_size);
+
+ mpdata->clk_mali = devm_clk_get(&pdev->dev, "clk_mali");
+ mpdata->clk_mali_0 = devm_clk_get(&pdev->dev, "clk_mali_0");
+ mpdata->clk_mali_1 = devm_clk_get(&pdev->dev, "clk_mali_1");
+ if (IS_ERR(mpdata->clk_mali) || IS_ERR(mpdata->clk_mali_0) || IS_ERR(mpdata->clk_mali_1)) {
+ dev_err(&pdev->dev, "failed to get clock pointer\n");
+ return -EFAULT;
+ }
+
+ pmali_plat = mpdata;
+ mpdata->pdev = pdev;
+ return 0;
+}
+#else
+int mali_clock_init_clk_tree(struct platform_device* pdev)
+{
+ //mali_dvfs_threshold_table *dvfs_tbl = &pmali_plat->dvfs_table[pmali_plat->def_clock];
+ struct clk *clk_mali = pmali_plat->clk_mali;
+
+ clk_prepare_enable(clk_mali);
+
+ return 0;
+}
+
+int mali_clock_init(mali_plat_info_t *pdev)
+{
+ *pdev = *pdev;
+ return 0;
+}
+
+int mali_clock_critical(critical_t critical, size_t param)
+{
+ int ret = 0;
+
+ ret = critical(param);
+
+ return ret;
+}
+
+static int critical_clock_set(size_t param)
+{
+ int ret = 0;
+ unsigned int idx = param;
+ mali_dvfs_threshold_table *dvfs_tbl = &pmali_plat->dvfs_table[idx];
+
+ struct clk *clk_mali = pmali_plat->clk_mali;
+ unsigned long time_use=0;
+
+
+ GPU_CLK_DBG();
+ do_gettimeofday(&start);
+ ret = clk_set_rate(clk_mali, dvfs_tbl->clk_freq);
+ do_gettimeofday(&end);
+ GPU_CLK_DBG();
+
+#ifndef AML_CLK_LOCK_ERROR
+ clk_disable_unprepare(clk_mali_x_old);
+#endif
+ time_use = (end.tv_sec - start.tv_sec)*1000000 + end.tv_usec - start.tv_usec;
+ GPU_CLK_DBG("step 1, mali_mux use: %ld us\n", time_use);
+
+ return 0;
+}
+
+int mali_clock_set(unsigned int clock)
+{
+ return mali_clock_critical(critical_clock_set, (size_t)clock);
+}
+
+void disable_clock(void)
+{
+#ifndef AML_CLK_LOCK_ERROR
+ struct clk *clk_mali = pmali_plat->clk_mali;
+
+ GPU_CLK_DBG();
+ clk_disable_unprepare(clk_mali);
+#endif
+ GPU_CLK_DBG();
+}
+
+void enable_clock(void)
+{
+#ifndef AML_CLK_LOCK_ERROR
+ struct clk *clk_mali = pmali_plat->clk_mali;
+
+ clk_prepare_enable(clk_mali);
+#endif
+ GPU_CLK_DBG();
+}
+
+u32 get_mali_freq(u32 idx)
+{
+ if (!mali_pm_statue) {
+ return pmali_plat->clk_sample[idx];
+ } else {
+ return 0;
+ }
+}
+
+void set_str_src(u32 data)
+{
+ printk("gpu: %s, %s, %d\n", __FILE__, __func__, __LINE__);
+}
+
+int mali_dt_info(struct platform_device *pdev, struct mali_plat_info_t *mpdata)
+{
+ struct device_node *gpu_dn = pdev->dev.of_node;
+ struct device_node *gpu_clk_dn;
+ struct mali_gpu_clk_item *clk_item;
+ phandle dvfs_clk_hdl;
+ mali_dvfs_threshold_table *dvfs_tbl = NULL;
+ uint32_t *clk_sample = NULL;
+
+ struct property *prop;
+ const __be32 *p;
+ int length = 0, i = 0;
+ u32 u;
+
+ int ret = 0;
+ if (!gpu_dn) {
+ dev_notice(&pdev->dev, "gpu device node not right\n");
+ return -ENODEV;
+ }
+
+ ret = of_property_read_u32(gpu_dn,"num_of_pp",
+ &mpdata->cfg_pp);
+ if (ret) {
+ dev_notice(&pdev->dev, "set max pp to default 6\n");
+ mpdata->cfg_pp = 6;
+ }
+ mpdata->scale_info.maxpp = mpdata->cfg_pp;
+ mpdata->maxpp_sysfs = mpdata->cfg_pp;
+ _dev_info(&pdev->dev, "max pp is %d\n", mpdata->scale_info.maxpp);
+
+ ret = of_property_read_u32(gpu_dn,"min_pp",
+ &mpdata->cfg_min_pp);
+ if (ret) {
+ dev_notice(&pdev->dev, "set min pp to default 1\n");
+ mpdata->cfg_min_pp = 1;
+ }
+ mpdata->scale_info.minpp = mpdata->cfg_min_pp;
+ _dev_info(&pdev->dev, "min pp is %d\n", mpdata->scale_info.minpp);
+
+ ret = of_property_read_u32(gpu_dn,"min_clk",
+ &mpdata->cfg_min_clock);
+ if (ret) {
+ dev_notice(&pdev->dev, "set min clk default to 0\n");
+ mpdata->cfg_min_clock = 0;
+ }
+ mpdata->scale_info.minclk = mpdata->cfg_min_clock;
+ _dev_info(&pdev->dev, "min clk is %d\n", mpdata->scale_info.minclk);
+
+ mpdata->reg_base_hiubus = of_iomap(gpu_dn, 1);
+ _dev_info(&pdev->dev, "hiu io source 0x%p\n", mpdata->reg_base_hiubus);
+
+ mpdata->reg_base_aobus = of_iomap(gpu_dn, 2);
+ _dev_info(&pdev->dev, "hiu io source 0x%p\n", mpdata->reg_base_aobus);
+
+ ret = of_property_read_u32(gpu_dn,"sc_mpp",
+ &mpdata->sc_mpp);
+ if (ret) {
+ dev_notice(&pdev->dev, "set pp used most of time default to %d\n", mpdata->cfg_pp);
+ mpdata->sc_mpp = mpdata->cfg_pp;
+ }
+ _dev_info(&pdev->dev, "num of pp used most of time %d\n", mpdata->sc_mpp);
+
+ of_get_property(gpu_dn, "tbl", &length);
+
+ length = length /sizeof(u32);
+ _dev_info(&pdev->dev, "clock dvfs cfg table size is %d\n", length);
+
+ mpdata->dvfs_table = devm_kzalloc(&pdev->dev,
+ sizeof(struct mali_dvfs_threshold_table)*length,
+ GFP_KERNEL);
+ dvfs_tbl = mpdata->dvfs_table;
+ if (mpdata->dvfs_table == NULL) {
+ dev_err(&pdev->dev, "failed to alloc dvfs table\n");
+ return -ENOMEM;
+ }
+ mpdata->clk_sample = devm_kzalloc(&pdev->dev, sizeof(u32)*length, GFP_KERNEL);
+ if (mpdata->clk_sample == NULL) {
+ dev_err(&pdev->dev, "failed to alloc clk_sample table\n");
+ return -ENOMEM;
+ }
+ clk_sample = mpdata->clk_sample;
+///////////
+ mpdata->clk_items = devm_kzalloc(&pdev->dev, sizeof(struct mali_gpu_clk_item) * length, GFP_KERNEL);
+ if (mpdata->clk_items == NULL) {
+ dev_err(&pdev->dev, "failed to alloc clk_item table\n");
+ return -ENOMEM;
+ }
+ clk_item = mpdata->clk_items;
+//
+ of_property_for_each_u32(gpu_dn, "tbl", prop, p, u) {
+ dvfs_clk_hdl = (phandle) u;
+ gpu_clk_dn = of_find_node_by_phandle(dvfs_clk_hdl);
+ ret = of_property_read_u32(gpu_clk_dn,"clk_freq", &dvfs_tbl->clk_freq);
+ if (ret) {
+ dev_notice(&pdev->dev, "read clk_freq failed\n");
+ }
+#if 0
+#ifdef MESON_CPU_VERSION_OPS
+ if (is_meson_gxbbm_cpu()) {
+ if (dvfs_tbl->clk_freq >= GXBBM_MAX_GPU_FREQ)
+ continue;
+ }
+#endif
+#endif
+#if 0
+ ret = of_property_read_string(gpu_clk_dn,"clk_parent",
+ &dvfs_tbl->clk_parent);
+ if (ret) {
+ dev_notice(&pdev->dev, "read clk_parent failed\n");
+ }
+ dvfs_tbl->clkp_handle = devm_clk_get(&pdev->dev, dvfs_tbl->clk_parent);
+ if (IS_ERR(dvfs_tbl->clkp_handle)) {
+ dev_notice(&pdev->dev, "failed to get %s's clock pointer\n", dvfs_tbl->clk_parent);
+ }
+ ret = of_property_read_u32(gpu_clk_dn,"clkp_freq", &dvfs_tbl->clkp_freq);
+ if (ret) {
+ dev_notice(&pdev->dev, "read clk_parent freq failed\n");
+ }
+#endif
+ ret = of_property_read_u32(gpu_clk_dn,"voltage", &dvfs_tbl->voltage);
+ if (ret) {
+ dev_notice(&pdev->dev, "read voltage failed\n");
+ }
+ ret = of_property_read_u32(gpu_clk_dn,"keep_count", &dvfs_tbl->keep_count);
+ if (ret) {
+ dev_notice(&pdev->dev, "read keep_count failed\n");
+ }
+ //downthreshold and upthreshold shall be u32
+ ret = of_property_read_u32_array(gpu_clk_dn,"threshold",
+ &dvfs_tbl->downthreshold, 2);
+ if (ret) {
+ dev_notice(&pdev->dev, "read threshold failed\n");
+ }
+ dvfs_tbl->freq_index = i;
+ clk_item->clock = dvfs_tbl->clk_freq / 1000000;
+ clk_item->vol = dvfs_tbl->voltage;
+
+ *clk_sample = dvfs_tbl->clk_freq / 1000000;
+
+ dvfs_tbl ++;
+ clk_item ++;
+ clk_sample ++;
+ i++;
+ mpdata->dvfs_table_size ++;
+ }
+
+ ret = of_property_read_u32(gpu_dn,"max_clk",
+ &mpdata->cfg_clock);
+ if (ret) {
+ dev_notice(&pdev->dev, "max clk set %d\n", mpdata->dvfs_table_size-2);
+ mpdata->cfg_clock = mpdata->dvfs_table_size-2;
+ }
+
+ mpdata->cfg_clock_bkup = mpdata->cfg_clock;
+ mpdata->maxclk_sysfs = mpdata->cfg_clock;
+ mpdata->scale_info.maxclk = mpdata->cfg_clock;
+ _dev_info(&pdev->dev, "max clk is %d\n", mpdata->scale_info.maxclk);
+
+ ret = of_property_read_u32(gpu_dn,"turbo_clk",
+ &mpdata->turbo_clock);
+ if (ret) {
+ dev_notice(&pdev->dev, "turbo clk set to %d\n", mpdata->dvfs_table_size-1);
+ mpdata->turbo_clock = mpdata->dvfs_table_size-1;
+ }
+ _dev_info(&pdev->dev, "turbo clk is %d\n", mpdata->turbo_clock);
+
+ ret = of_property_read_u32(gpu_dn,"def_clk",
+ &mpdata->def_clock);
+ if (ret) {
+ dev_notice(&pdev->dev, "default clk set to %d\n", mpdata->dvfs_table_size/2-1);
+ mpdata->def_clock = mpdata->dvfs_table_size/2 - 1;
+ }
+ _dev_info(&pdev->dev, "default clk is %d\n", mpdata->def_clock);
+
+ dvfs_tbl = mpdata->dvfs_table;
+ clk_sample = mpdata->clk_sample;
+ for (i = 0; i< mpdata->dvfs_table_size; i++) {
+ _dev_info(&pdev->dev, "====================%d====================\n"
+ "clk_freq=%10d, clk_parent=%9s, voltage=%d, keep_count=%d, threshod=<%d %d>, clk_sample=%d\n",
+ i,
+ dvfs_tbl->clk_freq, dvfs_tbl->clk_parent,
+ dvfs_tbl->voltage, dvfs_tbl->keep_count,
+ dvfs_tbl->downthreshold, dvfs_tbl->upthreshold, *clk_sample);
+ dvfs_tbl ++;
+ clk_sample ++;
+ }
+ _dev_info(&pdev->dev, "clock dvfs table size is %d\n", mpdata->dvfs_table_size);
+
+ mpdata->clk_mali = devm_clk_get(&pdev->dev, "gpu_mux");
+#if 0
+ mpdata->clk_mali_0 = devm_clk_get(&pdev->dev, "clk_mali_0");
+ mpdata->clk_mali_1 = devm_clk_get(&pdev->dev, "clk_mali_1");
+#endif
+ if (IS_ERR(mpdata->clk_mali)) {
+ dev_err(&pdev->dev, "failed to get clock pointer\n");
+ return -EFAULT;
+ }
+
+ pmali_plat = mpdata;
+ mpdata->pdev = pdev;
+ return 0;
+}
+
+#endif
--- /dev/null
+#ifndef __MALI_CLOCK_H__
+#define __MALI_CLOCK_H__
+#include <linux/version.h>
+#include <linux/pm.h>
+#include <linux/io.h>
+#include <linux/types.h>
+#include <linux/of.h>
+
+#include <asm/io.h>
+#include <linux/clk.h>
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 29))
+#include <linux/amlogic/iomap.h>
+#endif
+
+#ifndef HHI_MALI_CLK_CNTL
+#define HHI_MALI_CLK_CNTL 0x6C
+#define mplt_read(r) readl((pmali_plat->reg_base_hiubus) + ((r)<<2))
+#define mplt_write(r, v) writel((v), ((pmali_plat->reg_base_hiubus) + ((r)<<2)))
+#define mplt_setbits(r, m) mplt_write((r), (mplt_read(r) | (m)));
+#define mplt_clrbits(r, m) mplt_write((r), (mplt_read(r) & (~(m))));
+#endif
+
+//extern int mali_clock_init(struct platform_device *dev);
+int mali_clock_init_clk_tree(struct platform_device *pdev);
+
+typedef int (*critical_t)(size_t param);
+int mali_clock_critical(critical_t critical, size_t param);
+
+int mali_clock_init(mali_plat_info_t*);
+int mali_clock_set(unsigned int index);
+void disable_clock(void);
+void enable_clock(void);
+u32 get_mali_freq(u32 idx);
+void set_str_src(u32 data);
+int mali_dt_info(struct platform_device *pdev,
+ struct mali_plat_info_t *mpdata);
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2013 ARM Limited. All rights reserved.
+ *
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ *
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+/**
+ * @file arm_core_scaling.c
+ * Example core scaling policy.
+ */
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/workqueue.h>
+#include <linux/mali/mali_utgard.h>
+#include <mali_kernel_common.h>
+#include <mali_osk_profiling.h>
+#include <linux/time.h>
+
+//#include <linux/amlogic/amports/gp_pll.h>
+#include "meson_main2.h"
+
+
+static int currentStep;
+static int scaling_mode = MALI_PP_FS_SCALING;
+//static int scaling_mode = MALI_SCALING_DISABLE;
+//static int scaling_mode = MALI_PP_SCALING;
+
+//static struct gp_pll_user_handle_s *gp_pll_user_gpu;
+//static int is_gp_pll_get;
+//static int is_gp_pll_put;
+
+static unsigned scaling_dbg_level = 0;
+module_param(scaling_dbg_level, uint, 0644);
+MODULE_PARM_DESC(scaling_dbg_level , "scaling debug level");
+
+static mali_plat_info_t* pmali_plat = NULL;
+static struct workqueue_struct *mali_scaling_wq = NULL;
+//static DEFINE_SPINLOCK(lock);
+
+static int cur_gpu_clk_index = 0;
+static int exec_gpu_clk_index = 0;
+#define scalingdbg(level, fmt, arg...) \
+ do { \
+ if (scaling_dbg_level >= (level)) \
+ printk(fmt , ## arg); \
+ } while (0)
+
+struct mali_gpu_clock meson_gpu_clk_info = {
+ .item = NULL,
+ .num_of_steps = 0,
+};
+
+u32 revise_set_clk(u32 val, u32 flush)
+{
+ u32 ret = 0;
+ return ret;
+}
+
+void get_mali_rt_clkpp(u32* clk, u32* pp)
+{
+}
+
+u32 set_mali_rt_clkpp(u32 clk, u32 pp, u32 flush)
+{
+ u32 ret = 0;
+ return ret;
+}
+
+void revise_mali_rt(void)
+{
+}
+
+static void do_scaling(struct work_struct *work)
+{
+ //unsigned long flags;
+ mali_plat_info_t *pinfo = container_of(work, struct mali_plat_info_t, wq_work);
+
+ *pinfo = *pinfo;
+ //mali_dev_pause();
+ //spin_lock_irqsave(&lock, flags);
+ mali_clock_set(exec_gpu_clk_index);
+ cur_gpu_clk_index = exec_gpu_clk_index;
+ //spin_unlock_irqrestore(&lock, flags);
+ //mali_dev_resume();
+}
+void flush_scaling_job(void)
+{
+ if (mali_scaling_wq == NULL) return;
+
+ flush_workqueue(mali_scaling_wq);
+ printk("%s, %d\n", __func__, __LINE__);
+}
+
+
+int mali_core_scaling_init(mali_plat_info_t *mali_plat)
+{
+ pmali_plat = mali_plat;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)
+ mali_scaling_wq = alloc_workqueue("gpu_scaling_wq", WQ_HIGHPRI | WQ_UNBOUND, 0);
+#else
+ mali_scaling_wq = create_workqueue("gpu_scaling_wq");
+#endif
+ INIT_WORK(&pmali_plat->wq_work, do_scaling);
+ if (mali_scaling_wq == NULL) printk("Unable to create gpu scaling workqueue\n");
+
+ meson_gpu_clk_info.num_of_steps = pmali_plat->scale_info.maxclk;
+
+ return 0;
+}
+
+void mali_core_scaling_term(void)
+{
+ flush_scaling_job();
+ destroy_workqueue(mali_scaling_wq);
+ mali_scaling_wq = NULL;
+}
+
+void mali_pp_scaling_update(struct mali_gpu_utilization_data *data)
+{
+}
+
+void mali_pp_fs_scaling_update(struct mali_gpu_utilization_data *data)
+{
+}
+
+u32 get_mali_schel_mode(void)
+{
+ return scaling_mode;
+}
+
+void set_mali_schel_mode(u32 mode)
+{
+ scaling_mode = mode;
+ if (scaling_mode == MALI_TURBO_MODE) {
+ printk ("turbo mode\n");
+ pmali_plat->limit_on = 0;
+ meson_gpu_clk_info.num_of_steps = pmali_plat->turbo_clock;
+ } else {
+ printk ("not turbo mode\n");
+ pmali_plat->limit_on = 1;
+ meson_gpu_clk_info.num_of_steps = pmali_plat->scale_info.maxclk;
+ }
+
+ printk("total_enable_steps = %d\n", meson_gpu_clk_info.num_of_steps);
+}
+
+u32 get_current_frequency(void)
+{
+ return get_mali_freq(currentStep);
+}
+
+void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data)
+{
+}
+
+void mali_dev_restore(void)
+{
+ //TO add this
+ //mali_perf_set_num_pp_cores(num_cores_enabled);
+ if (pmali_plat && pmali_plat->pdev) {
+ mali_clock_init_clk_tree(pmali_plat->pdev);
+ } else {
+ printk("error: init clock failed, pmali_plat=%p, pmali_plat->pdev=%p\n",
+ pmali_plat, pmali_plat == NULL ? NULL: pmali_plat->pdev);
+ }
+}
+
+/* Function that platfrom report it's clock info which driver can set, needed when CONFIG_MALI_DVFS enabled */
+static void meson_platform_get_clock_info(struct mali_gpu_clock **data) {
+ if (pmali_plat) {
+ meson_gpu_clk_info.item = pmali_plat->clk_items;
+ meson_gpu_clk_info.num_of_steps = pmali_plat->scale_info.maxclk;
+ printk("get clock info\n");
+ } else {
+ printk("error pmali_plat is null");
+ }
+ *data = &meson_gpu_clk_info;
+}
+
+/* Function that get the current clock info, needed when CONFIG_MALI_DVFS enabled */
+static int meson_platform_get_freq(void) {
+ scalingdbg(1, "cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
+ //dynamically changed the num of steps;
+ return cur_gpu_clk_index;
+}
+
+/* Fuction that platform callback for freq setting, needed when CONFIG_MALI_DVFS enabled */
+static int meson_platform_set_freq(int setting_clock_step) {
+
+ if (exec_gpu_clk_index == setting_clock_step) {
+ return 0;
+ }
+
+ queue_work(mali_scaling_wq, &pmali_plat->wq_work);
+ exec_gpu_clk_index = setting_clock_step;
+ scalingdbg(1, "set cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
+ return 0;
+}
+
+int mali_meson_get_gpu_data(struct mali_gpu_device_data *mgpu_data)
+{
+ mgpu_data->get_clock_info = meson_platform_get_clock_info,
+ mgpu_data->get_freq = meson_platform_get_freq,
+ mgpu_data->set_freq = meson_platform_set_freq,
+ mgpu_data->utilization_callback = NULL;
+ return 0;
+}
--- /dev/null
+/*
+ * mali_platform.h
+ *
+ * Created on: Nov 8, 2013
+ * Author: amlogic
+ */
+
+#include <linux/kernel.h>
+#ifndef MALI_PLATFORM_H_
+#define MALI_PLATFORM_H_
+
+extern u32 mali_gp_reset_fail;
+extern u32 mali_core_timeout;
+
+#endif /* MALI_PLATFORM_H_ */
--- /dev/null
+#include <linux/platform_device.h>
+#include <linux/version.h>
+#include <linux/pm.h>
+#include <linux/of.h>
+#include <linux/module.h> /* kernel module definitions */
+#include <linux/ioport.h> /* request_mem_region */
+#include <linux/slab.h>
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
+#include <mach/register.h>
+#include <mach/irqs.h>
+#include <mach/io.h>
+#endif
+#include "meson_main.h"
+#include <common/mali_kernel_common.h>
+#include <common/mali_osk_profiling.h>
+#include <common/mali_pmu.h>
+#include <linux/mali/mali_utgard.h>
+
+static int mali_os_suspend(struct device *device)
+{
+ int ret = 0;
+
+ MALI_DEBUG_PRINT(4, ("mali_os_suspend() called\n"));
+ ret = mali_deep_suspend(device);
+
+ return ret;
+}
+
+static int mali_os_resume(struct device *device)
+{
+ int ret = 0;
+
+ MALI_DEBUG_PRINT(4, ("mali_os_resume() called\n"));
+
+ ret = mali_deep_resume(device);
+
+ return ret;
+}
+
+static int mali_os_freeze(struct device *device)
+{
+ int ret = 0;
+
+ MALI_DEBUG_PRINT(4, ("mali_os_freeze() called\n"));
+
+ mali_dev_freeze();
+
+ if (NULL != device->driver &&
+ NULL != device->driver->pm &&
+ NULL != device->driver->pm->freeze)
+ {
+ /* Need to notify Mali driver about this event */
+ ret = device->driver->pm->freeze(device);
+ }
+
+ return ret;
+}
+//copy from r4p1 linux/mali_pmu_power_up_down.c
+#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
+static int mali_pmu_powerup(void)
+{
+ struct mali_pmu_core *pmu = mali_pmu_get_global_pmu_core();
+
+ MALI_DEBUG_PRINT(5, ("Mali PMU: Power up\n"));
+
+ MALI_DEBUG_ASSERT_POINTER(pmu);
+ if (NULL == pmu) {
+ return -ENXIO;
+ }
+
+ mali_pmu_power_up_all(pmu);
+
+ return 0;
+}
+#endif
+
+static int mali_os_thaw(struct device *device)
+{
+ int ret = 0;
+
+ MALI_DEBUG_PRINT(4, ("mali_os_thaw() called\n"));
+#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
+ enable_clock();
+ mali_pmu_powerup();
+#endif
+
+ if (NULL != device->driver &&
+ NULL != device->driver->pm &&
+ NULL != device->driver->pm->thaw)
+ {
+ /* Need to notify Mali driver about this event */
+ ret = device->driver->pm->thaw(device);
+ }
+
+ return ret;
+}
+
+static int mali_os_restore(struct device *device)
+{
+ MALI_DEBUG_PRINT(4, ("mali_os_thaw() called\n"));
+#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
+ mali_dev_restore();
+#endif
+ return mali_os_resume(device);
+}
+
+#ifdef CONFIG_PM_RUNTIME
+#if 0
+static int mali_runtime_suspend(struct device *device)
+{
+ int ret = 0;
+
+ MALI_DEBUG_PRINT(4, ("mali_runtime_suspend() called\n"));
+ ret = mali_light_suspend(device);
+
+ return ret;
+}
+
+static int mali_runtime_resume(struct device *device)
+{
+ int ret = 0;
+
+ MALI_DEBUG_PRINT(4, ("mali_run time_resume() called\n"));
+ ret = mali_light_resume(device);
+
+ return ret;
+}
+
+static int mali_runtime_idle(struct device *device)
+{
+ MALI_DEBUG_PRINT(4, ("mali_runtime_idle() called\n"));
+
+ if (NULL != device->driver &&
+ NULL != device->driver->pm &&
+ NULL != device->driver->pm->runtime_idle)
+ {
+ /* Need to notify Mali driver about this event */
+ int ret = device->driver->pm->runtime_idle(device);
+ if (0 != ret)
+ {
+ return ret;
+ }
+ }
+
+ pm_runtime_suspend(device);
+
+ return 0;
+}
+#endif
+#endif
+
+static struct dev_pm_ops mali_gpu_device_type_pm_ops =
+{
+ .suspend = mali_os_suspend,
+ .resume = mali_os_resume,
+ .freeze = mali_os_freeze,
+ .thaw = mali_os_thaw,
+ .restore = mali_os_restore,
+#if 0//def CONFIG_PM_RUNTIME
+ .runtime_suspend = mali_runtime_suspend,
+ .runtime_resume = mali_runtime_resume,
+ .runtime_idle = mali_runtime_idle,
+#endif
+};
+
+struct device_type mali_pm_device =
+{
+ .pm = &mali_gpu_device_type_pm_ops,
+};
--- /dev/null
+/*
+ * Copyright (C) 2013 ARM Limited. All rights reserved.
+ *
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ *
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+/**
+ * @file arm_core_scaling.h
+ * Example core scaling policy.
+ */
+
+#ifndef __ARM_CORE_SCALING_H__
+#define __ARM_CORE_SCALING_H__
+
+#include <linux/types.h>
+#include <linux/workqueue.h>
+#include <linux/clk-provider.h>
+#include <linux/clk.h>
+
+enum mali_scale_mode_t {
+ MALI_PP_SCALING = 0,
+ MALI_PP_FS_SCALING,
+ MALI_SCALING_DISABLE,
+ MALI_TURBO_MODE,
+ MALI_SCALING_MODE_MAX
+};
+
+typedef struct mali_dvfs_threshold_table {
+ uint32_t freq_index;
+ uint32_t voltage;
+ uint32_t keep_count;
+ uint32_t downthreshold;
+ uint32_t upthreshold;
+ uint32_t clk_freq;
+ const char *clk_parent;
+ struct clk *clkp_handle;
+ uint32_t clkp_freq;
+} mali_dvfs_threshold_table;
+
+/**
+ * restrictions on frequency and number of pp.
+ */
+typedef struct mali_scale_info_t {
+ u32 minpp;
+ u32 maxpp;
+ u32 minclk;
+ u32 maxclk;
+} mali_scale_info_t;
+
+/**
+ * Platform spesific data for meson chips.
+ */
+typedef struct mali_plat_info_t {
+ u32 cfg_pp; /* number of pp. */
+ u32 cfg_min_pp;
+ u32 turbo_clock; /* reserved clock src. */
+ u32 def_clock; /* gpu clock used most of time.*/
+ u32 cfg_clock; /* max clock could be used.*/
+ u32 cfg_clock_bkup; /* same as cfg_clock, for backup. */
+ u32 cfg_min_clock;
+
+ u32 sc_mpp; /* number of pp used most of time.*/
+ u32 bst_gpu; /* threshold for boosting gpu. */
+ u32 bst_pp; /* threshold for boosting PP. */
+
+ u32 *clk;
+ u32 *clk_sample;
+ u32 clk_len;
+ u32 have_switch; /* have clock gate switch or not. */
+
+ mali_dvfs_threshold_table *dvfs_table;
+ struct mali_gpu_clk_item *clk_items;
+ u32 dvfs_table_size;
+
+ mali_scale_info_t scale_info;
+ u32 maxclk_sysfs;
+ u32 maxpp_sysfs;
+
+ /* set upper limit of pp or frequency, for THERMAL thermal or band width saving.*/
+ u32 limit_on;
+
+ /* for boost up gpu by user. */
+ void (*plat_preheat)(void);
+
+ struct platform_device *pdev;
+ void __iomem *reg_base_hiubus;
+ void __iomem *reg_base_aobus;
+ struct work_struct wq_work;
+ struct clk *clk_mali;
+ struct clk *clk_mali_0;
+ struct clk *clk_mali_1;
+} mali_plat_info_t;
+mali_plat_info_t* get_mali_plat_data(void);
+
+/**
+ * Initialize core scaling policy.
+ *
+ * @note The core scaling policy will assume that all PP cores are on initially.
+ *
+ * @param num_pp_cores Total number of PP cores.
+ */
+int mali_core_scaling_init(mali_plat_info_t*);
+
+/**
+ * Terminate core scaling policy.
+ */
+void mali_core_scaling_term(void);
+
+/**
+ * cancel and flush scaling job queue.
+ */
+void flush_scaling_job(void);
+
+/* get current state(pp, clk). */
+void get_mali_rt_clkpp(u32* clk, u32* pp);
+u32 set_mali_rt_clkpp(u32 clk, u32 pp, u32 flush);
+void revise_mali_rt(void);
+/* get max gpu clk level of this chip*/
+int get_gpu_max_clk_level(void);
+
+/* get or set the scale mode. */
+u32 get_mali_schel_mode(void);
+void set_mali_schel_mode(u32 mode);
+
+/* for frequency reporter in DS-5 streamline. */
+u32 get_current_frequency(void);
+void mali_dev_freeze(void);
+void mali_dev_restore(void);
+
+extern int mali_pm_statue;
+#endif /* __ARM_CORE_SCALING_H__ */
--- /dev/null
+/*
+ * mali_platform.h
+ *
+ * Created on: Nov 8, 2013
+ * Author: amlogic
+ */
+
+#ifndef MESON_MAIN_H_
+#define MESON_MAIN_H_
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#ifdef CONFIG_PM_RUNTIME
+#include <linux/pm_runtime.h>
+#endif
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
+#include <mach/cpu.h>
+#endif
+
+#include "mali_scaling.h"
+#include "mali_clock.h"
+
+extern struct device_type mali_pm_device;
+extern int mali_pm_statue;
+
+u32 set_max_mali_freq(u32 idx);
+u32 get_max_mali_freq(void);
+
+int mali_meson_init_start(struct platform_device* ptr_plt_dev);
+int mali_meson_init_finish(struct platform_device* ptr_plt_dev);
+int mali_meson_uninit(struct platform_device* ptr_plt_dev);
+int mali_light_suspend(struct device *device);
+int mali_light_resume(struct device *device);
+int mali_deep_suspend(struct device *device);
+int mali_deep_resume(struct device *device);
+
+#endif /* MESON_MAIN_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2010, 2012-2014 Amlogic Limited. All rights reserved.
+ *
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ *
+ */
+
+/**
+ * @file mali_platform.c
+ * Platform specific Mali driver functions for:
+ * meson8m2 and the newer chip
+ */
+#include <linux/platform_device.h>
+#include <linux/version.h>
+#include <linux/pm.h>
+#ifdef CONFIG_PM_RUNTIME
+#include <linux/pm_runtime.h>
+#endif
+#include <asm/io.h>
+#include <linux/mali/mali_utgard.h>
+#include "mali_kernel_common.h"
+#include <linux/dma-mapping.h>
+#include <linux/moduleparam.h>
+
+#include "mali_executor.h"
+#include "mali_scaling.h"
+#include "mali_clock.h"
+#include "meson_main2.h"
+
+int mali_pm_statue = 0;
+extern void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data);
+
+u32 mali_gp_reset_fail = 0;
+module_param(mali_gp_reset_fail, int, S_IRUSR | S_IWUSR | S_IWGRP | S_IRGRP | S_IROTH); /* rw-rw-r-- */
+MODULE_PARM_DESC(mali_gp_reset_fail, "times of failed to reset GP");
+u32 mali_core_timeout = 0;
+module_param(mali_core_timeout, int, S_IRUSR | S_IWUSR | S_IWGRP | S_IRGRP | S_IROTH); /* rw-rw-r-- */
+MODULE_PARM_DESC(mali_core_timeout, "timeout of failed to reset GP");
+
+static struct mali_gpu_device_data mali_gpu_data = {
+
+#if defined(CONFIG_ARCH_REALVIEW)
+ .dedicated_mem_start = 0x80000000, /* Physical start address (use 0xD0000000 for old indirect setup) */
+ .dedicated_mem_size = 0x10000000, /* 256MB */
+#endif
+#if defined(CONFIG_ARM64)
+ .fb_start = 0x5f000000,
+ .fb_size = 0x91000000,
+#else
+ .fb_start = 0xe0000000,
+ .fb_size = 0x01000000,
+#endif
+ .control_interval = 200, /* 1000ms */
+};
+
+int mali_platform_device_init(struct platform_device *device)
+{
+ int err = -1;
+
+ err = mali_meson_init_start(device);
+ if (0 != err) printk("mali init failed\n");
+ err = mali_meson_get_gpu_data(&mali_gpu_data);
+ if (0 != err) printk("mali get gpu data failed\n");
+
+ err = platform_device_add_data(device, &mali_gpu_data, sizeof(mali_gpu_data));
+
+ if (0 == err) {
+ device->dev.type = &mali_pm_device; /* We should probably use the pm_domain instead of type on newer kernels */
+#ifdef CONFIG_PM_RUNTIME
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
+ pm_runtime_set_autosuspend_delay(&device->dev, 1000);
+ pm_runtime_use_autosuspend(&device->dev);
+#endif
+ pm_runtime_enable(&device->dev);
+#endif
+ mali_meson_init_finish(device);
+ }
+
+ mali_gp_reset_fail = 0;
+ mali_core_timeout = 0;
+
+ return err;
+}
+
+int mali_platform_device_deinit(struct platform_device *device)
+{
+ MALI_IGNORE(device);
+
+ printk("%s, %d\n", __FILE__, __LINE__);
+ MALI_DEBUG_PRINT(4, ("mali_platform_device_deinit() called\n"));
+
+
+ mali_meson_uninit(device);
+
+ return 0;
+}
+
+#if 0
+static int param_set_core_scaling(const char *val, const struct kernel_param *kp)
+{
+ int ret = param_set_int(val, kp);
+ printk("%s, %d\n", __FILE__, __LINE__);
+
+ if (1 == mali_core_scaling_enable) {
+ mali_core_scaling_sync(mali_executor_get_num_cores_enabled());
+ }
+ return ret;
+}
+
+static struct kernel_param_ops param_ops_core_scaling = {
+ .set = param_set_core_scaling,
+ .get = param_get_int,
+};
+
+module_param_cb(mali_core_scaling_enable, ¶m_ops_core_scaling, &mali_core_scaling_enable, 0644);
+MODULE_PARM_DESC(mali_core_scaling_enable, "1 means to enable core scaling policy, 0 means to disable core scaling policy");
+#endif
--- /dev/null
+/*
+ * mali_platform.h
+ *
+ * Created on: Nov 8, 2013
+ * Author: amlogic
+ */
+
+#ifndef MESON_MAIN_H_
+#define MESON_MAIN_H_
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#ifdef CONFIG_PM_RUNTIME
+#include <linux/pm_runtime.h>
+#endif
+#include <linux/mali/mali_utgard.h>
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
+#include <mach/cpu.h>
+#endif
+
+#include "mali_scaling.h"
+#include "mali_clock.h"
+
+extern struct device_type mali_pm_device;
+extern int mali_pm_statue;
+
+u32 set_max_mali_freq(u32 idx);
+u32 get_max_mali_freq(void);
+
+int mali_meson_init_start(struct platform_device* ptr_plt_dev);
+int mali_meson_get_gpu_data(struct mali_gpu_device_data *mgpu_data);
+int mali_meson_init_finish(struct platform_device* ptr_plt_dev);
+int mali_meson_uninit(struct platform_device* ptr_plt_dev);
+int mali_light_suspend(struct device *device);
+int mali_light_resume(struct device *device);
+int mali_deep_suspend(struct device *device);
+int mali_deep_resume(struct device *device);
+
+#endif /* MESON_MAIN_H_ */
--- /dev/null
+/*******************************************************************
+ *
+ * Copyright C 2013 by Amlogic, Inc. All Rights Reserved.
+ *
+ * Description:
+ *
+ * Author: Amlogic Software
+ * Created: 2010/4/1 19:46
+ *
+ *******************************************************************/
+/* Standard Linux headers */
+#include <linux/platform_device.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/string.h>
+#include <linux/slab.h>
+#include <linux/list.h>
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
+#include <mach/io.h>
+#include <plat/io.h>
+#include <asm/io.h>
+#endif
+
+#include <linux/mali/mali_utgard.h>
+#include <common/mali_kernel_common.h>
+#include <common/mali_pmu.h>
+//#include "mali_pp_scheduler.h"
+#include "meson_main.h"
+
+#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
+static ssize_t domain_stat_read(struct class *class,
+ struct class_attribute *attr, char *buf)
+{
+ unsigned int val;
+ mali_plat_info_t* pmali_plat = get_mali_plat_data();
+
+ val = readl(pmali_plat->reg_base_aobus + 0xf0) & 0xff;
+ return sprintf(buf, "%x\n", val>>4);
+ return 0;
+}
+
+#define PREHEAT_CMD "preheat"
+#define PLL2_CMD "mpl2" /* mpl2 [11] or [0xxxxxxx] */
+#define SCMPP_CMD "scmpp" /* scmpp [number of pp your want in most of time]. */
+#define BSTGPU_CMD "bstgpu" /* bstgpu [0-256] */
+#define BSTPP_CMD "bstpp" /* bstpp [0-256] */
+#define LIMIT_CMD "lmt" /* lmt [0 or 1] */
+#define MAX_TOKEN 20
+#define FULL_UTILIZATION 256
+
+static ssize_t mpgpu_write(struct class *class,
+ struct class_attribute *attr, const char *buf, size_t count)
+{
+ char *pstart, *cprt = NULL;
+ u32 val = 0;
+ mali_plat_info_t* pmali_plat = get_mali_plat_data();
+
+ cprt = skip_spaces(buf);
+ pstart = strsep(&cprt," ");
+ if (strlen(pstart) < 1)
+ goto quit;
+
+ if (!strncmp(pstart, PREHEAT_CMD, MAX_TOKEN)) {
+ if (pmali_plat->plat_preheat) {
+ pmali_plat->plat_preheat();
+ }
+ } else if (!strncmp(pstart, PLL2_CMD, MAX_TOKEN)) {
+ int base = 10;
+ if ((strlen(cprt) > 2) && (cprt[0] == '0') &&
+ (cprt[1] == 'x' || cprt[1] == 'X'))
+ base = 16;
+ if (kstrtouint(cprt, base, &val) <0)
+ goto quit;
+ if (val < 11)
+ pmali_plat->cfg_clock = pmali_plat->cfg_clock_bkup;
+ else
+ pmali_plat->cfg_clock = pmali_plat->turbo_clock;
+ pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
+ set_str_src(val);
+ } else if (!strncmp(pstart, SCMPP_CMD, MAX_TOKEN)) {
+ if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
+ goto quit;
+ if ((val > 0) && (val < pmali_plat->cfg_pp)) {
+ pmali_plat->sc_mpp = val;
+ }
+ } else if (!strncmp(pstart, BSTGPU_CMD, MAX_TOKEN)) {
+ if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
+ goto quit;
+ if ((val > 0) && (val < FULL_UTILIZATION)) {
+ pmali_plat->bst_gpu = val;
+ }
+ } else if (!strncmp(pstart, BSTPP_CMD, MAX_TOKEN)) {
+ if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
+ goto quit;
+ if ((val > 0) && (val < FULL_UTILIZATION)) {
+ pmali_plat->bst_pp = val;
+ }
+ } else if (!strncmp(pstart, LIMIT_CMD, MAX_TOKEN)) {
+ if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
+ goto quit;
+
+ if (val < 2) {
+ pmali_plat->limit_on = val;
+ if (val == 0) {
+ pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
+ pmali_plat->scale_info.maxpp = pmali_plat->cfg_pp;
+ revise_mali_rt();
+ }
+ }
+ }
+quit:
+ return count;
+}
+
+static ssize_t scale_mode_read(struct class *class,
+ struct class_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", get_mali_schel_mode());
+}
+
+static ssize_t scale_mode_write(struct class *class,
+ struct class_attribute *attr, const char *buf, size_t count)
+{
+ int ret;
+ unsigned int val;
+
+ ret = kstrtouint(buf, 10, &val);
+ if (0 != ret)
+ {
+ return -EINVAL;
+ }
+
+ set_mali_schel_mode(val);
+
+ return count;
+}
+
+static ssize_t max_pp_read(struct class *class,
+ struct class_attribute *attr, char *buf)
+{
+ mali_plat_info_t* pmali_plat = get_mali_plat_data();
+ printk("maxpp:%d, maxpp_sysfs:%d, total=%d\n",
+ pmali_plat->scale_info.maxpp, pmali_plat->maxpp_sysfs,
+ pmali_plat->cfg_pp);
+ return sprintf(buf, "%d\n", pmali_plat->cfg_pp);
+}
+
+static ssize_t max_pp_write(struct class *class,
+ struct class_attribute *attr, const char *buf, size_t count)
+{
+ int ret;
+ unsigned int val;
+ mali_plat_info_t* pmali_plat;
+ mali_scale_info_t* pinfo;
+
+ pmali_plat = get_mali_plat_data();
+ pinfo = &pmali_plat->scale_info;
+
+ ret = kstrtouint(buf, 10, &val);
+ if ((0 != ret) || (val > pmali_plat->cfg_pp) || (val < pinfo->minpp))
+ return -EINVAL;
+
+ pmali_plat->maxpp_sysfs = val;
+ pinfo->maxpp = val;
+ revise_mali_rt();
+
+ return count;
+}
+
+static ssize_t min_pp_read(struct class *class,
+ struct class_attribute *attr, char *buf)
+{
+ mali_plat_info_t* pmali_plat = get_mali_plat_data();
+ return sprintf(buf, "%d\n", pmali_plat->scale_info.minpp);
+}
+
+static ssize_t min_pp_write(struct class *class,
+ struct class_attribute *attr, const char *buf, size_t count)
+{
+ int ret;
+ unsigned int val;
+ mali_plat_info_t* pmali_plat;
+ mali_scale_info_t* pinfo;
+
+ pmali_plat = get_mali_plat_data();
+ pinfo = &pmali_plat->scale_info;
+
+ ret = kstrtouint(buf, 10, &val);
+ if ((0 != ret) || (val > pinfo->maxpp) || (val < 1))
+ return -EINVAL;
+
+ pinfo->minpp = val;
+ revise_mali_rt();
+
+ return count;
+}
+
+static ssize_t max_freq_read(struct class *class,
+ struct class_attribute *attr, char *buf)
+{
+ mali_plat_info_t* pmali_plat = get_mali_plat_data();
+ printk("maxclk:%d, maxclk_sys:%d, max gpu level=%d\n",
+ pmali_plat->scale_info.maxclk, pmali_plat->maxclk_sysfs, get_gpu_max_clk_level());
+ return sprintf(buf, "%d\n", get_gpu_max_clk_level());
+}
+
+static ssize_t max_freq_write(struct class *class,
+ struct class_attribute *attr, const char *buf, size_t count)
+{
+ int ret;
+ unsigned int val;
+ mali_plat_info_t* pmali_plat;
+ mali_scale_info_t* pinfo;
+
+ pmali_plat = get_mali_plat_data();
+ pinfo = &pmali_plat->scale_info;
+
+ ret = kstrtouint(buf, 10, &val);
+ if ((0 != ret) || (val > pmali_plat->cfg_clock) || (val < pinfo->minclk))
+ return -EINVAL;
+
+ pmali_plat->maxclk_sysfs = val;
+ pinfo->maxclk = val;
+ revise_mali_rt();
+
+ return count;
+}
+
+static ssize_t min_freq_read(struct class *class,
+ struct class_attribute *attr, char *buf)
+{
+ mali_plat_info_t* pmali_plat = get_mali_plat_data();
+ return sprintf(buf, "%d\n", pmali_plat->scale_info.minclk);
+}
+
+static ssize_t min_freq_write(struct class *class,
+ struct class_attribute *attr, const char *buf, size_t count)
+{
+ int ret;
+ unsigned int val;
+ mali_plat_info_t* pmali_plat;
+ mali_scale_info_t* pinfo;
+
+ pmali_plat = get_mali_plat_data();
+ pinfo = &pmali_plat->scale_info;
+
+ ret = kstrtouint(buf, 10, &val);
+ if ((0 != ret) || (val > pinfo->maxclk))
+ return -EINVAL;
+
+ pinfo->minclk = val;
+ revise_mali_rt();
+
+ return count;
+}
+
+static ssize_t freq_read(struct class *class,
+ struct class_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", get_current_frequency());
+}
+
+static ssize_t freq_write(struct class *class,
+ struct class_attribute *attr, const char *buf, size_t count)
+{
+ int ret;
+ unsigned int val;
+ u32 clk, pp;
+ get_mali_rt_clkpp(&clk, &pp);
+
+ ret = kstrtouint(buf, 10, &val);
+ if (0 != ret)
+ return -EINVAL;
+
+ set_mali_rt_clkpp(val, pp, 1);
+
+ return count;
+}
+
+static ssize_t current_pp_read(struct class *class,
+ struct class_attribute *attr, char *buf)
+{
+ u32 clk, pp;
+ get_mali_rt_clkpp(&clk, &pp);
+ return sprintf(buf, "%d\n", pp);
+}
+
+static ssize_t current_pp_write(struct class *class,
+ struct class_attribute *attr, const char *buf, size_t count)
+{
+ int ret;
+ unsigned int val;
+ u32 clk, pp;
+
+ get_mali_rt_clkpp(&clk, &pp);
+ ret = kstrtouint(buf, 10, &val);
+ if (0 != ret)
+ {
+ return -EINVAL;
+ }
+
+ ret = kstrtouint(buf, 10, &val);
+ if (0 != ret)
+ return -EINVAL;
+
+ set_mali_rt_clkpp(clk, val, 1);
+
+ return count;
+}
+
+static struct class_attribute mali_class_attrs[] = {
+ __ATTR(domain_stat, 0644, domain_stat_read, NULL),
+ __ATTR(mpgpucmd, 0644, NULL, mpgpu_write),
+ __ATTR(scale_mode, 0644, scale_mode_read, scale_mode_write),
+ __ATTR(min_freq, 0644, min_freq_read, min_freq_write),
+ __ATTR(max_freq, 0644, max_freq_read, max_freq_write),
+ __ATTR(min_pp, 0644, min_pp_read, min_pp_write),
+ __ATTR(max_pp, 0644, max_pp_read, max_pp_write),
+ __ATTR(cur_freq, 0644, freq_read, freq_write),
+ __ATTR(cur_pp, 0644, current_pp_read, current_pp_write),
+};
+
+static struct class mpgpu_class = {
+ .name = "mpgpu",
+};
+#endif
+
+int mpgpu_class_init(void)
+{
+#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
+ int ret = 0;
+ int i;
+ int attr_num = ARRAY_SIZE(mali_class_attrs);
+
+ ret = class_register(&mpgpu_class);
+ if (ret) {
+ printk(KERN_ERR "%s: class_register failed\n", __func__);
+ return ret;
+ }
+ for (i = 0; i< attr_num; i++) {
+ ret = class_create_file(&mpgpu_class, &mali_class_attrs[i]);
+ if (ret) {
+ printk(KERN_ERR "%d ST: class item failed to register\n", i);
+ }
+ }
+ return ret;
+#else
+ return 0;
+#endif
+}
+
+void mpgpu_class_exit(void)
+{
+#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
+ class_unregister(&mpgpu_class);
+#endif
+}
+
--- /dev/null
+/*
+ * platform.c
+ *
+ * clock source setting and resource config
+ *
+ * Created on: Dec 4, 2013
+ * Author: amlogic
+ */
+
+#include <linux/platform_device.h>
+#include <linux/version.h>
+#include <linux/pm.h>
+#include <linux/of.h>
+#include <linux/module.h> /* kernel module definitions */
+#include <linux/ioport.h> /* request_mem_region */
+#include <linux/slab.h>
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
+#include <mach/register.h>
+#include <mach/irqs.h>
+#include <mach/io.h>
+#endif
+#include <asm/io.h>
+#include <linux/mali/mali_utgard.h>
+#ifdef CONFIG_GPU_THERMAL
+#include <linux/gpu_cooling.h>
+#include <linux/gpucore_cooling.h>
+#ifdef CONFIG_DEVFREQ_THERMAL
+#include <linux/amlogic/aml_thermal_hw.h>
+#include <common/mali_ukk.h>
+#endif
+#endif
+#include <common/mali_kernel_common.h>
+#include <common/mali_osk_profiling.h>
+#include <common/mali_pmu.h>
+
+#include "mali_scaling.h"
+#include "mali_clock.h"
+#include "meson_main.h"
+#include "mali_executor.h"
+
+/*
+ * For Meson 8 M2.
+ *
+ */
+static void mali_plat_preheat(void);
+static mali_plat_info_t mali_plat_data = {
+ .bst_gpu = 210, /* threshold for boosting gpu. */
+ .bst_pp = 160, /* threshold for boosting PP. */
+ .have_switch = 1,
+ .limit_on = 1,
+ .plat_preheat = mali_plat_preheat,
+};
+
+static void mali_plat_preheat(void)
+{
+#ifndef CONFIG_MALI_DVFS
+ u32 pre_fs;
+ u32 clk, pp;
+
+ if (get_mali_schel_mode() != MALI_PP_FS_SCALING)
+ return;
+
+ get_mali_rt_clkpp(&clk, &pp);
+ pre_fs = mali_plat_data.def_clock + 1;
+ if (clk < pre_fs)
+ clk = pre_fs;
+ if (pp < mali_plat_data.sc_mpp)
+ pp = mali_plat_data.sc_mpp;
+ set_mali_rt_clkpp(clk, pp, 1);
+#endif
+}
+
+mali_plat_info_t* get_mali_plat_data(void) {
+ return &mali_plat_data;
+}
+
+int get_mali_freq_level(int freq)
+{
+ int i = 0, level = -1;
+ int mali_freq_num;
+
+ if (freq < 0)
+ return level;
+
+ mali_freq_num = mali_plat_data.dvfs_table_size - 1;
+ if (freq < mali_plat_data.clk_sample[0])
+ level = mali_freq_num-1;
+ else if (freq >= mali_plat_data.clk_sample[mali_freq_num - 1])
+ level = 0;
+ else {
+ for (i=0; i<mali_freq_num - 1 ;i++) {
+ if (freq >= mali_plat_data.clk_sample[i] && freq < mali_plat_data.clk_sample[i + 1]) {
+ level = i;
+ level = mali_freq_num-level - 1;
+ break;
+ }
+ }
+ }
+ return level;
+}
+
+unsigned int get_mali_max_level(void)
+{
+ return mali_plat_data.dvfs_table_size - 1;
+}
+
+int get_gpu_max_clk_level(void)
+{
+ return mali_plat_data.cfg_clock;
+}
+
+#ifdef CONFIG_GPU_THERMAL
+static void set_limit_mali_freq(u32 idx)
+{
+ if (mali_plat_data.limit_on == 0)
+ return;
+ if (idx > mali_plat_data.turbo_clock || idx < mali_plat_data.scale_info.minclk)
+ return;
+ if (idx > mali_plat_data.maxclk_sysfs) {
+ printk("idx > max freq\n");
+ return;
+ }
+ mali_plat_data.scale_info.maxclk= idx;
+ revise_mali_rt();
+}
+
+static u32 get_limit_mali_freq(void)
+{
+ return mali_plat_data.scale_info.maxclk;
+}
+
+#ifdef CONFIG_DEVFREQ_THERMAL
+static u32 get_mali_utilization(void)
+{
+ return (_mali_ukk_utilization_pp() * 100) / 256;
+}
+#endif
+#endif
+
+#ifdef CONFIG_GPU_THERMAL
+static u32 set_limit_pp_num(u32 num)
+{
+ u32 ret = -1;
+ if (mali_plat_data.limit_on == 0)
+ goto quit;
+ if (num > mali_plat_data.cfg_pp ||
+ num < mali_plat_data.scale_info.minpp)
+ goto quit;
+
+ if (num > mali_plat_data.maxpp_sysfs) {
+ printk("pp > sysfs set pp\n");
+ goto quit;
+ }
+
+ mali_plat_data.scale_info.maxpp = num;
+ revise_mali_rt();
+ ret = 0;
+quit:
+ return ret;
+}
+#ifdef CONFIG_DEVFREQ_THERMAL
+static u32 mali_get_online_pp(void)
+{
+ unsigned int val;
+ mali_plat_info_t* pmali_plat = get_mali_plat_data();
+
+ val = readl(pmali_plat->reg_base_aobus + 0xf0) & 0xff;
+ if (val == 0x07) /* No pp is working */
+ return 0;
+
+ return mali_executor_get_num_cores_enabled();
+}
+#endif
+#endif
+
+void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data);
+int mali_meson_init_start(struct platform_device* ptr_plt_dev)
+{
+ dev_set_drvdata(&ptr_plt_dev->dev, &mali_plat_data);
+ mali_dt_info(ptr_plt_dev, &mali_plat_data);
+ mali_clock_init_clk_tree(ptr_plt_dev);
+ return 0;
+}
+
+int mali_meson_init_finish(struct platform_device* ptr_plt_dev)
+{
+ if (mali_core_scaling_init(&mali_plat_data) < 0)
+ return -1;
+ return 0;
+}
+
+int mali_meson_uninit(struct platform_device* ptr_plt_dev)
+{
+ mali_core_scaling_term();
+ return 0;
+}
+
+static int mali_cri_light_suspend(size_t param)
+{
+ int ret;
+ struct device *device;
+ struct mali_pmu_core *pmu;
+
+ ret = 0;
+ mali_pm_statue = 1;
+ device = (struct device *)param;
+ pmu = mali_pmu_get_global_pmu_core();
+
+ if (NULL != device->driver &&
+ NULL != device->driver->pm &&
+ NULL != device->driver->pm->runtime_suspend)
+ {
+ /* Need to notify Mali driver about this event */
+ ret = device->driver->pm->runtime_suspend(device);
+ }
+ mali_pmu_power_down_all(pmu);
+ return ret;
+}
+
+static int mali_cri_light_resume(size_t param)
+{
+ int ret;
+ struct device *device;
+ struct mali_pmu_core *pmu;
+
+ ret = 0;
+ device = (struct device *)param;
+ pmu = mali_pmu_get_global_pmu_core();
+
+ mali_pmu_power_up_all(pmu);
+ if (NULL != device->driver &&
+ NULL != device->driver->pm &&
+ NULL != device->driver->pm->runtime_resume)
+ {
+ /* Need to notify Mali driver about this event */
+ ret = device->driver->pm->runtime_resume(device);
+ }
+ mali_pm_statue = 0;
+ return ret;
+}
+
+static int mali_cri_deep_suspend(size_t param)
+{
+ int ret;
+ struct device *device;
+ struct mali_pmu_core *pmu;
+
+ ret = 0;
+ device = (struct device *)param;
+ pmu = mali_pmu_get_global_pmu_core();
+
+ if (NULL != device->driver &&
+ NULL != device->driver->pm &&
+ NULL != device->driver->pm->suspend)
+ {
+ /* Need to notify Mali driver about this event */
+ ret = device->driver->pm->suspend(device);
+ }
+ mali_pmu_power_down_all(pmu);
+ return ret;
+}
+
+static int mali_cri_deep_resume(size_t param)
+{
+ int ret;
+ struct device *device;
+ struct mali_pmu_core *pmu;
+
+ ret = 0;
+ device = (struct device *)param;
+ pmu = mali_pmu_get_global_pmu_core();
+
+ mali_pmu_power_up_all(pmu);
+ if (NULL != device->driver &&
+ NULL != device->driver->pm &&
+ NULL != device->driver->pm->resume)
+ {
+ /* Need to notify Mali driver about this event */
+ ret = device->driver->pm->resume(device);
+ }
+ return ret;
+
+}
+
+int mali_light_suspend(struct device *device)
+{
+ int ret = 0;
+#ifdef CONFIG_MALI400_PROFILING
+ _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
+ MALI_PROFILING_EVENT_CHANNEL_GPU |
+ MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
+ 0, 0, 0, 0, 0);
+#endif
+
+ flush_scaling_job();
+ /* clock scaling. Kasin..*/
+ ret = mali_clock_critical(mali_cri_light_suspend, (size_t)device);
+ disable_clock();
+ return ret;
+}
+
+int mali_light_resume(struct device *device)
+{
+ int ret = 0;
+ enable_clock();
+ ret = mali_clock_critical(mali_cri_light_resume, (size_t)device);
+#ifdef CONFIG_MALI400_PROFILING
+ _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
+ MALI_PROFILING_EVENT_CHANNEL_GPU |
+ MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
+ get_current_frequency(), 0, 0, 0, 0);
+#endif
+ return ret;
+}
+
+int mali_deep_suspend(struct device *device)
+{
+ int ret = 0;
+
+ mali_pm_statue = 1;
+ flush_scaling_job();
+
+
+ /* clock scaling off. Kasin... */
+ ret = mali_clock_critical(mali_cri_deep_suspend, (size_t)device);
+ disable_clock();
+ return ret;
+}
+
+int mali_deep_resume(struct device *device)
+{
+ int ret = 0;
+
+ /* clock scaling up. Kasin.. */
+ enable_clock();
+ ret = mali_clock_critical(mali_cri_deep_resume, (size_t)device);
+ mali_pm_statue = 0;
+ return ret;
+
+}
+
+void mali_post_init(void)
+{
+#ifdef CONFIG_GPU_THERMAL
+ int err;
+ struct gpufreq_cooling_device *gcdev = NULL;
+ struct gpucore_cooling_device *gccdev = NULL;
+
+ gcdev = gpufreq_cooling_alloc();
+ register_gpu_freq_info(get_current_frequency);
+ if (IS_ERR(gcdev))
+ printk("malloc gpu cooling buffer error!!\n");
+ else if (!gcdev)
+ printk("system does not enable thermal driver\n");
+ else {
+ gcdev->get_gpu_freq_level = get_mali_freq_level;
+ gcdev->get_gpu_max_level = get_mali_max_level;
+ gcdev->set_gpu_freq_idx = set_limit_mali_freq;
+ gcdev->get_gpu_current_max_level = get_limit_mali_freq;
+#ifdef CONFIG_DEVFREQ_THERMAL
+ gcdev->get_gpu_freq = get_mali_freq;
+ gcdev->get_gpu_loading = get_mali_utilization;
+ gcdev->get_online_pp = mali_get_online_pp;
+#endif
+ err = gpufreq_cooling_register(gcdev);
+#ifdef CONFIG_DEVFREQ_THERMAL
+ aml_thermal_min_update(gcdev->cool_dev);
+#endif
+ if (err < 0)
+ printk("register GPU cooling error\n");
+ printk("gpu cooling register okay with err=%d\n",err);
+ }
+
+ gccdev = gpucore_cooling_alloc();
+ if (IS_ERR(gccdev))
+ printk("malloc gpu core cooling buffer error!!\n");
+ else if (!gccdev)
+ printk("system does not enable thermal driver\n");
+ else {
+ gccdev->max_gpu_core_num=mali_plat_data.cfg_pp;
+ gccdev->set_max_pp_num=set_limit_pp_num;
+ err = (int)gpucore_cooling_register(gccdev);
+#ifdef CONFIG_DEVFREQ_THERMAL
+ aml_thermal_min_update(gccdev->cool_dev);
+#endif
+ if (err < 0)
+ printk("register GPU cooling error\n");
+ printk("gpu core cooling register okay with err=%d\n",err);
+ }
+#endif
+}
--- /dev/null
+/*
+ * Copyright (C) 2013 ARM Limited. All rights reserved.
+ *
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ *
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+/**
+ * @file arm_core_scaling.c
+ * Example core scaling policy.
+ */
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/workqueue.h>
+#include <linux/mali/mali_utgard.h>
+#include <mali_kernel_common.h>
+#include <mali_osk_profiling.h>
+
+#if AMLOGIC_GPU_USE_GPPLL
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 16)
+#include <linux/amlogic/amports/gp_pll.h>
+#else
+#include <linux/amlogic/media/clk/gp_pll.h>
+#endif
+#endif
+#define LOG_MALI_SCALING 1
+#include "meson_main2.h"
+#include "mali_clock.h"
+
+static int currentStep;
+#ifndef CONFIG_MALI_DVFS
+static int num_cores_enabled;
+static int lastStep;
+static struct work_struct wq_work;
+static mali_plat_info_t* pmali_plat = NULL;
+#endif
+static int scaling_mode = MALI_PP_FS_SCALING;
+//static int scaling_mode = MALI_SCALING_DISABLE;
+//static int scaling_mode = MALI_PP_SCALING;
+
+#if AMLOGIC_GPU_USE_GPPLL
+static struct gp_pll_user_handle_s *gp_pll_user_gpu;
+static int is_gp_pll_get;
+static int is_gp_pll_put;
+#endif
+
+static unsigned scaling_dbg_level = 0;
+module_param(scaling_dbg_level, uint, 0644);
+MODULE_PARM_DESC(scaling_dbg_level , "scaling debug level");
+
+#define scalingdbg(level, fmt, arg...) \
+ do { \
+ if (scaling_dbg_level >= (level)) \
+ printk(fmt , ## arg); \
+ } while (0)
+
+#ifndef CONFIG_MALI_DVFS
+static inline void mali_clk_exected(void)
+{
+ mali_dvfs_threshold_table * pdvfs = pmali_plat->dvfs_table;
+ uint32_t execStep = currentStep;
+#if AMLOGIC_GPU_USE_GPPLL
+ mali_dvfs_threshold_table *dvfs_tbl = &pmali_plat->dvfs_table[currentStep];
+#endif
+
+ //if (pdvfs[currentStep].freq_index == pdvfs[lastStep].freq_index) return;
+ if ((pdvfs[execStep].freq_index == pdvfs[lastStep].freq_index) ||
+ (pdvfs[execStep].clk_freq == pdvfs[lastStep].clk_freq)){
+ return;
+ }
+
+#if AMLOGIC_GPU_USE_GPPLL
+ if (0 == strcmp(dvfs_tbl->clk_parent, "gp0_pll")) {
+ gp_pll_request(gp_pll_user_gpu);
+ if (!is_gp_pll_get) {
+ //printk("not get pll\n");
+ execStep = currentStep - 1;
+ }
+ } else {
+ //not get the gp pll, do need put
+ is_gp_pll_get = 0;
+ is_gp_pll_put = 0;
+ gp_pll_release(gp_pll_user_gpu);
+ }
+#endif
+
+ //mali_dev_pause();
+ mali_clock_set(pdvfs[execStep].freq_index);
+ //mali_dev_resume();
+ lastStep = execStep;
+#if AMLOGIC_GPU_USE_GPPLL
+ if (is_gp_pll_put) {
+ //printk("release gp0 pll\n");
+ gp_pll_release(gp_pll_user_gpu);
+ gp_pll_request(gp_pll_user_gpu);
+ is_gp_pll_get = 0;
+ is_gp_pll_put = 0;
+ }
+#endif
+
+}
+#if AMLOGIC_GPU_USE_GPPLL
+static int gp_pll_user_cb_gpu(struct gp_pll_user_handle_s *user,
+ int event)
+{
+ if (event == GP_PLL_USER_EVENT_GRANT) {
+ //printk("granted\n");
+ is_gp_pll_get = 1;
+ is_gp_pll_put = 0;
+ schedule_work(&wq_work);
+ } else if (event == GP_PLL_USER_EVENT_YIELD) {
+ //printk("ask for yield\n");
+ is_gp_pll_get = 0;
+ is_gp_pll_put = 1;
+ schedule_work(&wq_work);
+ }
+
+ return 0;
+}
+#endif
+
+static void do_scaling(struct work_struct *work)
+{
+ mali_dvfs_threshold_table * pdvfs = pmali_plat->dvfs_table;
+ int err = mali_perf_set_num_pp_cores(num_cores_enabled);
+ scalingdbg(1, "set pp cores to %d\n", num_cores_enabled);
+ MALI_DEBUG_ASSERT(0 == err);
+ MALI_IGNORE(err);
+ scalingdbg(1, "pdvfs[%d].freq_index=%d, pdvfs[%d].freq_index=%d\n",
+ currentStep, pdvfs[currentStep].freq_index,
+ lastStep, pdvfs[lastStep].freq_index);
+ mali_clk_exected();
+#ifdef CONFIG_MALI400_PROFILING
+ _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
+ MALI_PROFILING_EVENT_CHANNEL_GPU |
+ MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
+ get_current_frequency(),
+ 0, 0, 0, 0);
+#endif
+}
+#endif
+
+u32 revise_set_clk(u32 val, u32 flush)
+{
+ u32 ret = 0;
+#ifndef CONFIG_MALI_DVFS
+ mali_scale_info_t* pinfo;
+
+ pinfo = &pmali_plat->scale_info;
+
+ if (val < pinfo->minclk)
+ val = pinfo->minclk;
+ else if (val > pinfo->maxclk)
+ val = pinfo->maxclk;
+
+ if (val != currentStep) {
+ currentStep = val;
+ if (flush)
+ schedule_work(&wq_work);
+ else
+ ret = 1;
+ }
+#endif
+ return ret;
+}
+
+void get_mali_rt_clkpp(u32* clk, u32* pp)
+{
+#ifndef CONFIG_MALI_DVFS
+ *clk = currentStep;
+ *pp = num_cores_enabled;
+#endif
+}
+
+u32 set_mali_rt_clkpp(u32 clk, u32 pp, u32 flush)
+{
+ u32 ret = 0;
+#ifndef CONFIG_MALI_DVFS
+ mali_scale_info_t* pinfo;
+ u32 flush_work = 0;
+
+ pinfo = &pmali_plat->scale_info;
+ if (clk < pinfo->minclk)
+ clk = pinfo->minclk;
+ else if (clk > pinfo->maxclk)
+ clk = pinfo->maxclk;
+
+ if (clk != currentStep) {
+ currentStep = clk;
+ if (flush)
+ flush_work++;
+ else
+ ret = 1;
+ }
+ if (pp < pinfo->minpp)
+ pp = pinfo->minpp;
+ else if (pp > pinfo->maxpp)
+ pp = pinfo->maxpp;
+
+ if (pp != num_cores_enabled) {
+ num_cores_enabled = pp;
+ if (flush)
+ flush_work++;
+ else
+ ret = 1;
+ }
+
+ if (flush_work)
+ schedule_work(&wq_work);
+#endif
+ return ret;
+}
+
+void revise_mali_rt(void)
+{
+#ifndef CONFIG_MALI_DVFS
+ set_mali_rt_clkpp(currentStep, num_cores_enabled, 1);
+#endif
+}
+
+void flush_scaling_job(void)
+{
+#ifndef CONFIG_MALI_DVFS
+ cancel_work_sync(&wq_work);
+#endif
+}
+
+#ifndef CONFIG_MALI_DVFS
+static u32 enable_one_core(void)
+{
+ scalingdbg(2, "meson: one more pp, curent has %d pp cores\n", num_cores_enabled + 1);
+ return set_mali_rt_clkpp(currentStep, num_cores_enabled + 1, 0);
+}
+
+static u32 disable_one_core(void)
+{
+ scalingdbg(2, "meson: disable one pp, current has %d pp cores\n", num_cores_enabled - 1);
+ return set_mali_rt_clkpp(currentStep, num_cores_enabled - 1, 0);
+}
+
+static u32 enable_max_num_cores(void)
+{
+ return set_mali_rt_clkpp(currentStep, pmali_plat->scale_info.maxpp, 0);
+}
+
+static u32 enable_pp_cores(u32 val)
+{
+ scalingdbg(2, "meson: enable %d pp cores\n", val);
+ return set_mali_rt_clkpp(currentStep, val, 0);
+}
+#endif
+
+int mali_core_scaling_init(mali_plat_info_t *mali_plat)
+{
+#ifndef CONFIG_MALI_DVFS
+ if (mali_plat == NULL) {
+ scalingdbg(2, " Mali platform data is NULL!!!\n");
+ return -1;
+ }
+
+ pmali_plat = mali_plat;
+ num_cores_enabled = pmali_plat->sc_mpp;
+#if AMLOGIC_GPU_USE_GPPLL
+ gp_pll_user_gpu = gp_pll_user_register("gpu", 1,
+ gp_pll_user_cb_gpu);
+ //not get the gp pll, do need put
+ is_gp_pll_get = 0;
+ is_gp_pll_put = 0;
+ if (gp_pll_user_gpu == NULL) printk("register gp pll user for gpu failed\n");
+#endif
+
+ currentStep = pmali_plat->def_clock;
+ lastStep = currentStep;
+ INIT_WORK(&wq_work, do_scaling);
+#endif
+ return 0;
+ /* NOTE: Mali is not fully initialized at this point. */
+}
+
+void mali_core_scaling_term(void)
+{
+#ifndef CONFIG_MALI_DVFS
+ flush_scheduled_work();
+#if AMLOGIC_GPU_USE_GPPLL
+ gp_pll_user_unregister(gp_pll_user_gpu);
+#endif
+#endif
+}
+
+#ifndef CONFIG_MALI_DVFS
+static u32 mali_threshold [] = {
+ 102, /* 40% */
+ 128, /* 50% */
+ 230, /* 90% */
+};
+#endif
+
+void mali_pp_scaling_update(struct mali_gpu_utilization_data *data)
+{
+#ifndef CONFIG_MALI_DVFS
+ int ret = 0;
+
+ if (mali_threshold[2] < data->utilization_pp)
+ ret = enable_max_num_cores();
+ else if (mali_threshold[1]< data->utilization_pp)
+ ret = enable_one_core();
+ else if (0 < data->utilization_pp)
+ ret = disable_one_core();
+ if (ret == 1)
+ schedule_work(&wq_work);
+#endif
+}
+
+#if LOG_MALI_SCALING
+void trace_utilization(struct mali_gpu_utilization_data *data, u32 current_idx, u32 next,
+ u32 current_pp, u32 next_pp)
+{
+ char direction;
+ if (next > current_idx)
+ direction = '>';
+ else if ((current_idx > pmali_plat->scale_info.minpp) && (next < current_idx))
+ direction = '<';
+ else
+ direction = '~';
+
+ scalingdbg(2, "[SCALING]%c (%3d-->%3d)@%3d{%3d - %3d}. pp:(%d-->%d)\n",
+ direction,
+ get_mali_freq(current_idx),
+ get_mali_freq(next),
+ data->utilization_gpu,
+ pmali_plat->dvfs_table[current_idx].downthreshold,
+ pmali_plat->dvfs_table[current_idx].upthreshold,
+ current_pp, next_pp);
+}
+#endif
+
+#ifndef CONFIG_MALI_DVFS
+static int mali_stay_count = 0;
+static void mali_decide_next_status(struct mali_gpu_utilization_data *data, int* next_fs_idx,
+ int* pp_change_flag)
+{
+ u32 utilization, mali_up_limit, decided_fs_idx;
+ u32 ld_left, ld_right;
+ u32 ld_up, ld_down;
+ u32 change_mode;
+
+ *pp_change_flag = 0;
+ change_mode = 0;
+ utilization = data->utilization_gpu;
+
+ scalingdbg(5, "line(%d), scaling_mode=%d, MALI_TURBO_MODE=%d, turbo=%d, maxclk=%d\n",
+ __LINE__, scaling_mode, MALI_TURBO_MODE,
+ pmali_plat->turbo_clock, pmali_plat->scale_info.maxclk);
+
+ mali_up_limit = (scaling_mode == MALI_TURBO_MODE) ?
+ pmali_plat->turbo_clock : pmali_plat->scale_info.maxclk;
+ decided_fs_idx = currentStep;
+
+ ld_up = pmali_plat->dvfs_table[currentStep].upthreshold;
+ ld_down = pmali_plat->dvfs_table[currentStep].downthreshold;
+
+ scalingdbg(2, "utilization=%d, ld_up=%d\n ", utilization, ld_up);
+ if (utilization >= ld_up) { /* go up */
+
+ scalingdbg(2, "currentStep=%d, mali_up_limit=%d\n ", currentStep, mali_up_limit);
+ if (currentStep < mali_up_limit) {
+ change_mode = 1;
+ if ((currentStep < pmali_plat->def_clock) && (utilization > pmali_plat->bst_gpu))
+ decided_fs_idx = pmali_plat->def_clock;
+ else
+ decided_fs_idx++;
+ }
+ if ((data->utilization_pp >= ld_up) &&
+ (num_cores_enabled < pmali_plat->scale_info.maxpp)) {
+ if ((num_cores_enabled < pmali_plat->sc_mpp) && (data->utilization_pp >= pmali_plat->bst_pp)) {
+ *pp_change_flag = 1;
+ change_mode = 1;
+ } else if (change_mode == 0) {
+ *pp_change_flag = 2;
+ change_mode = 1;
+ }
+ }
+#if LOG_MALI_SCALING
+ scalingdbg(2, "[nexting..] [LD:%d]-> FS[CRNT:%d LMT:%d NEXT:%d] PP[NUM:%d LMT:%d MD:%d][F:%d]\n",
+ data->utilization_pp, currentStep, mali_up_limit, decided_fs_idx,
+ num_cores_enabled, pmali_plat->scale_info.maxpp, *pp_change_flag, change_mode);
+#endif
+ } else if (utilization <= ld_down) { /* go down */
+ if (mali_stay_count > 0) {
+ *next_fs_idx = decided_fs_idx;
+ mali_stay_count--;
+ return;
+ }
+
+ if (num_cores_enabled > pmali_plat->sc_mpp) {
+ change_mode = 1;
+ if (data->utilization_pp <= ld_down) {
+ ld_left = data->utilization_pp * num_cores_enabled;
+ ld_right = (pmali_plat->dvfs_table[currentStep].upthreshold) *
+ (num_cores_enabled - 1);
+ if (ld_left < ld_right) {
+ change_mode = 2;
+ }
+ }
+ } else if (currentStep > pmali_plat->scale_info.minclk) {
+ change_mode = 1;
+ } else if (num_cores_enabled > 1) { /* decrease PPS */
+ if (data->utilization_pp <= ld_down) {
+ ld_left = data->utilization_pp * num_cores_enabled;
+ ld_right = (pmali_plat->dvfs_table[currentStep].upthreshold) *
+ (num_cores_enabled - 1);
+ scalingdbg(2, "ld_left=%d, ld_right=%d\n", ld_left, ld_right);
+ if (ld_left < ld_right) {
+ change_mode = 2;
+ }
+ }
+ }
+
+ if (change_mode == 1) {
+ decided_fs_idx--;
+ } else if (change_mode == 2) { /* decrease PPS */
+ *pp_change_flag = -1;
+ }
+ }
+
+ if (decided_fs_idx < 0 ) {
+ printk("gpu debug, next index below 0\n");
+ decided_fs_idx = 0;
+ }
+ if (decided_fs_idx > pmali_plat->scale_info.maxclk) {
+ decided_fs_idx = pmali_plat->scale_info.maxclk;
+ printk("gpu debug, next index above max, set to %d\n", decided_fs_idx);
+ }
+
+ if (change_mode)
+ mali_stay_count = pmali_plat->dvfs_table[decided_fs_idx].keep_count;
+ *next_fs_idx = decided_fs_idx;
+}
+#endif
+
+void mali_pp_fs_scaling_update(struct mali_gpu_utilization_data *data)
+{
+#ifndef CONFIG_MALI_DVFS
+ int ret = 0;
+ int pp_change_flag = 0;
+ u32 next_idx = 0;
+
+#if LOG_MALI_SCALING
+ u32 last_pp = num_cores_enabled;
+#endif
+ mali_decide_next_status(data, &next_idx, &pp_change_flag);
+
+ if (pp_change_flag == 1)
+ ret = enable_pp_cores(pmali_plat->sc_mpp);
+ else if (pp_change_flag == 2)
+ ret = enable_one_core();
+ else if (pp_change_flag == -1) {
+ ret = disable_one_core();
+ }
+
+#if LOG_MALI_SCALING
+ if (pp_change_flag || (next_idx != currentStep))
+ trace_utilization(data, currentStep, next_idx, last_pp, num_cores_enabled);
+#endif
+
+ if (next_idx != currentStep) {
+ ret = 1;
+ currentStep = next_idx;
+ }
+
+ if (ret == 1)
+ schedule_work(&wq_work);
+#ifdef CONFIG_MALI400_PROFILING
+ else
+ _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
+ MALI_PROFILING_EVENT_CHANNEL_GPU |
+ MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
+ get_current_frequency(),
+ 0, 0, 0, 0);
+#endif
+#endif
+}
+
+u32 get_mali_schel_mode(void)
+{
+ return scaling_mode;
+}
+
+void set_mali_schel_mode(u32 mode)
+{
+#ifndef CONFIG_MALI_DVFS
+ MALI_DEBUG_ASSERT(mode < MALI_SCALING_MODE_MAX);
+ if (mode >= MALI_SCALING_MODE_MAX)
+ return;
+ scaling_mode = mode;
+
+ //disable thermal in turbo mode
+ if (scaling_mode == MALI_TURBO_MODE) {
+ pmali_plat->limit_on = 0;
+ } else {
+ pmali_plat->limit_on = 1;
+ }
+ /* set default performance range. */
+ pmali_plat->scale_info.minclk = pmali_plat->cfg_min_clock;
+ pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
+ pmali_plat->scale_info.minpp = pmali_plat->cfg_min_pp;
+ pmali_plat->scale_info.maxpp = pmali_plat->cfg_pp;
+
+ /* set current status and tune max freq */
+ if (scaling_mode == MALI_PP_FS_SCALING) {
+ pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
+ enable_pp_cores(pmali_plat->sc_mpp);
+ } else if (scaling_mode == MALI_SCALING_DISABLE) {
+ pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
+ enable_max_num_cores();
+ } else if (scaling_mode == MALI_TURBO_MODE) {
+ pmali_plat->scale_info.maxclk = pmali_plat->turbo_clock;
+ enable_max_num_cores();
+ }
+ currentStep = pmali_plat->scale_info.maxclk;
+ schedule_work(&wq_work);
+#endif
+}
+
+u32 get_current_frequency(void)
+{
+ return get_mali_freq(currentStep);
+}
+
+void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data)
+{
+#ifndef CONFIG_MALI_DVFS
+ if (mali_pm_statue)
+ return;
+
+ switch (scaling_mode) {
+ case MALI_PP_FS_SCALING:
+ mali_pp_fs_scaling_update(data);
+ break;
+ case MALI_PP_SCALING:
+ mali_pp_scaling_update(data);
+ break;
+ default:
+ break;
+ }
+#endif
+}
+static u32 clk_cntl_save = 0;
+void mali_dev_freeze(void)
+{
+ clk_cntl_save = mplt_read(HHI_MALI_CLK_CNTL);
+}
+
+void mali_dev_restore(void)
+{
+
+ mplt_write(HHI_MALI_CLK_CNTL, clk_cntl_save);
+ if (pmali_plat && pmali_plat->pdev) {
+ mali_clock_init_clk_tree(pmali_plat->pdev);
+ } else {
+ printk("error: init clock failed, pmali_plat=%p, pmali_plat->pdev=%p\n",
+ pmali_plat, pmali_plat == NULL ? NULL: pmali_plat->pdev);
+ }
+}
+
+int mali_meson_get_gpu_data(struct mali_gpu_device_data *mgpu_data)
+{
+ mgpu_data->get_clock_info = NULL;
+ mgpu_data->get_freq = NULL;
+ mgpu_data->set_freq = NULL;
+ mgpu_data->utilization_callback = mali_gpu_utilization_callback;
+ return 0;
+}
--- /dev/null
+/*
+ * AMLOGIC Mali fix driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
+ *
+ * Author: Tim Yao <timyao@amlogic.com>
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/timer.h>
+#include <asm/io.h>
+#include <linux/ioport.h>
+#include <linux/dma-mapping.h>
+
+#include <linux/module.h>
+
+#include <mach/am_regs.h>
+#include <mach/clock.h>
+#include <linux/io.h>
+#include <mach/io.h>
+#include <plat/io.h>
+#include <asm/io.h>
+
+#include "mali_kernel_common.h"
+#include "mali_osk.h"
+#include "mali_platform.h"
+#include "mali_fix.h"
+
+#define MALI_MM1_REG_ADDR 0xd0064000
+#define MALI_MMU_REGISTER_INT_STATUS 0x0008
+#define MALI_MM2_REG_ADDR 0xd0065000
+#define MALI_MMU_REGISTER_INT_STATUS 0x0008
+#define MALI_MM_REG_SIZE 0x1000
+
+#define READ_MALI_MMU1_REG(r) (ioread32(((u8*)mali_mm1_regs) + r))
+#define READ_MALI_MMU2_REG(r) (ioread32(((u8*)mali_mm2_regs) + r))
+
+extern int mali_PP0_int_cnt(void);
+extern int mali_PP1_int_cnt(void);
+
+#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
+static ulong * mali_mm1_regs = NULL;
+static ulong * mali_mm2_regs = NULL;
+static struct timer_list timer;
+
+static u32 mali_pp1_int_count = 0;
+static u32 mali_pp2_int_count = 0;
+static u32 mali_pp1_mmu_int_count = 0;
+static u32 mali_pp2_mmu_int_count = 0;
+static u32 mali_mmu_int_process_state[2];
+
+static void timer_callback(ulong data)
+{
+ unsigned long mali_flags;
+
+ mali_pp1_int_count = mali_PP0_int_cnt();
+ mali_pp2_int_count = mali_PP1_int_cnt();
+
+ /* lock mali_clock_gating when access Mali registers */
+ mali_flags = mali_clock_gating_lock();
+
+ if (readl((u32 *)P_HHI_MALI_CLK_CNTL) & 0x100) {
+ /* polling for PP1 MMU interrupt */
+ if (mali_mmu_int_process_state[0] == MMU_INT_NONE) {
+ if (READ_MALI_MMU1_REG(MALI_MMU_REGISTER_INT_STATUS) != 0) {
+ mali_pp1_mmu_int_count++;
+ MALI_DEBUG_PRINT(3, ("Mali MMU: core0 page fault emit \n"));
+ mali_mmu_int_process_state[0] = MMU_INT_HIT;
+ __raw_writel(1, (volatile void *)P_ISA_TIMERC);
+ }
+ }
+
+ /* polling for PP2 MMU interrupt */
+ if (mali_mmu_int_process_state[1] == MMU_INT_NONE) {
+ if (READ_MALI_MMU2_REG(MALI_MMU_REGISTER_INT_STATUS) != 0) {
+ mali_pp2_mmu_int_count++;
+ MALI_DEBUG_PRINT(3, ("Mali MMU: core1 page fault emit \n"));
+ mali_mmu_int_process_state[1] = MMU_INT_HIT;
+ __raw_writel(1, (volatile void *)P_ISA_TIMERC);
+ }
+ }
+ }
+
+ mali_clock_gating_unlock(mali_flags);
+
+ timer.expires = jiffies + HZ/100;
+
+ add_timer(&timer);
+}
+
+void malifix_set_mmu_int_process_state(int index, int state)
+{
+ if (index < 2)
+ mali_mmu_int_process_state[index] = state;
+}
+
+int malifix_get_mmu_int_process_state(int index)
+{
+ if (index < 2)
+ return mali_mmu_int_process_state[index];
+ return 0;
+}
+#endif
+
+void malifix_init(void)
+{
+#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
+ if (!mali_meson_is_revb())
+ return;
+
+ if ((mali_mm1_regs) && (mali_mm2_regs)) return;
+ mali_mmu_int_process_state[0] = 0;
+ mali_mmu_int_process_state[1] = 0;
+
+ /* set up Timer C as a 1uS one-shot timer */
+ aml_clr_reg32_mask(P_ISA_TIMER_MUX, (1<<18)|(1<<14)|(3<<4));
+ aml_set_reg32_mask(P_ISA_TIMER_MUX, (1<<18)|(0<<14)|(0<<4));
+
+ setup_timer(&timer, timer_callback, 0);
+
+ mali_mm1_regs = (ulong *)ioremap_nocache(MALI_MM1_REG_ADDR, MALI_MM_REG_SIZE);
+ if (mali_mm1_regs)
+ printk("Mali pp1 MMU register mapped at %p...\n", mali_mm1_regs);
+
+ mali_mm2_regs = (ulong *)ioremap_nocache(MALI_MM2_REG_ADDR, MALI_MM_REG_SIZE);
+ if (mali_mm2_regs)
+ printk("Mali pp2 MMU register mapped at %p...\n", mali_mm2_regs);
+
+ if ((mali_mm1_regs != NULL) && (mali_mm2_regs != NULL))
+ mod_timer(&timer, jiffies + HZ/100);
+#endif
+}
+
+void malifix_exit(void)
+{
+#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
+ if (!mali_meson_is_revb())
+ return;
+
+ del_timer(&timer);
+
+ if (mali_mm1_regs != NULL)
+ iounmap(mali_mm1_regs);
+ mali_mm1_regs = NULL;
+
+ if (mali_mm2_regs != NULL)
+ iounmap(mali_mm2_regs);
+ mali_mm2_regs = NULL;
+
+#endif
+ return;
+}
+
+#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
+module_param(mali_pp1_int_count, uint, 0664);
+MODULE_PARM_DESC(mali_pp1_int_count, "Mali PP1 interrupt count\n");
+
+module_param(mali_pp2_int_count, uint, 0664);
+MODULE_PARM_DESC(mali_pp2_int_count, "Mali PP1 interrupt count\n");
+
+module_param(mali_pp1_mmu_int_count, uint, 0664);
+MODULE_PARM_DESC(mali_pp1_mmu_int_count, "Mali PP1 mmu interrupt count\n");
+
+module_param(mali_pp2_mmu_int_count, uint, 0664);
+MODULE_PARM_DESC(mali_pp2_mmu_int_count, "Mali PP2 mmu interrupt count\n");
+#endif
+
+MODULE_DESCRIPTION("AMLOGIC mali fix driver");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Tim Yao <timyao@amlogic.com>");
--- /dev/null
+#ifndef MALI_FIX_H
+#define MALI_FIX_H
+
+#define MMU_INT_NONE 0
+#define MMU_INT_HIT 1
+#define MMU_INT_TOP 2
+#define MMU_INT_BOT 3
+
+extern void malifix_init(void);
+extern void malifix_exit(void);
+extern void malifix_set_mmu_int_process_state(int, int);
+extern int malifix_get_mmu_int_process_state(int);
+extern int mali_meson_is_revb(void);
+#endif /* MALI_FIX_H */
--- /dev/null
+/*
+ * This confidential and proprietary software may be used only as
+ * authorised by a licensing agreement from AMLOGIC, INC.
+ * (C) COPYRIGHT 2011 AMLOGIC, INC.
+ * ALL RIGHTS RESERVED
+ * The entire notice above must be reproduced on all authorised
+ * copies and copies may only be made to the extent permitted
+ * by a licensing agreement from AMLOGIC, INC.
+ */
+
+/**
+ * @file mali_platform.c
+ * Platform specific Mali driver functions for meson platform
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+#include <linux/spinlock.h>
+#include <linux/spinlock_types.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <mach/am_regs.h>
+#include <mach/clock.h>
+
+#include "mali_kernel_common.h"
+#include "mali_osk.h"
+#include "mali_platform.h"
+#include "mali_poweron_reg.h"
+#include "mali_fix.h"
+#include "mali_platform.h"
+
+static int last_power_mode = -1;
+static int mali_init_flag = 0;
+static const u32 poweron_data[] =
+{
+/* commands */
+/* 000 */ 0x00000040, 0x20400000, 0x00000300, 0x30040000,
+/* 010 */ 0x00000400, 0x400a0000, 0x0f000033, 0x10000042,
+/* 020 */ 0x00300c00, 0x10000040, 0x4c000001, 0x00000000,
+/* 030 */ 0x00000000, 0x60000000, 0x00000000, 0x00000000,
+/* 040 */ 0x00004000, 0x00002000, 0x00000210, 0x0000203f,
+/* 050 */ 0x00000220, 0x0000203f, 0x00000230, 0x0000203f,
+/* 060 */ 0x00000240, 0x0000203f, 0x00000250, 0x0000203f,
+/* 070 */ 0x00000260, 0x0000203f, 0x00000270, 0x0000203f,
+/* 080 */ 0x00000280, 0x0000203f, 0x00000290, 0x0000203f,
+/* 090 */ 0x000002a0, 0x0000203f, 0x000002b0, 0x0000203f,
+/* 0a0 */ 0x000002c0, 0x0000203f, 0x000002d0, 0x0000203f,
+/* 0b0 */ 0x000002e0, 0x0000203f, 0x000002f0, 0x0000203f,
+/* 0c0 */ 0x00002000, 0x00002000, 0x00002010, 0x0000203f,
+/* 0d0 */ 0x00002020, 0x0000203f, 0x00002030, 0x0000203f,
+/* 0e0 */ 0x00002040, 0x0000203f, 0x00002050, 0x0000203f,
+/* 0f0 */ 0x00002060, 0x0000203f, 0x00002070, 0x0000203f,
+/* 100 */ 0x00002080, 0x0000203f, 0x00002090, 0x0000203f,
+/* 110 */ 0x000020a0, 0x0000203f, 0x000020b0, 0x0000203f,
+/* 120 */ 0x000020c0, 0x0000203f, 0x000020d0, 0x0000203f,
+/* 130 */ 0x000020e0, 0x0000203f, 0x000020f0, 0x0000203f,
+/* 140 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 150 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 160 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 170 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 180 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 190 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 1a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 1b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 1c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 1d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 1e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 1f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 200 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 210 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 220 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 230 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 240 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 250 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 260 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 270 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 280 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 290 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 2a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 2b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 2c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 2d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 2e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 2f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* const */
+/* 300 */ 0x3f2a6400, 0xbf317600, 0x3e8d8e00, 0x00000000,
+/* 310 */ 0x3f2f7000, 0x3f36e200, 0x3e10c500, 0x00000000,
+/* 320 */ 0xbe974e00, 0x3dc35300, 0x3f735800, 0x00000000,
+/* 330 */ 0x00000000, 0x00000000, 0x00000000, 0x3f800000,
+/* 340 */ 0x42b00000, 0x42dc0000, 0x3f800000, 0x3f800000,
+/* 350 */ 0x42b00000, 0x42dc0000, 0x00000000, 0x00000000,
+/* 360 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 370 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 380 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 390 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 3a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 3b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 3c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 3d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 3e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* 3f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+/* inst */
+/* 400 */ 0xad4ad6b5, 0x438002b5, 0x0007ffe0, 0x00001e00,
+/* 410 */ 0xad4ad694, 0x038002b5, 0x0087ffe0, 0x00005030,
+/* 420 */ 0xad4bda56, 0x038002b5, 0x0007ffe0, 0x00001c10,
+/* 430 */ 0xad4ad6b5, 0x038002b5, 0x4007fee0, 0x00001c00
+};
+
+static struct clk *mali_clk = NULL;
+
+#if MESON_CPU_TYPE <= MESON_CPU_TYPE_MESON6
+
+#define OFFSET_MMU_DTE 0
+#define OFFSET_MMU_PTE 4096
+#define OFFSET_MMU_VIRTUAL_ZERO 8192
+
+#define INT_MALI_GP_BITS (1<<16)
+#define INT_MALI_PP_BITS (1<<18)
+#define INT_MALI_PP_MMU_BITS (1<<19)
+#define INT_ALL (0xffffffff)
+
+#define INT_MALI_PP_MMU_PAGE_FAULT (1<<0)
+
+#define MMU_FLAG_DTE_PRESENT 0x01
+#define MMU_FLAG_PTE_PAGE_PRESENT 0x01
+#define MMU_FLAG_PTE_RD_PERMISSION 0x02
+#define MMU_FLAG_PTE_WR_PERMISSION 0x04
+
+//static int mali_revb_flag = -1;
+static DEFINE_SPINLOCK(lock);
+extern int mali_revb_flag;
+int mali_meson_is_revb(void)
+{
+ printk("mail version=%d\n",mali_revb_flag);
+ if (mali_revb_flag == -1)
+ mali_revb_flag = 1;
+ else if (mali_revb_flag == 0)
+ panic("rev-a! you should neet earlier version of mali_driver.!\n");
+
+ return mali_revb_flag;
+}
+
+static void mali_meson_poweron(int first_poweron)
+{
+ unsigned long flags;
+ u32 p, p_aligned;
+ dma_addr_t p_phy;
+ int i;
+ unsigned int_mask;
+
+ if (!first_poweron) {
+ if ((last_power_mode != -1) && (last_power_mode != MALI_POWER_MODE_DEEP_SLEEP)) {
+ MALI_DEBUG_PRINT(3, ("Maybe your system not deep sleep now.......\n"));
+ //printk("Maybe your system not deep sleep now.......\n");
+ return;
+ }
+ }
+
+ MALI_DEBUG_PRINT(2, ("mali_meson_poweron: Mali APB bus accessing\n"));
+ if (READ_MALI_REG(MALI_PP_PP_VERSION) != MALI_PP_PP_VERSION_MAGIC) {
+ MALI_DEBUG_PRINT(3, ("mali_meson_poweron: Mali APB bus access failed\n"));
+ //printk("mali_meson_poweron: Mali APB bus access failed.");
+ return;
+ }
+ MALI_DEBUG_PRINT(2, ("..........accessing done.\n"));
+ if (READ_MALI_REG(MALI_MMU_DTE_ADDR) != 0) {
+ MALI_DEBUG_PRINT(3, ("mali_meson_poweron: Mali is not really powered off\n"));
+ //printk("mali_meson_poweron: Mali is not really powered off.");
+ return;
+ }
+
+ p = (u32)kcalloc(4096 * 4, 1, GFP_KERNEL);
+ if (!p) {
+ printk("mali_meson_poweron: NOMEM in meson_poweron\n");
+ return;
+ }
+
+ p_aligned = __ALIGN_MASK(p, 4096);
+
+ /* DTE */
+ *(u32 *)(p_aligned) = (virt_to_phys((void *)p_aligned) + OFFSET_MMU_PTE) | MMU_FLAG_DTE_PRESENT;
+ /* PTE */
+ for (i=0; i<1024; i++) {
+ *(u32 *)(p_aligned + OFFSET_MMU_PTE + i*4) =
+ (virt_to_phys((void *)p_aligned) + OFFSET_MMU_VIRTUAL_ZERO + 4096 * i) |
+ MMU_FLAG_PTE_PAGE_PRESENT |
+ MMU_FLAG_PTE_RD_PERMISSION;
+ }
+
+ /* command & data */
+ memcpy((void *)(p_aligned + OFFSET_MMU_VIRTUAL_ZERO), poweron_data, 4096);
+
+ p_phy = dma_map_single(NULL, (void *)p_aligned, 4096 * 3, DMA_TO_DEVICE);
+
+ /* Set up Mali GP MMU */
+ WRITE_MALI_REG(MALI_MMU_DTE_ADDR, p_phy);
+ WRITE_MALI_REG(MALI_MMU_CMD, 0);
+
+ if ((READ_MALI_REG(MALI_MMU_STATUS) & 1) != 1)
+ printk("mali_meson_poweron: MMU enabling failed.\n");
+
+ /* Set up Mali command registers */
+ WRITE_MALI_REG(MALI_APB_GP_VSCL_START, 0);
+ WRITE_MALI_REG(MALI_APB_GP_VSCL_END, 0x38);
+
+ spin_lock_irqsave(&lock, flags);
+
+ int_mask = READ_MALI_REG(MALI_APB_GP_INT_MASK);
+ WRITE_MALI_REG(MALI_APB_GP_INT_CLEAR, 0x707bff);
+ WRITE_MALI_REG(MALI_APB_GP_INT_MASK, 0);
+
+ /* Start GP */
+ WRITE_MALI_REG(MALI_APB_GP_CMD, 1);
+
+ for (i = 0; i<100; i++)
+ udelay(500);
+
+ /* check Mali GP interrupt */
+ if (READ_MALI_REG(MALI_APB_GP_INT_RAWSTAT) & 0x707bff)
+ printk("mali_meson_poweron: Interrupt received.\n");
+ else
+ printk("mali_meson_poweron: No interrupt received.\n");
+
+ /* force reset GP */
+ WRITE_MALI_REG(MALI_APB_GP_CMD, 1 << 5);
+
+ /* stop MMU paging and reset */
+ WRITE_MALI_REG(MALI_MMU_CMD, 1);
+ WRITE_MALI_REG(MALI_MMU_CMD, 6);
+
+ for (i = 0; i<100; i++)
+ udelay(500);
+
+ WRITE_MALI_REG(MALI_APB_GP_INT_CLEAR, 0x3ff);
+ WRITE_MALI_REG(MALI_MMU_INT_CLEAR, INT_ALL);
+ WRITE_MALI_REG(MALI_MMU_INT_MASK, 0);
+
+ WRITE_MALI_REG(MALI_APB_GP_INT_CLEAR, 0x707bff);
+ WRITE_MALI_REG(MALI_APB_GP_INT_MASK, int_mask);
+
+ spin_unlock_irqrestore(&lock, flags);
+
+ dma_unmap_single(NULL, p_phy, 4096 * 3, DMA_TO_DEVICE);
+
+ kfree((void *)p);
+
+ /* Mali revision detection */
+ if (last_power_mode == -1)
+ mali_revb_flag = mali_meson_is_revb();
+}
+#else
+static void mali_meson_poweron(int first_poweron) {
+ return;
+}
+#endif /*MESON_CPU_TYPE <= MESON_CPU_TYPE_MESON6 */
+
+_mali_osk_errcode_t mali_platform_init(void)
+{
+ mali_clk = clk_get_sys("mali", "pll_fixed");
+
+ if (mali_clk ) {
+ if (!mali_init_flag) {
+ clk_set_rate(mali_clk, 333000000);
+ mali_clk->enable(mali_clk);
+ malifix_init();
+ mali_meson_poweron(1);
+ mali_init_flag = 1;
+ }
+ MALI_SUCCESS;
+ } else
+ panic("linux kernel should > 3.0\n");
+
+#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6
+ MALI_PRINT_ERROR(("Failed to lookup mali clock"));
+ MALI_ERROR(_MALI_OSK_ERR_FAULT);
+#else
+ MALI_SUCCESS;
+#endif /* CONFIG_ARCH_MESON6 */
+}
+
+_mali_osk_errcode_t mali_platform_deinit(void)
+{
+ mali_init_flag =0;
+ printk("MALI:mali_platform_deinit\n");
+ malifix_exit();
+
+ MALI_SUCCESS;
+}
+
+_mali_osk_errcode_t mali_platform_power_mode_change(mali_power_mode power_mode)
+{
+ MALI_DEBUG_PRINT(3, ( "mali_platform_power_mode_change power_mode=%d\n", power_mode));
+
+ switch (power_mode) {
+ case MALI_POWER_MODE_LIGHT_SLEEP:
+ case MALI_POWER_MODE_DEEP_SLEEP:
+ /* Turn off mali clock gating */
+ mali_clk->disable(mali_clk);
+ break;
+
+ case MALI_POWER_MODE_ON:
+ /* Turn on MALI clock gating */
+ mali_clk->enable(mali_clk);
+ mali_meson_poweron(0);
+ break;
+ }
+ last_power_mode = power_mode;
+ MALI_SUCCESS;
+}
+
--- /dev/null
+/*
+ * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+ *
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ *
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+/**
+ * @file mali_platform.h
+ * Platform specific Mali driver functions
+ */
+
+#ifndef __MALI_PLATFORM_H__
+#define __MALI_PLATFORM_H__
+
+#include "mali_osk.h"
+
+/** @brief description of power change reasons
+ */
+typedef enum mali_power_mode_tag
+{
+ MALI_POWER_MODE_ON, /**< Power Mali on */
+ MALI_POWER_MODE_LIGHT_SLEEP, /**< Mali has been idle for a short time, or runtime PM suspend */
+ MALI_POWER_MODE_DEEP_SLEEP, /**< Mali has been idle for a long time, or OS suspend */
+} mali_power_mode;
+
+/** @brief Platform specific setup and initialisation of MALI
+ *
+ * This is called from the entrypoint of the driver to initialize the platform
+ *
+ * @return _MALI_OSK_ERR_OK on success otherwise, a suitable _mali_osk_errcode_t error.
+ */
+_mali_osk_errcode_t mali_platform_init(void);
+
+/** @brief Platform specific deinitialisation of MALI
+ *
+ * This is called on the exit of the driver to terminate the platform
+ *
+ * @return _MALI_OSK_ERR_OK on success otherwise, a suitable _mali_osk_errcode_t error.
+ */
+_mali_osk_errcode_t mali_platform_deinit(void);
+
+/** @brief Platform specific powerdown sequence of MALI
+ *
+ * Notification from the Mali device driver stating the new desired power mode.
+ * MALI_POWER_MODE_ON must be obeyed, while the other modes are optional.
+ * @param power_mode defines the power modes
+ * @return _MALI_OSK_ERR_OK on success otherwise, a suitable _mali_osk_errcode_t error.
+ */
+_mali_osk_errcode_t mali_platform_power_mode_change(mali_power_mode power_mode);
+
+
+/** @brief Platform specific handling of GPU utilization data
+ *
+ * When GPU utilization data is enabled, this function will be
+ * periodically called.
+ *
+ * @param utilization The workload utilization of the Mali GPU. 0 = no utilization, 256 = full utilization.
+ */
+void mali_gpu_utilization_handler(u32 utilization);
+
+/** @brief Setting the power domain of MALI
+ *
+ * This function sets the power domain of MALI if Linux run time power management is enabled
+ *
+ * @param dev Reference to struct platform_device (defined in linux) used by MALI GPU
+ */
+void set_mali_parent_power_domain(void* dev);
+
+#endif
--- /dev/null
+/*
+ * This confidential and proprietary software may be used only as
+ * authorised by a licensing agreement from AMLOGIC, INC.
+ * (C) COPYRIGHT 2011 AMLOGIC, INC.
+ * ALL RIGHTS RESERVED
+ * The entire notice above must be reproduced on all authorised
+ * copies and copies may only be made to the extent permitted
+ * by a licensing agreement from AMLOGIC, INC.
+ */
+
+#ifndef MALI_POWERON_REG_H
+#define MALI_POWERON_REG_H
+
+#define MALI_PP_PP_VERSION_MAGIC 0xCD070100UL
+
+#if defined(IO_APB2_BUS_PHY_BASE)
+#define WRITE_MALI_REG(reg, val) \
+ __raw_writel(val, (volatile void *)(reg - IO_APB2_BUS_PHY_BASE + IO_APB2_BUS_BASE))
+#define READ_MALI_REG(reg) \
+ __raw_readl((volatile void *)(reg - IO_APB2_BUS_PHY_BASE + IO_APB2_BUS_BASE))
+#else
+#define WRITE_MALI_REG(reg, val) \
+ __raw_writel(val, (volatile void *)(reg - IO_APB_BUS_PHY_BASE + IO_APB_BUS_BASE))
+#define READ_MALI_REG(reg) \
+ __raw_readl((volatile void *)(reg - IO_APB_BUS_PHY_BASE + IO_APB_BUS_BASE))
+#endif
+
+#define MALI_APB_GP_VSCL_START 0xd0060000
+#define MALI_APB_GP_VSCL_END 0xd0060004
+#define MALI_APB_GP_CMD 0xd0060020
+#define MALI_APB_GP_INT_RAWSTAT 0xd0060024
+#define MALI_APB_GP_INT_CLEAR 0xd0060028
+#define MALI_APB_GP_INT_MASK 0xd006002c
+#define MALI_APB_GP_INT_STAT 0xd0060030
+
+#define MALI_MMU_DTE_ADDR 0xd0063000
+#define MALI_MMU_STATUS 0xd0063004
+#define MALI_MMU_CMD 0xd0063008
+#define MALI_MMU_RAW_STATUS 0xd0064014
+#define MALI_MMU_INT_CLEAR 0xd0064018
+#define MALI_MMU_INT_MASK 0xd006401c
+#define MALI_MMU_INT_STATUS 0xd0064020
+
+#define MALI_PP_MMU_DTE_ADDR 0xd0064000
+#define MALI_PP_MMU_STATUS 0xd0064004
+#define MALI_PP_MMU_CMD 0xd0064008
+#define MALI_PP_MMU_RAW_STATUS 0xd0064014
+#define MALI_PP_MMU_INT_CLEAR 0xd0064018
+#define MALI_PP_MMU_INT_MASK 0xd006401c
+#define MALI_PP_MMU_INT_STATUS 0xd0064020
+
+#define MALI_APB_PP_REND_LIST_ADDR 0xd0068000
+#define MALI_APB_PP_REND_RSW_BASE 0xd0068004
+#define MALI_APB_PP_REND_VERTEX_BASE 0xd0068008
+#define MALI_APB_PPSUBPIXEL_SPECIFIER 0xd0068048
+#define MALI_APB_WB0_SOURCE_SELECT 0xd0068100
+#define MALI_APB_WB0_TARGET_ADDR 0xd0068104
+#define MALI_APB_WB0_TARGET_SCANLINE_LENGTH 0xd0068114
+
+#define MALI_PP_PP_VERSION 0xd0069000
+#define MALI_PP_STATUS 0xd0069008
+#define MALI_PP_CTRL_MGMT 0xd006900C
+#define MALI_PP_INT_RAWSTAT 0xd0069020
+#define MALI_PP_INT_CLEAR 0xd0069024
+#define MALI_PP_INT_MASK 0xd0069028
+#define MALI_PP_INT_STAT 0xd006902C
+
+#endif /* MALI_POWERON_REG_H */
--- /dev/null
+/*
+ * platform.c
+ *
+ * clock source setting and resource config
+ *
+ * Created on: Dec 4, 2013
+ * Author: amlogic
+ */
+
+#include <linux/platform_device.h>
+#include <linux/version.h>
+#include <linux/pm.h>
+#include <linux/of.h>
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <mach/register.h>
+#include <mach/irqs.h>
+#include <mach/io.h>
+#include <asm/io.h>
+#include <linux/mali/mali_utgard.h>
+
+#include <common/mali_kernel_common.h>
+#include <common/mali_osk_profiling.h>
+#include <common/mali_pmu.h>
+
+#include "meson_main.h"
+#include "mali_fix.h"
+#include "mali_platform.h"
+
+/**
+ * For Meson 6tvd.
+ *
+ */
+
+#if MESON_CPU_TYPE <= MESON_CPU_TYPE_MESON6TV
+
+u32 mali_dvfs_clk[1];
+u32 mali_dvfs_clk_sample[1];
+
+#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6TV
+#undef INT_MALI_GP
+#undef INT_MALI_GP_MMU
+#undef INT_MALI_PP
+#undef INT_MALI_PP2
+#undef INT_MALI_PP3
+#undef INT_MALI_PP4
+#undef INT_MALI_PP_MMU
+#undef INT_MALI_PP2_MMU
+#undef INT_MALI_PP3_MMU
+#undef INT_MALI_PP4_MMU
+
+#define INT_MALI_GP (48+32)
+#define INT_MALI_GP_MMU (49+32)
+#define INT_MALI_PP (50+32)
+#define INT_MALI_PP2 (58+32)
+#define INT_MALI_PP3 (60+32)
+#define INT_MALI_PP4 (62+32)
+#define INT_MALI_PP_MMU (51+32)
+#define INT_MALI_PP2_MMU (59+32)
+#define INT_MALI_PP3_MMU (61+32)
+#define INT_MALI_PP4_MMU (63+32)
+
+#ifndef CONFIG_MALI400_4_PP
+static struct resource meson_mali_resources[] =
+{
+ MALI_GPU_RESOURCES_MALI400_MP2(0xd0060000,
+ INT_MALI_GP, INT_MALI_GP_MMU,
+ INT_MALI_PP, INT_MALI_PP_MMU,
+ INT_MALI_PP2, INT_MALI_PP2_MMU)
+};
+#else
+static struct resource meson_mali_resources[] =
+{
+ MALI_GPU_RESOURCES_MALI400_MP4(0xd0060000,
+ INT_MALI_GP, INT_MALI_GP_MMU,
+ INT_MALI_PP, INT_MALI_PP_MMU,
+ INT_MALI_PP2, INT_MALI_PP2_MMU,
+ INT_MALI_PP3, INT_MALI_PP3_MMU,
+ INT_MALI_PP4, INT_MALI_PP4_MMU
+ )
+};
+#endif
+
+#elif MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
+
+#undef INT_MALI_GP
+#undef INT_MALI_GP_MMU
+#undef INT_MALI_PP
+#undef INT_MALI_PP2
+#undef INT_MALI_PP_MMU
+#undef INT_MALI_PP2_MMU
+
+#define INT_MALI_GP (48+32)
+#define INT_MALI_GP_MMU (49+32)
+#define INT_MALI_PP (50+32)
+#define INT_MALI_PP_MMU (51+32)
+#define INT_MALI_PP2_MMU ( 6+32)
+
+static struct resource meson_mali_resources[] =
+{
+ MALI_GPU_RESOURCES_MALI400_MP2(0xd0060000,
+ INT_MALI_GP, INT_MALI_GP_MMU,
+ INT_MALI_PP, INT_MALI_PP2_MMU,
+ INT_MALI_PP_MMU, INT_MALI_PP2_MMU)
+};
+
+#else /* MESON_CPU_TYPE == MESON_CPU_TYPE_MESON3 */
+
+#undef INT_MALI_GP
+#undef INT_MALI_GP_MMU
+#undef INT_MALI_PP
+#undef INT_MALI_PP_MMU
+
+#define INT_MALI_GP 48
+#define INT_MALI_GP_MMU 49
+#define INT_MALI_PP 50
+#define INT_MALI_PP_MMU 51
+
+static struct resource meson_mali_resources[] =
+{
+ MALI_GPU_RESOURCES_MALI400_MP1(0xd0060000,
+ INT_MALI_GP, INT_MALI_GP_MMU, INT_MALI_PP, INT_MALI_PP_MMU)
+};
+#endif /* MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6TV */
+
+void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data)
+{
+
+}
+
+mali_plat_info_t mali_plat_data = {
+
+};
+
+int mali_meson_init_start(struct platform_device* ptr_plt_dev)
+{
+ /* for mali platform data. */
+ struct mali_gpu_device_data* pdev = ptr_plt_dev->dev.platform_data;
+
+ pdev->control_interval = 1000;
+ pdev->utilization_callback = mali_gpu_utilization_callback;
+
+ /* for resource data. */
+ ptr_plt_dev->num_resources = ARRAY_SIZE(meson_mali_resources);
+ ptr_plt_dev->resource = meson_mali_resources;
+ return 0;
+}
+
+int mali_meson_init_finish(struct platform_device* ptr_plt_dev)
+{
+ mali_platform_init();
+ return 0;
+}
+
+int mali_meson_uninit(struct platform_device* ptr_plt_dev)
+{
+ mali_platform_deinit();
+ return 0;
+}
+
+int mali_light_suspend(struct device *device)
+{
+ int ret = 0;
+
+ if (NULL != device->driver &&
+ NULL != device->driver->pm &&
+ NULL != device->driver->pm->runtime_suspend)
+ {
+ /* Need to notify Mali driver about this event */
+ ret = device->driver->pm->runtime_suspend(device);
+ }
+
+ mali_platform_power_mode_change(MALI_POWER_MODE_LIGHT_SLEEP);
+ return ret;
+}
+
+int mali_light_resume(struct device *device)
+{
+ int ret = 0;
+
+ mali_platform_power_mode_change(MALI_POWER_MODE_ON);
+
+ if (NULL != device->driver &&
+ NULL != device->driver->pm &&
+ NULL != device->driver->pm->runtime_resume)
+ {
+ /* Need to notify Mali driver about this event */
+ ret = device->driver->pm->runtime_resume(device);
+ }
+ return ret;
+}
+
+int mali_deep_suspend(struct device *device)
+{
+ int ret = 0;
+
+ if (NULL != device->driver &&
+ NULL != device->driver->pm &&
+ NULL != device->driver->pm->suspend)
+ {
+ /* Need to notify Mali driver about this event */
+ ret = device->driver->pm->suspend(device);
+ }
+
+ mali_platform_power_mode_change(MALI_POWER_MODE_DEEP_SLEEP);
+ return ret;
+}
+
+int mali_deep_resume(struct device *device)
+{
+ int ret = 0;
+
+ mali_platform_power_mode_change(MALI_POWER_MODE_ON);
+
+ if (NULL != device->driver &&
+ NULL != device->driver->pm &&
+ NULL != device->driver->pm->resume)
+ {
+ /* Need to notify Mali driver about this event */
+ ret = device->driver->pm->resume(device);
+ }
+ return ret;
+
+}
+
+void mali_core_scaling_term(void)
+{
+
+}
+
+int get_gpu_max_clk_level(void)
+{
+ return 0;
+}
+
+void mali_post_init(void)
+{
+}
+#endif /* MESON_CPU_TYPE <= MESON_CPU_TYPE_MESON6 */
--- /dev/null
+#include <linux/platform_device.h>
+#include <linux/version.h>
+#include <linux/pm.h>
+#include <mach/register.h>
+#include <mach/irqs.h>
+#include <linux/io.h>
+#include <mach/io.h>
+#include <plat/io.h>
+#include <asm/io.h>
+#include "meson_main.h"
+
+#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6TVD
+
+#define FCLK_MPLL2 (2 << 9)
+static DEFINE_SPINLOCK(lock);
+static mali_plat_info_t* pmali_plat = NULL;
+static u32 mali_extr_backup = 0;
+static u32 mali_extr_sample_backup = 0;
+
+int mali_clock_init(mali_plat_info_t* mali_plat)
+{
+ u32 def_clk_data;
+ if (mali_plat == NULL) {
+ printk(" Mali platform data is NULL!!!\n");
+ return -1;
+ }
+
+ pmali_plat = mali_plat;
+ if (pmali_plat->have_switch) {
+ def_clk_data = pmali_plat->clk[pmali_plat->def_clock];
+ writel(def_clk_data | (def_clk_data << 16), (u32*)P_HHI_MALI_CLK_CNTL);
+ setbits_le32((u32)P_HHI_MALI_CLK_CNTL, 1 << 24);
+ setbits_le32((u32)P_HHI_MALI_CLK_CNTL, 1 << 8);
+ } else {
+ mali_clock_set(pmali_plat->def_clock);
+ }
+
+ mali_extr_backup = pmali_plat->clk[pmali_plat->clk_len - 1];
+ mali_extr_sample_backup = pmali_plat->clk_sample[pmali_plat->clk_len - 1];
+ return 0;
+}
+
+int mali_clock_critical(critical_t critical, size_t param)
+{
+ int ret = 0;
+ unsigned long flags;
+
+ spin_lock_irqsave(&lock, flags);
+ ret = critical(param);
+ spin_unlock_irqrestore(&lock, flags);
+ return ret;
+}
+
+static int critical_clock_set(size_t param)
+{
+ unsigned int idx = param;
+ if (pmali_plat->have_switch) {
+ u32 clk_value;
+ setbits_le32((u32)P_HHI_MALI_CLK_CNTL, 1 << 31);
+ clk_value = readl((u32 *)P_HHI_MALI_CLK_CNTL) & 0xffff0000;
+ clk_value = clk_value | pmali_plat->clk[idx] | (1 << 8);
+ writel(clk_value, (u32*)P_HHI_MALI_CLK_CNTL);
+ clrbits_le32((u32)P_HHI_MALI_CLK_CNTL, 1 << 31);
+ } else {
+ clrbits_le32((u32)P_HHI_MALI_CLK_CNTL, 1 << 8);
+ clrbits_le32((u32)P_HHI_MALI_CLK_CNTL, (0x7F | (0x7 << 9)));
+ writel(pmali_plat->clk[idx], (u32*)P_HHI_MALI_CLK_CNTL);
+ setbits_le32((u32)P_HHI_MALI_CLK_CNTL, 1 << 8);
+ }
+ return 0;
+}
+
+int mali_clock_set(unsigned int clock)
+{
+ return mali_clock_critical(critical_clock_set, (size_t)clock);
+}
+
+void disable_clock(void)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&lock, flags);
+ clrbits_le32((u32)P_HHI_MALI_CLK_CNTL, 1 << 8);
+ spin_unlock_irqrestore(&lock, flags);
+}
+
+void enable_clock(void)
+{
+ u32 ret;
+ unsigned long flags;
+
+ spin_lock_irqsave(&lock, flags);
+ setbits_le32((u32)P_HHI_MALI_CLK_CNTL, 1 << 8);
+ ret = readl((u32 *)P_HHI_MALI_CLK_CNTL) & (1 << 8);
+ spin_unlock_irqrestore(&lock, flags);
+}
+
+u32 get_mali_freq(u32 idx)
+{
+ if (!mali_pm_statue) {
+ return pmali_plat->clk_sample[idx];
+ } else {
+ return 0;
+ }
+}
+
+void set_str_src(u32 data)
+{
+ if (data == 11) {
+ writel(0x0004d000, (u32*)P_HHI_MPLL_CNTL9);
+ } else if (data > 11) {
+ writel(data, (u32*)P_HHI_MPLL_CNTL9);
+ }
+ if (data == 0) {
+ pmali_plat->clk[pmali_plat->clk_len - 1] = mali_extr_backup;
+ pmali_plat->clk_sample[pmali_plat->clk_len - 1] = mali_extr_sample_backup;
+ } else if (data > 10) {
+ pmali_plat->clk_sample[pmali_plat->clk_len - 1] = 600;
+ pmali_plat->clk[pmali_plat->clk_len - 1] = FCLK_MPLL2;
+ }
+}
+#endif
--- /dev/null
+#ifndef _MALI_CLOCK_H_
+#define _MALI_CLOCK_H_
+
+typedef int (*critical_t)(size_t param);
+int mali_clock_critical(critical_t critical, size_t param);
+
+int mali_clock_init(mali_plat_info_t*);
+int mali_clock_set(unsigned int index);
+void disable_clock(void);
+void enable_clock(void);
+u32 get_mali_freq(u32 idx);
+void set_str_src(u32 data);
+#endif /* _MALI_CLOCK_H_ */
--- /dev/null
+/*
+ * mali_platform.h
+ *
+ * Created on: Nov 8, 2013
+ * Author: amlogic
+ */
+
+#include <linux/kernel.h>
+#ifndef MALI_PLATFORM_H_
+#define MALI_PLATFORM_H_
+
+extern u32 mali_gp_reset_fail;
+extern u32 mali_core_timeout;
+
+#endif /* MALI_PLATFORM_H_ */
--- /dev/null
+#include <linux/platform_device.h>
+#include <linux/version.h>
+#include <linux/pm.h>
+#include <linux/of.h>
+#include <linux/module.h> /* kernel module definitions */
+#include <linux/ioport.h> /* request_mem_region */
+#include <linux/slab.h>
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
+#include <mach/register.h>
+#include <mach/irqs.h>
+#include <mach/io.h>
+#endif
+#include "meson_main.h"
+#include <common/mali_kernel_common.h>
+#include <common/mali_osk_profiling.h>
+#include <common/mali_pmu.h>
+#include <linux/mali/mali_utgard.h>
+
+static int mali_os_suspend(struct device *device)
+{
+ int ret = 0;
+
+ MALI_DEBUG_PRINT(4, ("mali_os_suspend() called\n"));
+ ret = mali_deep_suspend(device);
+
+ return ret;
+}
+
+static int mali_os_resume(struct device *device)
+{
+ int ret = 0;
+
+ MALI_DEBUG_PRINT(4, ("mali_os_resume() called\n"));
+
+ ret = mali_deep_resume(device);
+
+ return ret;
+}
+
+static int mali_os_freeze(struct device *device)
+{
+ int ret = 0;
+
+ MALI_DEBUG_PRINT(4, ("mali_os_freeze() called\n"));
+
+ if (NULL != device->driver &&
+ NULL != device->driver->pm &&
+ NULL != device->driver->pm->freeze)
+ {
+ /* Need to notify Mali driver about this event */
+ ret = device->driver->pm->freeze(device);
+ }
+
+ return ret;
+}
+//copy from r4p1 linux/mali_pmu_power_up_down.c
+#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
+static int mali_pmu_powerup(void)
+{
+ struct mali_pmu_core *pmu = mali_pmu_get_global_pmu_core();
+
+ MALI_DEBUG_PRINT(5, ("Mali PMU: Power up\n"));
+
+ MALI_DEBUG_ASSERT_POINTER(pmu);
+ if (NULL == pmu) {
+ return -ENXIO;
+ }
+
+ mali_pmu_power_up_all(pmu);
+
+ return 0;
+}
+#endif
+
+static int mali_os_thaw(struct device *device)
+{
+ int ret = 0;
+
+ MALI_DEBUG_PRINT(4, ("mali_os_thaw() called\n"));
+#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
+ enable_clock();
+ mali_pmu_powerup();
+#endif
+
+ if (NULL != device->driver &&
+ NULL != device->driver->pm &&
+ NULL != device->driver->pm->thaw)
+ {
+ /* Need to notify Mali driver about this event */
+ ret = device->driver->pm->thaw(device);
+ }
+
+ return ret;
+}
+
+static int mali_os_restore(struct device *device)
+{
+ MALI_DEBUG_PRINT(4, ("mali_os_thaw() called\n"));
+#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
+ mali_dev_restore();
+#endif
+ return mali_os_resume(device);
+}
+
+#ifdef CONFIG_PM_RUNTIME
+#if 0
+static int mali_runtime_suspend(struct device *device)
+{
+ int ret = 0;
+
+ MALI_DEBUG_PRINT(4, ("mali_runtime_suspend() called\n"));
+ ret = mali_light_suspend(device);
+
+ return ret;
+}
+
+static int mali_runtime_resume(struct device *device)
+{
+ int ret = 0;
+
+ MALI_DEBUG_PRINT(4, ("mali_run time_resume() called\n"));
+ ret = mali_light_resume(device);
+
+ return ret;
+}
+
+static int mali_runtime_idle(struct device *device)
+{
+ MALI_DEBUG_PRINT(4, ("mali_runtime_idle() called\n"));
+
+ if (NULL != device->driver &&
+ NULL != device->driver->pm &&
+ NULL != device->driver->pm->runtime_idle)
+ {
+ /* Need to notify Mali driver about this event */
+ int ret = device->driver->pm->runtime_idle(device);
+ if (0 != ret)
+ {
+ return ret;
+ }
+ }
+
+ pm_runtime_suspend(device);
+
+ return 0;
+}
+#endif
+#endif
+
+static struct dev_pm_ops mali_gpu_device_type_pm_ops =
+{
+ .suspend = mali_os_suspend,
+ .resume = mali_os_resume,
+ .freeze = mali_os_freeze,
+ .thaw = mali_os_thaw,
+ .restore = mali_os_restore,
+#if 0//def CONFIG_PM_RUNTIME
+ .runtime_suspend = mali_runtime_suspend,
+ .runtime_resume = mali_runtime_resume,
+ .runtime_idle = mali_runtime_idle,
+#endif
+};
+
+struct device_type mali_pm_device =
+{
+ .pm = &mali_gpu_device_type_pm_ops,
+};
--- /dev/null
+/*
+ * Copyright (C) 2013 ARM Limited. All rights reserved.
+ *
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ *
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+/**
+ * @file arm_core_scaling.h
+ * Example core scaling policy.
+ */
+
+#ifndef __ARM_CORE_SCALING_H__
+#define __ARM_CORE_SCALING_H__
+
+#include <linux/types.h>
+#include <linux/workqueue.h>
+#include <linux/clk-provider.h>
+#include <linux/clk.h>
+
+enum mali_scale_mode_t {
+ MALI_PP_SCALING = 0,
+ MALI_PP_FS_SCALING,
+ MALI_SCALING_DISABLE,
+ MALI_TURBO_MODE,
+ MALI_SCALING_MODE_MAX
+};
+
+typedef struct mali_dvfs_threshold_table {
+ uint32_t freq_index;
+ uint32_t voltage;
+ uint32_t keep_count;
+ uint32_t downthreshold;
+ uint32_t upthreshold;
+ uint32_t clk_freq;
+ const char *clk_parent;
+ struct clk *clkp_handle;
+ uint32_t clkp_freq;
+} mali_dvfs_threshold_table;
+
+/**
+ * restrictions on frequency and number of pp.
+ */
+typedef struct mali_scale_info_t {
+ u32 minpp;
+ u32 maxpp;
+ u32 minclk;
+ u32 maxclk;
+} mali_scale_info_t;
+
+/**
+ * Platform spesific data for meson chips.
+ */
+typedef struct mali_plat_info_t {
+ u32 cfg_pp; /* number of pp. */
+ u32 cfg_min_pp;
+ u32 turbo_clock; /* reserved clock src. */
+ u32 def_clock; /* gpu clock used most of time.*/
+ u32 cfg_clock; /* max clock could be used.*/
+ u32 cfg_clock_bkup; /* same as cfg_clock, for backup. */
+ u32 cfg_min_clock;
+
+ u32 sc_mpp; /* number of pp used most of time.*/
+ u32 bst_gpu; /* threshold for boosting gpu. */
+ u32 bst_pp; /* threshold for boosting PP. */
+
+ u32 *clk;
+ u32 *clk_sample;
+ u32 clk_len;
+ u32 have_switch; /* have clock gate switch or not. */
+
+ mali_dvfs_threshold_table *dvfs_table;
+ //struct mali_gpu_clk_item *clk_items;
+ u32 dvfs_table_size;
+
+ mali_scale_info_t scale_info;
+ u32 maxclk_sysfs;
+ u32 maxpp_sysfs;
+
+ /* set upper limit of pp or frequency, for THERMAL thermal or band width saving.*/
+ u32 limit_on;
+
+ /* for boost up gpu by user. */
+ void (*plat_preheat)(void);
+
+#if 0
+ struct platform_device *pdev;
+ void __iomem *reg_base_hiubus;
+ void __iomem *reg_base_aobus;
+ struct work_struct wq_work;
+ struct clk *clk_mali;
+ struct clk *clk_mali_0;
+ struct clk *clk_mali_1;
+#endif
+} mali_plat_info_t;
+mali_plat_info_t* get_mali_plat_data(void);
+
+/**
+ * Initialize core scaling policy.
+ *
+ * @note The core scaling policy will assume that all PP cores are on initially.
+ *
+ * @param num_pp_cores Total number of PP cores.
+ */
+int mali_core_scaling_init(mali_plat_info_t*);
+
+/**
+ * Terminate core scaling policy.
+ */
+void mali_core_scaling_term(void);
+
+/**
+ * cancel and flush scaling job queue.
+ */
+void flush_scaling_job(void);
+
+/* get current state(pp, clk). */
+void get_mali_rt_clkpp(u32* clk, u32* pp);
+u32 set_mali_rt_clkpp(u32 clk, u32 pp, u32 flush);
+void revise_mali_rt(void);
+/* get max gpu clk level of this chip*/
+//int get_gpu_max_clk_level(void);
+
+/* get or set the scale mode. */
+u32 get_mali_schel_mode(void);
+void set_mali_schel_mode(u32 mode);
+
+/* for frequency reporter in DS-5 streamline. */
+u32 get_current_frequency(void);
+//void mali_dev_freeze(void);
+void mali_dev_restore(void);
+
+extern int mali_pm_statue;
+#endif /* __ARM_CORE_SCALING_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2010, 2012-2013 ARM Limited. All rights reserved.
+ *
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ *
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+#include <linux/version.h>
+#include <linux/dma-mapping.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/pm.h>
+#include <linux/of.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
+#include <mach/register.h>
+#include <mach/irqs.h>
+#include <mach/io.h>
+#endif
+#include <asm/io.h>
+
+#include "meson_main.h"
+#include <linux/mali/mali_utgard.h>
+#include "mali_kernel_common.h"
+#include "common/mali_pmu.h"
+#include "common/mali_osk_profiling.h"
+
+int mali_pm_statue = 0;
+u32 mali_gp_reset_fail = 0;
+module_param(mali_gp_reset_fail, int, S_IRUSR | S_IWUSR | S_IWGRP | S_IRGRP | S_IROTH); /* rw-rw-r-- */
+MODULE_PARM_DESC(mali_gp_reset_fail, "times of failed to reset GP");
+u32 mali_core_timeout = 0;
+module_param(mali_core_timeout, int, S_IRUSR | S_IWUSR | S_IWGRP | S_IRGRP | S_IROTH); /* rw-rw-r-- */
+MODULE_PARM_DESC(mali_core_timeout, "times of failed to reset GP");
+
+static struct mali_gpu_device_data mali_gpu_data =
+{
+ .shared_mem_size = 1024 * 1024 * 1024,
+ .max_job_runtime = 60000, /* 60 seconds */
+ .pmu_switch_delay = 0xFFFF, /* do not have to be this high on FPGA, but it is good for testing to have a delay */
+#if defined(CONFIG_ARCH_MESON8B)||defined(CONFIG_ARCH_MESONG9BB)
+ .pmu_domain_config = {0x1, 0x2, 0x4, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x1, 0x2, 0x0},
+#else
+ .pmu_domain_config = {0x1, 0x2, 0x4, 0x4,
+ 0x0, 0x8, 0x8, 0x8,
+ 0x0, 0x1, 0x2, 0x8},
+#endif
+};
+
+static void mali_platform_device_release(struct device *device);
+static struct platform_device mali_gpu_device =
+{
+ .name = MALI_GPU_NAME_UTGARD,
+ .id = 0,
+ .dev.release = mali_platform_device_release,
+ .dev.coherent_dma_mask = DMA_BIT_MASK(32),
+ .dev.platform_data = &mali_gpu_data,
+ .dev.type = &mali_pm_device, /* We should probably use the pm_domain instead of type on newer kernels */
+};
+
+int mali_pdev_pre_init(struct platform_device* ptr_plt_dev)
+{
+ MALI_DEBUG_PRINT(4, ("mali_platform_device_register() called\n"));
+ if (mali_gpu_data.shared_mem_size < 10) {
+ MALI_DEBUG_PRINT(2, ("mali os memory didn't configered, set to default(512M)\n"));
+ mali_gpu_data.shared_mem_size = 1024 * 1024 *1024;
+ }
+ return mali_meson_init_start(ptr_plt_dev);
+}
+
+void mali_pdev_post_init(struct platform_device* pdev)
+{
+ mali_gp_reset_fail = 0;
+ mali_core_timeout = 0;
+#ifdef CONFIG_PM_RUNTIME
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
+ pm_runtime_set_autosuspend_delay(&(pdev->dev), 1000);
+ pm_runtime_use_autosuspend(&(pdev->dev));
+#endif
+ pm_runtime_enable(&(pdev->dev));
+#endif
+ mali_meson_init_finish(pdev);
+}
+
+int mali_pdev_dts_init(struct platform_device* mali_gpu_device)
+{
+ struct device_node *cfg_node = mali_gpu_device->dev.of_node;
+ struct device_node *child;
+ u32 prop_value;
+ int err;
+
+ for_each_child_of_node(cfg_node, child) {
+ err = of_property_read_u32(child, "shared_memory", &prop_value);
+ if (err == 0) {
+ MALI_DEBUG_PRINT(2, ("shared_memory configurate %d\n", prop_value));
+ mali_gpu_data.shared_mem_size = prop_value * 1024 * 1024;
+ }
+ }
+
+ err = mali_pdev_pre_init(mali_gpu_device);
+ if (err == 0)
+ mali_pdev_post_init(mali_gpu_device);
+ return err;
+}
+
+int mali_platform_device_register(void)
+{
+ int err = -1;
+ err = mali_pdev_pre_init(&mali_gpu_device);
+ if (err == 0) {
+ err = platform_device_register(&mali_gpu_device);
+ if (0 == err)
+ mali_pdev_post_init(&mali_gpu_device);
+ }
+ return err;
+}
+
+void mali_platform_device_unregister(void)
+{
+ MALI_DEBUG_PRINT(4, ("mali_platform_device_unregister() called\n"));
+ mali_core_scaling_term();
+ platform_device_unregister(&mali_gpu_device);
+ platform_device_put(&mali_gpu_device);
+}
+
+static void mali_platform_device_release(struct device *device)
+{
+ MALI_DEBUG_PRINT(4, ("mali_platform_device_release() called\n"));
+}
+
+
--- /dev/null
+/*
+ * mali_platform.h
+ *
+ * Created on: Nov 8, 2013
+ * Author: amlogic
+ */
+
+#ifndef MESON_MAIN_H_
+#define MESON_MAIN_H_
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#ifdef CONFIG_PM_RUNTIME
+#include <linux/pm_runtime.h>
+#endif
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
+#include <mach/cpu.h>
+#endif
+
+#include "mali_scaling.h"
+#include "mali_clock.h"
+
+extern struct device_type mali_pm_device;
+extern int mali_pm_statue;
+
+u32 set_max_mali_freq(u32 idx);
+u32 get_max_mali_freq(void);
+
+int mali_meson_init_start(struct platform_device* ptr_plt_dev);
+int mali_meson_init_finish(struct platform_device* ptr_plt_dev);
+int mali_meson_uninit(struct platform_device* ptr_plt_dev);
+int mali_light_suspend(struct device *device);
+int mali_light_resume(struct device *device);
+int mali_deep_suspend(struct device *device);
+int mali_deep_resume(struct device *device);
+
+#endif /* MESON_MAIN_H_ */
--- /dev/null
+/*******************************************************************
+ *
+ * Copyright C 2013 by Amlogic, Inc. All Rights Reserved.
+ *
+ * Description:
+ *
+ * Author: Amlogic Software
+ * Created: 2010/4/1 19:46
+ *
+ *******************************************************************/
+/* Standard Linux headers */
+#include <linux/platform_device.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/string.h>
+#include <linux/slab.h>
+#include <linux/list.h>
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
+#include <mach/io.h>
+#include <plat/io.h>
+#include <asm/io.h>
+#endif
+
+#include <linux/mali/mali_utgard.h>
+#include <common/mali_kernel_common.h>
+#include <common/mali_pmu.h>
+//include "mali_pp_scheduler.h"
+#include "meson_main.h"
+
+#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
+static ssize_t domain_stat_read(struct class *class,
+ struct class_attribute *attr, char *buf)
+{
+#if 0
+ unsigned int val;
+ mali_plat_info_t* pmali_plat = get_mali_plat_data();
+
+ val = readl(pmali_plat->reg_base_aobus + 0xf0) & 0xff;
+ return sprintf(buf, "%x\n", val>>4);
+#else
+ return 0;
+#endif
+}
+
+#define PREHEAT_CMD "preheat"
+#define PLL2_CMD "mpl2" /* mpl2 [11] or [0xxxxxxx] */
+#define SCMPP_CMD "scmpp" /* scmpp [number of pp your want in most of time]. */
+#define BSTGPU_CMD "bstgpu" /* bstgpu [0-256] */
+#define BSTPP_CMD "bstpp" /* bstpp [0-256] */
+#define LIMIT_CMD "lmt" /* lmt [0 or 1] */
+#define MAX_TOKEN 20
+#define FULL_UTILIZATION 256
+
+static ssize_t mpgpu_write(struct class *class,
+ struct class_attribute *attr, const char *buf, size_t count)
+{
+ char *pstart, *cprt = NULL;
+ u32 val = 0;
+ mali_plat_info_t* pmali_plat = get_mali_plat_data();
+
+ cprt = skip_spaces(buf);
+ pstart = strsep(&cprt," ");
+ if (strlen(pstart) < 1)
+ goto quit;
+
+ if (!strncmp(pstart, PREHEAT_CMD, MAX_TOKEN)) {
+ if (pmali_plat->plat_preheat) {
+ pmali_plat->plat_preheat();
+ }
+ } else if (!strncmp(pstart, PLL2_CMD, MAX_TOKEN)) {
+ int base = 10;
+ if ((strlen(cprt) > 2) && (cprt[0] == '0') &&
+ (cprt[1] == 'x' || cprt[1] == 'X'))
+ base = 16;
+ if (kstrtouint(cprt, base, &val) <0)
+ goto quit;
+ if (val < 11)
+ pmali_plat->cfg_clock = pmali_plat->cfg_clock_bkup;
+ else
+ pmali_plat->cfg_clock = pmali_plat->turbo_clock;
+ pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
+ set_str_src(val);
+ } else if (!strncmp(pstart, SCMPP_CMD, MAX_TOKEN)) {
+ if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
+ goto quit;
+ if ((val > 0) && (val < pmali_plat->cfg_pp)) {
+ pmali_plat->sc_mpp = val;
+ }
+ } else if (!strncmp(pstart, BSTGPU_CMD, MAX_TOKEN)) {
+ if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
+ goto quit;
+ if ((val > 0) && (val < FULL_UTILIZATION)) {
+ pmali_plat->bst_gpu = val;
+ }
+ } else if (!strncmp(pstart, BSTPP_CMD, MAX_TOKEN)) {
+ if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
+ goto quit;
+ if ((val > 0) && (val < FULL_UTILIZATION)) {
+ pmali_plat->bst_pp = val;
+ }
+ } else if (!strncmp(pstart, LIMIT_CMD, MAX_TOKEN)) {
+ if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
+ goto quit;
+
+ if (val < 2) {
+ pmali_plat->limit_on = val;
+ if (val == 0) {
+ pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
+ pmali_plat->scale_info.maxpp = pmali_plat->cfg_pp;
+ revise_mali_rt();
+ }
+ }
+ }
+quit:
+ return count;
+}
+
+static ssize_t scale_mode_read(struct class *class,
+ struct class_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", get_mali_schel_mode());
+}
+
+static ssize_t scale_mode_write(struct class *class,
+ struct class_attribute *attr, const char *buf, size_t count)
+{
+ int ret;
+ unsigned int val;
+
+ ret = kstrtouint(buf, 10, &val);
+ if (0 != ret)
+ {
+ return -EINVAL;
+ }
+
+ set_mali_schel_mode(val);
+
+ return count;
+}
+
+static ssize_t max_pp_read(struct class *class,
+ struct class_attribute *attr, char *buf)
+{
+#if 0
+ mali_plat_info_t* pmali_plat = get_mali_plat_data();
+ printk("maxpp:%d, maxpp_sysfs:%d, total=%d\n",
+ pmali_plat->scale_info.maxpp, pmali_plat->maxpp_sysfs,
+ pmali_plat->cfg_pp);
+ return sprintf(buf, "%d\n", pmali_plat->cfg_pp);
+#else
+ return 0;
+#endif
+}
+
+static ssize_t max_pp_write(struct class *class,
+ struct class_attribute *attr, const char *buf, size_t count)
+{
+ int ret;
+ unsigned int val;
+ mali_plat_info_t* pmali_plat;
+ mali_scale_info_t* pinfo;
+
+ pmali_plat = get_mali_plat_data();
+ pinfo = &pmali_plat->scale_info;
+
+ ret = kstrtouint(buf, 10, &val);
+ if ((0 != ret) || (val > pmali_plat->cfg_pp) || (val < pinfo->minpp))
+ return -EINVAL;
+
+ pmali_plat->maxpp_sysfs = val;
+ pinfo->maxpp = val;
+ revise_mali_rt();
+
+ return count;
+}
+
+static ssize_t min_pp_read(struct class *class,
+ struct class_attribute *attr, char *buf)
+{
+ mali_plat_info_t* pmali_plat = get_mali_plat_data();
+ return sprintf(buf, "%d\n", pmali_plat->scale_info.minpp);
+}
+
+static ssize_t min_pp_write(struct class *class,
+ struct class_attribute *attr, const char *buf, size_t count)
+{
+ int ret;
+ unsigned int val;
+ mali_plat_info_t* pmali_plat;
+ mali_scale_info_t* pinfo;
+
+ pmali_plat = get_mali_plat_data();
+ pinfo = &pmali_plat->scale_info;
+
+ ret = kstrtouint(buf, 10, &val);
+ if ((0 != ret) || (val > pinfo->maxpp) || (val < 1))
+ return -EINVAL;
+
+ pinfo->minpp = val;
+ revise_mali_rt();
+
+ return count;
+}
+
+static ssize_t max_freq_read(struct class *class,
+ struct class_attribute *attr, char *buf)
+{
+#if 0
+ mali_plat_info_t* pmali_plat = get_mali_plat_data();
+ printk("maxclk:%d, maxclk_sys:%d, max gpu level=%d\n",
+ pmali_plat->scale_info.maxclk, pmali_plat->maxclk_sysfs, get_gpu_max_clk_level());
+ return sprintf(buf, "%d\n", get_gpu_max_clk_level());
+#else
+ return 0;
+#endif
+}
+
+static ssize_t max_freq_write(struct class *class,
+ struct class_attribute *attr, const char *buf, size_t count)
+{
+ int ret;
+ unsigned int val;
+ mali_plat_info_t* pmali_plat;
+ mali_scale_info_t* pinfo;
+
+ pmali_plat = get_mali_plat_data();
+ pinfo = &pmali_plat->scale_info;
+
+ ret = kstrtouint(buf, 10, &val);
+ if ((0 != ret) || (val > pmali_plat->cfg_clock) || (val < pinfo->minclk))
+ return -EINVAL;
+
+ pmali_plat->maxclk_sysfs = val;
+ pinfo->maxclk = val;
+ revise_mali_rt();
+
+ return count;
+}
+
+static ssize_t min_freq_read(struct class *class,
+ struct class_attribute *attr, char *buf)
+{
+ mali_plat_info_t* pmali_plat = get_mali_plat_data();
+ return sprintf(buf, "%d\n", pmali_plat->scale_info.minclk);
+}
+
+static ssize_t min_freq_write(struct class *class,
+ struct class_attribute *attr, const char *buf, size_t count)
+{
+ int ret;
+ unsigned int val;
+ mali_plat_info_t* pmali_plat;
+ mali_scale_info_t* pinfo;
+
+ pmali_plat = get_mali_plat_data();
+ pinfo = &pmali_plat->scale_info;
+
+ ret = kstrtouint(buf, 10, &val);
+ if ((0 != ret) || (val > pinfo->maxclk))
+ return -EINVAL;
+
+ pinfo->minclk = val;
+ revise_mali_rt();
+
+ return count;
+}
+
+static ssize_t freq_read(struct class *class,
+ struct class_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", get_current_frequency());
+}
+
+static ssize_t freq_write(struct class *class,
+ struct class_attribute *attr, const char *buf, size_t count)
+{
+ int ret;
+ unsigned int val;
+ u32 clk, pp;
+ get_mali_rt_clkpp(&clk, &pp);
+
+ ret = kstrtouint(buf, 10, &val);
+ if (0 != ret)
+ return -EINVAL;
+
+ set_mali_rt_clkpp(val, pp, 1);
+
+ return count;
+}
+
+static ssize_t current_pp_read(struct class *class,
+ struct class_attribute *attr, char *buf)
+{
+ u32 clk, pp;
+ get_mali_rt_clkpp(&clk, &pp);
+ return sprintf(buf, "%d\n", pp);
+}
+
+static ssize_t current_pp_write(struct class *class,
+ struct class_attribute *attr, const char *buf, size_t count)
+{
+ int ret;
+ unsigned int val;
+ u32 clk, pp;
+
+ get_mali_rt_clkpp(&clk, &pp);
+ ret = kstrtouint(buf, 10, &val);
+ if (0 != ret)
+ {
+ return -EINVAL;
+ }
+
+ ret = kstrtouint(buf, 10, &val);
+ if (0 != ret)
+ return -EINVAL;
+
+ set_mali_rt_clkpp(clk, val, 1);
+
+ return count;
+}
+
+static struct class_attribute mali_class_attrs[] = {
+ __ATTR(domain_stat, 0644, domain_stat_read, NULL),
+ __ATTR(mpgpucmd, 0644, NULL, mpgpu_write),
+ __ATTR(scale_mode, 0644, scale_mode_read, scale_mode_write),
+ __ATTR(min_freq, 0644, min_freq_read, min_freq_write),
+ __ATTR(max_freq, 0644, max_freq_read, max_freq_write),
+ __ATTR(min_pp, 0644, min_pp_read, min_pp_write),
+ __ATTR(max_pp, 0644, max_pp_read, max_pp_write),
+ __ATTR(cur_freq, 0644, freq_read, freq_write),
+ __ATTR(cur_pp, 0644, current_pp_read, current_pp_write),
+};
+
+static struct class mpgpu_class = {
+ .name = "mpgpu",
+};
+#endif
+
+int mpgpu_class_init(void)
+{
+#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
+ int ret = 0;
+ int i;
+ int attr_num = ARRAY_SIZE(mali_class_attrs);
+
+ ret = class_register(&mpgpu_class);
+ if (ret) {
+ printk(KERN_ERR "%s: class_register failed\n", __func__);
+ return ret;
+ }
+ for (i = 0; i< attr_num; i++) {
+ ret = class_create_file(&mpgpu_class, &mali_class_attrs[i]);
+ if (ret) {
+ printk(KERN_ERR "%d ST: class item failed to register\n", i);
+ }
+ }
+ return ret;
+#else
+ return 0;
+#endif
+}
+
+void mpgpu_class_exit(void)
+{
+#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
+ class_unregister(&mpgpu_class);
+#endif
+}
+
--- /dev/null
+/*
+ * platform.c
+ *
+ * clock source setting and resource config
+ *
+ * Created on: Dec 4, 2013
+ * Author: amlogic
+ */
+
+#include <linux/platform_device.h>
+#include <linux/version.h>
+#include <linux/pm.h>
+#include <linux/of.h>
+#include <linux/module.h> /* kernel module definitions */
+#include <linux/ioport.h> /* request_mem_region */
+#include <linux/slab.h>
+#include <mach/register.h>
+#include <mach/irqs.h>
+#include <mach/io.h>
+#include <asm/io.h>
+#include <linux/mali/mali_utgard.h>
+
+#include <common/mali_kernel_common.h>
+#include <common/mali_osk_profiling.h>
+#include <common/mali_pmu.h>
+
+#include "meson_main.h"
+
+/*
+ * For Meson 8TVD.
+ *
+ */
+
+#define CFG_PP 2
+#define CFG_CLOCK 3
+#define CFG_MIN_PP 1
+#define CFG_MIN_CLOCK 0
+
+/* fclk is 2Ghz. */
+#define FCLK_DEV5 (7 << 9) /* 400 Mhz */
+#define FCLK_DEV3 (6 << 9) /* 666 Mhz */
+#define FCLK_DEV2 (5 << 9) /* 1000 Mhz */
+#define FCLK_DEV7 (4 << 9) /* 285 Mhz */
+
+u32 mali_dvfs_clk[] = {
+ FCLK_DEV7 | 9, /* 100 Mhz */
+ FCLK_DEV2 | 4, /* 200 Mhz */
+ FCLK_DEV3 | 1, /* 333 Mhz */
+ FCLK_DEV5 | 0, /* 400 Mhz */
+};
+
+u32 mali_dvfs_clk_sample[] = {
+ 100, /* 182.1 Mhz */
+ 200, /* 318.7 Mhz */
+ 333, /* 425 Mhz */
+ 400, /* 510 Mhz */
+};
+
+static mali_plat_info_t mali_plat_data = {
+ .cfg_pp = CFG_PP, /* number of pp. */
+ .cfg_min_pp = CFG_MIN_PP,
+ .def_clock = CFG_CLOCK, /* gpu clock used most of time.*/
+ .cfg_clock = CFG_CLOCK, /* max gpu clock. */
+ .cfg_min_clock = CFG_MIN_CLOCK,
+
+ .clk = mali_dvfs_clk, /* clock source table. */
+ .clk_sample = mali_dvfs_clk_sample, /* freqency table for show. */
+ .clk_len = sizeof(mali_dvfs_clk) / sizeof(mali_dvfs_clk[0]),
+ .have_switch = 0,
+};
+
+#define MALI_USER_PP0 AM_IRQ4(31)
+
+static struct resource mali_gpu_resources[] =
+{
+MALI_GPU_RESOURCES_MALI450_MP2_PMU(0xC9140000, INT_MALI_GP, INT_MALI_GP_MMU,
+ MALI_USER_PP0, INT_MALI_PP_MMU,
+ INT_MALI_PP1, INT_MALI_PP_MMU1,
+ INT_MALI_PP)
+};
+
+int mali_meson_init_start(struct platform_device* ptr_plt_dev)
+{
+ ptr_plt_dev->num_resources = ARRAY_SIZE(mali_gpu_resources);
+ ptr_plt_dev->resource = mali_gpu_resources;
+ return mali_clock_init(&mali_plat_data);
+}
+
+int mali_meson_init_finish(struct platform_device* ptr_plt_dev)
+{
+ return 0;
+}
+
+int mali_meson_uninit(struct platform_device* ptr_plt_dev)
+{
+ return 0;
+}
+
+static int mali_cri_pmu_on_off(size_t param)
+{
+ struct mali_pmu_core *pmu;
+
+ MALI_DEBUG_PRINT(4, ("mali_os_suspend() called\n"));
+ pmu = mali_pmu_get_global_pmu_core();
+ if (param == 0)
+ mali_pmu_power_down_all(pmu);
+ else
+ mali_pmu_power_up_all(pmu);
+ return 0;
+}
+
+int mali_light_suspend(struct device *device)
+{
+ int ret = 0;
+#ifdef CONFIG_MALI400_PROFILING
+ _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
+ MALI_PROFILING_EVENT_CHANNEL_GPU |
+ MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
+ 0, 0, 0, 0, 0);
+#endif
+ if (NULL != device->driver &&
+ NULL != device->driver->pm &&
+ NULL != device->driver->pm->runtime_suspend)
+ {
+ /* Need to notify Mali driver about this event */
+ ret = device->driver->pm->runtime_suspend(device);
+ }
+
+ /* clock scaling. Kasin..*/
+ mali_clock_critical(mali_cri_pmu_on_off, 0);
+ disable_clock();
+ return ret;
+}
+
+int mali_light_resume(struct device *device)
+{
+ int ret = 0;
+ /* clock scaling. Kasin..*/
+ enable_clock();
+
+ mali_clock_critical(mali_cri_pmu_on_off, 1);
+#ifdef CONFIG_MALI400_PROFILING
+ _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
+ MALI_PROFILING_EVENT_CHANNEL_GPU |
+ MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
+ 0, 0, 0, 0, 0);
+#endif
+
+ if (NULL != device->driver &&
+ NULL != device->driver->pm &&
+ NULL != device->driver->pm->runtime_resume)
+ {
+ /* Need to notify Mali driver about this event */
+ ret = device->driver->pm->runtime_resume(device);
+ }
+ return ret;
+}
+
+int mali_deep_suspend(struct device *device)
+{
+ int ret = 0;
+ //enable_clock();
+ //flush_scaling_job();
+ if (NULL != device->driver &&
+ NULL != device->driver->pm &&
+ NULL != device->driver->pm->suspend)
+ {
+ /* Need to notify Mali driver about this event */
+ ret = device->driver->pm->suspend(device);
+ }
+
+ /* clock scaling off. Kasin... */
+ mali_clock_critical(mali_cri_pmu_on_off, 0);
+ disable_clock();
+ return ret;
+}
+
+int mali_deep_resume(struct device *device)
+{
+ int ret = 0;
+ /* clock scaling up. Kasin.. */
+ enable_clock();
+ mali_clock_critical(mali_cri_pmu_on_off, 1);
+ if (NULL != device->driver &&
+ NULL != device->driver->pm &&
+ NULL != device->driver->pm->resume)
+ {
+ /* Need to notify Mali driver about this event */
+ ret = device->driver->pm->resume(device);
+ }
+ return ret;
+
+}
+
+void mali_post_init(void)
+{
+}
--- /dev/null
+/*
+ * platform.c
+ *
+ * clock source setting and resource config
+ *
+ * Created on: Dec 4, 2013
+ * Author: amlogic
+ */
+
+#include <linux/platform_device.h>
+#include <linux/version.h>
+#include <linux/pm.h>
+#include <linux/of.h>
+#include <linux/module.h> /* kernel module definitions */
+#include <linux/ioport.h> /* request_mem_region */
+#include <linux/slab.h>
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
+#include <mach/register.h>
+#include <mach/irqs.h>
+#include <mach/io.h>
+#endif
+#include <asm/io.h>
+#include <linux/mali/mali_utgard.h>
+#ifdef CONFIG_GPU_THERMAL
+#include <linux/gpu_cooling.h>
+#include <linux/gpucore_cooling.h>
+#endif
+#include <common/mali_kernel_common.h>
+#include <common/mali_osk_profiling.h>
+#include <common/mali_pmu.h>
+
+#include "meson_main.h"
+
+/*
+ * For Meson 8 M2.
+ *
+ */
+
+#define CFG_PP 6
+#define CFG_CLOCK 3
+#define CFG_MIN_PP 1
+#define CFG_MIN_CLOCK 0
+
+/* fclk is 2550Mhz. */
+#define FCLK_DEV3 (6 << 9) /* 850 Mhz */
+#define FCLK_DEV4 (5 << 9) /* 637.5 Mhz */
+#define FCLK_DEV5 (7 << 9) /* 510 Mhz */
+#define FCLK_DEV7 (4 << 9) /* 364.3 Mhz */
+
+static u32 mali_dvfs_clk[] = {
+ FCLK_DEV7 | 1, /* 182.1 Mhz */
+ FCLK_DEV4 | 1, /* 318.7 Mhz */
+ FCLK_DEV3 | 1, /* 425 Mhz */
+ FCLK_DEV5 | 0, /* 510 Mhz */
+ FCLK_DEV4 | 0, /* 637.5 Mhz */
+};
+
+static u32 mali_dvfs_clk_sample[] = {
+ 182, /* 182.1 Mhz */
+ 319, /* 318.7 Mhz */
+ 425, /* 425 Mhz */
+ 510, /* 510 Mhz */
+ 637, /* 637.5 Mhz */
+};
+//////////////////////////////////////
+//for dvfs
+struct mali_gpu_clk_item meson_gpu_clk[] = {
+ {182, 1150}, /* 182.1 Mhz, 1150mV */
+ {319, 1150}, /* 318.7 Mhz */
+ {425, 1150}, /* 425 Mhz */
+ {510, 1150}, /* 510 Mhz */
+ {637, 1150}, /* 637.5 Mhz */
+};
+struct mali_gpu_clock meson_gpu_clk_info = {
+ .item = meson_gpu_clk,
+ .num_of_steps = ARRAY_SIZE(meson_gpu_clk),
+};
+static int cur_gpu_clk_index = 0;
+//////////////////////////////////////
+static mali_dvfs_threshold_table mali_dvfs_table[]={
+ { 0, 0, 3, 30, 80}, /* for 182.1 */
+ { 1, 1, 3, 40, 205}, /* for 318.7 */
+ { 2, 2, 3, 150, 215}, /* for 425.0 */
+ { 3, 3, 3, 170, 253}, /* for 510.0 */
+ { 4, 4, 3, 230, 255}, /* for 637.5 */
+ { 0, 0, 3, 0, 0}
+};
+
+static void mali_plat_preheat(void);
+static mali_plat_info_t mali_plat_data = {
+ .cfg_pp = CFG_PP, /* number of pp. */
+ .cfg_min_pp = CFG_MIN_PP,
+ .turbo_clock = 4, /* reserved clock src. */
+ .def_clock = 2, /* gpu clock used most of time.*/
+ .cfg_clock = CFG_CLOCK, /* max gpu clock. */
+ .cfg_clock_bkup = CFG_CLOCK,
+ .cfg_min_clock = CFG_MIN_CLOCK,
+
+ .sc_mpp = 3, /* number of pp used most of time.*/
+ .bst_gpu = 210, /* threshold for boosting gpu. */
+ .bst_pp = 160, /* threshold for boosting PP. */
+
+ .clk = mali_dvfs_clk, /* clock source table. */
+ .clk_sample = mali_dvfs_clk_sample, /* freqency table for show. */
+ .clk_len = sizeof(mali_dvfs_clk) / sizeof(mali_dvfs_clk[0]),
+ .have_switch = 1,
+
+ .dvfs_table = mali_dvfs_table, /* DVFS table. */
+ .dvfs_table_size = sizeof(mali_dvfs_table) / sizeof(mali_dvfs_threshold_table),
+
+ .scale_info = {
+ CFG_MIN_PP, /* minpp */
+ CFG_PP, /* maxpp, should be same as cfg_pp */
+ CFG_MIN_CLOCK, /* minclk */
+ CFG_CLOCK, /* maxclk should be same as cfg_clock */
+ },
+
+ .limit_on = 1,
+ .plat_preheat = mali_plat_preheat,
+};
+
+static void mali_plat_preheat(void)
+{
+#ifndef CONFIG_MALI_DVFS
+ u32 pre_fs;
+ u32 clk, pp;
+
+ if (get_mali_schel_mode() != MALI_PP_FS_SCALING)
+ return;
+
+ get_mali_rt_clkpp(&clk, &pp);
+ pre_fs = mali_plat_data.def_clock + 1;
+ if (clk < pre_fs)
+ clk = pre_fs;
+ if (pp < mali_plat_data.sc_mpp)
+ pp = mali_plat_data.sc_mpp;
+ set_mali_rt_clkpp(clk, pp, 1);
+#endif
+}
+
+mali_plat_info_t* get_mali_plat_data(void) {
+ return &mali_plat_data;
+}
+
+int get_mali_freq_level(int freq)
+{
+ int i = 0, level = -1;
+ int mali_freq_num;
+
+ if (freq < 0)
+ return level;
+
+ mali_freq_num = mali_plat_data.dvfs_table_size - 1;
+ if (freq < mali_plat_data.clk_sample[0])
+ level = mali_freq_num-1;
+ if (freq >= mali_plat_data.clk_sample[mali_freq_num - 1])
+ level = 0;
+ for (i=0; i<mali_freq_num - 1 ;i++) {
+ if (freq >= mali_plat_data.clk_sample[i] && freq < mali_plat_data.clk_sample[i + 1]) {
+ level = i;
+ level = mali_freq_num-level - 1;
+ break;
+ }
+ }
+ return level;
+}
+
+unsigned int get_mali_max_level(void)
+{
+ return mali_plat_data.dvfs_table_size - 1;
+}
+
+static struct resource mali_gpu_resources[] =
+{
+ MALI_GPU_RESOURCES_MALI450_MP6_PMU(IO_MALI_APB_PHY_BASE, INT_MALI_GP, INT_MALI_GP_MMU,
+ INT_MALI_PP0, INT_MALI_PP0_MMU,
+ INT_MALI_PP1, INT_MALI_PP1_MMU,
+ INT_MALI_PP2, INT_MALI_PP2_MMU,
+ INT_MALI_PP4, INT_MALI_PP4_MMU,
+ INT_MALI_PP5, INT_MALI_PP5_MMU,
+ INT_MALI_PP6, INT_MALI_PP6_MMU,
+ INT_MALI_PP)
+};
+
+#ifdef CONFIG_GPU_THERMAL
+static void set_limit_mali_freq(u32 idx)
+{
+ if (mali_plat_data.limit_on == 0)
+ return;
+ if (idx > mali_plat_data.turbo_clock || idx < mali_plat_data.scale_info.minclk)
+ return;
+ mali_plat_data.scale_info.maxclk= idx;
+ revise_mali_rt();
+}
+
+static u32 get_limit_mali_freq(void)
+{
+ return mali_plat_data.scale_info.maxclk;
+}
+#endif
+
+#ifdef CONFIG_GPU_THERMAL
+static u32 set_limit_pp_num(u32 num)
+{
+ u32 ret = -1;
+ if (mali_plat_data.limit_on == 0)
+ goto quit;
+ if (num > mali_plat_data.cfg_pp ||
+ num < mali_plat_data.scale_info.minpp)
+ goto quit;
+ mali_plat_data.scale_info.maxpp = num;
+ revise_mali_rt();
+ ret = 0;
+quit:
+ return ret;
+}
+#endif
+
+void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data);
+
+#if 0
+struct mali_gpu_clk_item {
+ unsigned int clock; /* unit(MHz) */
+ unsigned int vol;
+};
+
+struct mali_gpu_clock {
+ struct mali_gpu_clk_item *item;
+ unsigned int num_of_steps;
+};
+#endif
+
+/* Function that platfrom report it's clock info which driver can set, needed when CONFIG_MALI_DVFS enabled */
+void meson_platform_get_clock_info(struct mali_gpu_clock **data) {
+ *data = &meson_gpu_clk_info;
+}
+
+/* Function that get the current clock info, needed when CONFIG_MALI_DVFS enabled */
+int meson_platform_get_freq(void) {
+ printk("get cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
+ return cur_gpu_clk_index;
+}
+
+/* Fuction that platform callback for freq setting, needed when CONFIG_MALI_DVFS enabled */
+int meson_platform_set_freq(int setting_clock_step) {
+
+ if (cur_gpu_clk_index == setting_clock_step) {
+ return 0;
+ }
+
+ mali_clock_set(setting_clock_step);
+
+ cur_gpu_clk_index = setting_clock_step;
+ printk("set cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
+
+ return 0;
+}
+
+int mali_meson_init_start(struct platform_device* ptr_plt_dev)
+{
+ struct mali_gpu_device_data* pdev = ptr_plt_dev->dev.platform_data;
+
+ /* chip mark detect. */
+#ifdef IS_MESON_M8_CPU
+ if (IS_MESON_M8_CPU) {
+ mali_plat_data.have_switch = 0;
+ }
+#endif
+
+ /* for resource data. */
+ ptr_plt_dev->num_resources = ARRAY_SIZE(mali_gpu_resources);
+ ptr_plt_dev->resource = mali_gpu_resources;
+
+ /*for dvfs*/
+#ifndef CONFIG_MALI_DVFS
+ /* for mali platform data. */
+ pdev->control_interval = 300;
+ pdev->utilization_callback = mali_gpu_utilization_callback;
+#else
+ pdev->get_clock_info = meson_platform_get_clock_info;
+ pdev->get_freq = meson_platform_get_freq;
+ pdev->set_freq = meson_platform_set_freq;
+#endif
+
+ return mali_clock_init(&mali_plat_data);
+}
+
+int mali_meson_init_finish(struct platform_device* ptr_plt_dev)
+{
+#ifndef CONFIG_MALI_DVFS
+ if (mali_core_scaling_init(&mali_plat_data) < 0)
+ return -1;
+#else
+ printk("disable meson own dvfs\n");
+#endif
+ return 0;
+}
+
+int mali_meson_uninit(struct platform_device* ptr_plt_dev)
+{
+ return 0;
+}
+
+static int mali_cri_light_suspend(size_t param)
+{
+ int ret;
+ struct device *device;
+ struct mali_pmu_core *pmu;
+
+ ret = 0;
+ mali_pm_statue = 1;
+ device = (struct device *)param;
+ pmu = mali_pmu_get_global_pmu_core();
+
+ if (NULL != device->driver &&
+ NULL != device->driver->pm &&
+ NULL != device->driver->pm->runtime_suspend)
+ {
+ /* Need to notify Mali driver about this event */
+ ret = device->driver->pm->runtime_suspend(device);
+ }
+ mali_pmu_power_down_all(pmu);
+ return ret;
+}
+
+static int mali_cri_light_resume(size_t param)
+{
+ int ret;
+ struct device *device;
+ struct mali_pmu_core *pmu;
+
+ ret = 0;
+ device = (struct device *)param;
+ pmu = mali_pmu_get_global_pmu_core();
+
+ mali_pmu_power_up_all(pmu);
+ if (NULL != device->driver &&
+ NULL != device->driver->pm &&
+ NULL != device->driver->pm->runtime_resume)
+ {
+ /* Need to notify Mali driver about this event */
+ ret = device->driver->pm->runtime_resume(device);
+ }
+ mali_pm_statue = 0;
+ return ret;
+}
+
+static int mali_cri_deep_suspend(size_t param)
+{
+ int ret;
+ struct device *device;
+ struct mali_pmu_core *pmu;
+
+ ret = 0;
+ device = (struct device *)param;
+ pmu = mali_pmu_get_global_pmu_core();
+
+ if (NULL != device->driver &&
+ NULL != device->driver->pm &&
+ NULL != device->driver->pm->suspend)
+ {
+ /* Need to notify Mali driver about this event */
+ ret = device->driver->pm->suspend(device);
+ }
+ mali_pmu_power_down_all(pmu);
+ return ret;
+}
+
+static int mali_cri_deep_resume(size_t param)
+{
+ int ret;
+ struct device *device;
+ struct mali_pmu_core *pmu;
+
+ ret = 0;
+ device = (struct device *)param;
+ pmu = mali_pmu_get_global_pmu_core();
+
+ mali_pmu_power_up_all(pmu);
+ if (NULL != device->driver &&
+ NULL != device->driver->pm &&
+ NULL != device->driver->pm->resume)
+ {
+ /* Need to notify Mali driver about this event */
+ ret = device->driver->pm->resume(device);
+ }
+ return ret;
+
+}
+
+int mali_light_suspend(struct device *device)
+{
+ int ret = 0;
+#ifdef CONFIG_MALI400_PROFILING
+ _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
+ MALI_PROFILING_EVENT_CHANNEL_GPU |
+ MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
+ 0, 0, 0, 0, 0);
+#endif
+
+ /* clock scaling. Kasin..*/
+ ret = mali_clock_critical(mali_cri_light_suspend, (size_t)device);
+ disable_clock();
+ return ret;
+}
+
+int mali_light_resume(struct device *device)
+{
+ int ret = 0;
+ enable_clock();
+ ret = mali_clock_critical(mali_cri_light_resume, (size_t)device);
+#ifdef CONFIG_MALI400_PROFILING
+ _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
+ MALI_PROFILING_EVENT_CHANNEL_GPU |
+ MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
+ get_current_frequency(), 0, 0, 0, 0);
+#endif
+ return ret;
+}
+
+int mali_deep_suspend(struct device *device)
+{
+ int ret = 0;
+
+ mali_pm_statue = 1;
+ enable_clock();
+#ifndef CONFIG_MALI_DVFS
+ flush_scaling_job();
+#endif
+
+ /* clock scaling off. Kasin... */
+ ret = mali_clock_critical(mali_cri_deep_suspend, (size_t)device);
+ disable_clock();
+ return ret;
+}
+
+int mali_deep_resume(struct device *device)
+{
+ int ret = 0;
+
+ /* clock scaling up. Kasin.. */
+ enable_clock();
+ ret = mali_clock_critical(mali_cri_deep_resume, (size_t)device);
+ mali_pm_statue = 0;
+ return ret;
+
+}
+
+void mali_post_init(void)
+{
+#ifdef CONFIG_GPU_THERMAL
+ int err;
+ struct gpufreq_cooling_device *gcdev = NULL;
+ struct gpucore_cooling_device *gccdev = NULL;
+
+ gcdev = gpufreq_cooling_alloc();
+ register_gpu_freq_info(get_current_frequency);
+ if (IS_ERR(gcdev))
+ printk("malloc gpu cooling buffer error!!\n");
+ else if (!gcdev)
+ printk("system does not enable thermal driver\n");
+ else {
+ gcdev->get_gpu_freq_level = get_mali_freq_level;
+ gcdev->get_gpu_max_level = get_mali_max_level;
+ gcdev->set_gpu_freq_idx = set_limit_mali_freq;
+ gcdev->get_gpu_current_max_level = get_limit_mali_freq;
+ err = gpufreq_cooling_register(gcdev);
+ if (err < 0)
+ printk("register GPU cooling error\n");
+ printk("gpu cooling register okay with err=%d\n",err);
+ }
+
+ gccdev = gpucore_cooling_alloc();
+ if (IS_ERR(gccdev))
+ printk("malloc gpu core cooling buffer error!!\n");
+ else if (!gccdev)
+ printk("system does not enable thermal driver\n");
+ else {
+ gccdev->max_gpu_core_num=mali_plat_data.cfg_pp;
+ gccdev->set_max_pp_num=set_limit_pp_num;
+ err = (int)gpucore_cooling_register(gccdev);
+ if (err < 0)
+ printk("register GPU cooling error\n");
+ printk("gpu core cooling register okay with err=%d\n",err);
+ }
+#endif
+}
--- /dev/null
+/*
+ * platform.c
+ *
+ * clock source setting and resource config
+ *
+ * Created on: Dec 4, 2013
+ * Author: amlogic
+ */
+
+#include <linux/platform_device.h>
+#include <linux/version.h>
+#include <linux/pm.h>
+#include <linux/of.h>
+#include <linux/module.h> /* kernel module definitions */
+#include <linux/ioport.h> /* request_mem_region */
+#include <linux/slab.h>
+#include <mach/register.h>
+#include <mach/irqs.h>
+#include <mach/io.h>
+#include <asm/io.h>
+#include <linux/mali/mali_utgard.h>
+#include <linux/gpu_cooling.h>
+#include <linux/gpucore_cooling.h>
+#include <common/mali_kernel_common.h>
+#include <common/mali_osk_profiling.h>
+#include <common/mali_pmu.h>
+
+#include "meson_main.h"
+
+/*
+ * For Meson 8B.
+ *
+ */
+
+#define CFG_PP 2
+#define CFG_CLOCK 3
+#define CFG_MIN_PP 1
+#define CFG_MIN_CLOCK 0
+
+/* fclk is 2550Mhz. */
+#define FCLK_DEV3 (6 << 9) /* 850 Mhz */
+#define FCLK_DEV4 (5 << 9) /* 637.5 Mhz */
+#define FCLK_DEV5 (7 << 9) /* 510 Mhz */
+#define FCLK_DEV7 (4 << 9) /* 364.3 Mhz */
+
+static u32 mali_dvfs_clk[] = {
+ FCLK_DEV5 | 1, /* 255 Mhz */
+ FCLK_DEV7 | 0, /* 364 Mhz */
+ FCLK_DEV3 | 1, /* 425 Mhz */
+ FCLK_DEV5 | 0, /* 510 Mhz */
+ FCLK_DEV4 | 0, /* 637.5 Mhz */
+};
+
+static u32 mali_dvfs_clk_sample[] = {
+ 255, /* 182.1 Mhz */
+ 364, /* 318.7 Mhz */
+ 425, /* 425 Mhz */
+ 510, /* 510 Mhz */
+ 637, /* 637.5 Mhz */
+};
+
+//////////////////////////////////////
+//for dvfs
+struct mali_gpu_clk_item meson_gpu_clk[] = {
+ {255, 1150}, /* 182.1 Mhz, 1150mV */
+ {364, 1150}, /* 318.7 Mhz */
+ {425, 1150}, /* 425 Mhz */
+ {510, 1150}, /* 510 Mhz */
+ {637, 1150}, /* 637.5 Mhz */
+};
+struct mali_gpu_clock meson_gpu_clk_info = {
+ .item = meson_gpu_clk,
+ .num_of_steps = ARRAY_SIZE(meson_gpu_clk),
+};
+static int cur_gpu_clk_index = 0;
+//////////////////////////////////////
+
+static mali_dvfs_threshold_table mali_dvfs_table[]={
+ { 0, 0, 5, 30 , 180}, /* for 255 */
+ { 1, 1, 5, 152, 205}, /* for 364 */
+ { 2, 2, 5, 180, 212}, /* for 425 */
+ { 3, 3, 5, 205, 236}, /* for 510 */
+ { 4, 4, 5, 230, 255}, /* for 637 */
+ { 0, 0, 5, 0, 0}
+};
+
+static void mali_plat_preheat(void);
+static mali_plat_info_t mali_plat_data = {
+ .cfg_pp = CFG_PP, /* number of pp. */
+ .cfg_min_pp = CFG_MIN_PP,
+ .turbo_clock = 4, /* reserved clock src. */
+ .def_clock = 2, /* gpu clock used most of time.*/
+ .cfg_clock = CFG_CLOCK, /* max gpu clock. */
+ .cfg_clock_bkup = CFG_CLOCK,
+ .cfg_min_clock = CFG_MIN_CLOCK,
+
+ .sc_mpp = 2, /* number of pp used most of time.*/
+ .bst_gpu = 210, /* threshold for boosting gpu. */
+ .bst_pp = 160, /* threshold for boosting PP. */
+
+ .clk = mali_dvfs_clk, /* clock source table. */
+ .clk_sample = mali_dvfs_clk_sample, /* freqency table for show. */
+ .clk_len = sizeof(mali_dvfs_clk) / sizeof(mali_dvfs_clk[0]),
+ .have_switch = 1,
+
+ .dvfs_table = mali_dvfs_table, /* DVFS table. */
+ .dvfs_table_size = sizeof(mali_dvfs_table) / sizeof(mali_dvfs_threshold_table),
+
+ .scale_info = {
+ CFG_MIN_PP, /* minpp */
+ CFG_PP, /* maxpp, should be same as cfg_pp */
+ CFG_MIN_CLOCK, /* minclk */
+ CFG_CLOCK, /* maxclk should be same as cfg_clock */
+ },
+
+ .limit_on = 1,
+ .plat_preheat = mali_plat_preheat,
+};
+
+static void mali_plat_preheat(void)
+{
+#ifndef CONFIG_MALI_DVFS
+ u32 pre_fs;
+ u32 clk, pp;
+
+ if (get_mali_schel_mode() != MALI_PP_FS_SCALING)
+ return;
+
+ get_mali_rt_clkpp(&clk, &pp);
+ pre_fs = mali_plat_data.def_clock + 1;
+ if (clk < pre_fs)
+ clk = pre_fs;
+ if (pp < mali_plat_data.sc_mpp)
+ pp = mali_plat_data.sc_mpp;
+ set_mali_rt_clkpp(clk, pp, 1);
+#endif
+}
+
+mali_plat_info_t* get_mali_plat_data(void) {
+ return &mali_plat_data;
+}
+
+int get_mali_freq_level(int freq)
+{
+ int i = 0, level = -1;
+ int mali_freq_num;
+
+ if (freq < 0)
+ return level;
+ mali_freq_num = mali_plat_data.dvfs_table_size - 1;
+ if (freq < mali_plat_data.clk_sample[0])
+ level = mali_freq_num-1;
+ if (freq >= mali_plat_data.clk_sample[mali_freq_num - 1])
+ level = 0;
+ for (i=0; i<mali_freq_num - 1 ;i++) {
+ if (freq >= mali_plat_data.clk_sample[i] && freq < mali_plat_data.clk_sample[i + 1]) {
+ level = i;
+ level = mali_freq_num-level - 1;
+ break;
+ }
+ }
+ return level;
+}
+
+unsigned int get_mali_max_level(void)
+{
+ return mali_plat_data.dvfs_table_size - 1;
+}
+
+static struct resource mali_gpu_resources[] =
+{
+ MALI_GPU_RESOURCES_MALI450_MP2_PMU(IO_MALI_APB_PHY_BASE, INT_MALI_GP, INT_MALI_GP_MMU,
+ INT_MALI_PP0, INT_MALI_PP0_MMU,
+ INT_MALI_PP1, INT_MALI_PP1_MMU,
+ INT_MALI_PP)
+};
+
+static void set_limit_mali_freq(u32 idx)
+{
+ if (mali_plat_data.limit_on == 0)
+ return;
+ if (idx > mali_plat_data.turbo_clock || idx < mali_plat_data.scale_info.minclk)
+ return;
+ mali_plat_data.scale_info.maxclk= idx;
+
+ revise_mali_rt();
+}
+
+static u32 get_limit_mali_freq(void)
+{
+ return mali_plat_data.scale_info.maxclk;
+}
+
+static u32 set_limit_pp_num(u32 num)
+{
+ u32 ret = -1;
+ if (mali_plat_data.limit_on == 0)
+ goto quit;
+ if (num > mali_plat_data.cfg_pp ||
+ num < mali_plat_data.scale_info.minpp)
+ goto quit;
+ mali_plat_data.scale_info.maxpp = num;
+ revise_mali_rt();
+ ret = 0;
+quit:
+ return ret;
+}
+
+void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data);
+
+#if 0
+struct mali_gpu_clk_item {
+ unsigned int clock; /* unit(MHz) */
+ unsigned int vol;
+};
+
+struct mali_gpu_clock {
+ struct mali_gpu_clk_item *item;
+ unsigned int num_of_steps;
+};
+#endif
+
+/* Function that platfrom report it's clock info which driver can set, needed when CONFIG_MALI_DVFS enabled */
+void meson_platform_get_clock_info(struct mali_gpu_clock **data) {
+ *data = &meson_gpu_clk_info;
+}
+
+/* Function that get the current clock info, needed when CONFIG_MALI_DVFS enabled */
+int meson_platform_get_freq(void) {
+ printk("get cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
+ return cur_gpu_clk_index;
+}
+
+/* Fuction that platform callback for freq setting, needed when CONFIG_MALI_DVFS enabled */
+int meson_platform_set_freq(int setting_clock_step) {
+
+ if (cur_gpu_clk_index == setting_clock_step) {
+ return 0;
+ }
+
+ mali_clock_set(setting_clock_step);
+
+ cur_gpu_clk_index = setting_clock_step;
+ printk("set cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
+
+ return 0;
+}
+int mali_meson_init_start(struct platform_device* ptr_plt_dev)
+{
+ struct mali_gpu_device_data* pdev = ptr_plt_dev->dev.platform_data;
+
+
+ /* for resource data. */
+ ptr_plt_dev->num_resources = ARRAY_SIZE(mali_gpu_resources);
+ ptr_plt_dev->resource = mali_gpu_resources;
+
+ /*for dvfs*/
+#ifndef CONFIG_MALI_DVFS
+ /* for mali platform data. */
+ pdev->control_interval = 200;
+ pdev->utilization_callback = mali_gpu_utilization_callback;
+#else
+ pdev->get_clock_info = meson_platform_get_clock_info;
+ pdev->get_freq = meson_platform_get_freq;
+ pdev->set_freq = meson_platform_set_freq;
+#endif
+
+ return mali_clock_init(&mali_plat_data);
+}
+
+int mali_meson_init_finish(struct platform_device* ptr_plt_dev)
+{
+#ifndef CONFIG_MALI_DVFS
+ if (mali_core_scaling_init(&mali_plat_data) < 0)
+ return -1;
+#endif
+ return 0;
+}
+
+int mali_meson_uninit(struct platform_device* ptr_plt_dev)
+{
+ return 0;
+}
+
+static int mali_cri_light_suspend(size_t param)
+{
+ int ret;
+ struct device *device;
+ struct mali_pmu_core *pmu;
+
+ ret = 0;
+ mali_pm_statue = 1;
+ device = (struct device *)param;
+ pmu = mali_pmu_get_global_pmu_core();
+
+ if (NULL != device->driver &&
+ NULL != device->driver->pm &&
+ NULL != device->driver->pm->runtime_suspend)
+ {
+ /* Need to notify Mali driver about this event */
+ ret = device->driver->pm->runtime_suspend(device);
+ }
+ mali_pmu_power_down_all(pmu);
+ return ret;
+}
+
+static int mali_cri_light_resume(size_t param)
+{
+ int ret;
+ struct device *device;
+ struct mali_pmu_core *pmu;
+
+ ret = 0;
+ device = (struct device *)param;
+ pmu = mali_pmu_get_global_pmu_core();
+
+ mali_pmu_power_up_all(pmu);
+ if (NULL != device->driver &&
+ NULL != device->driver->pm &&
+ NULL != device->driver->pm->runtime_resume)
+ {
+ /* Need to notify Mali driver about this event */
+ ret = device->driver->pm->runtime_resume(device);
+ }
+ mali_pm_statue = 0;
+ return ret;
+}
+
+static int mali_cri_deep_suspend(size_t param)
+{
+ int ret;
+ struct device *device;
+ struct mali_pmu_core *pmu;
+
+ ret = 0;
+ device = (struct device *)param;
+ pmu = mali_pmu_get_global_pmu_core();
+
+ if (NULL != device->driver &&
+ NULL != device->driver->pm &&
+ NULL != device->driver->pm->suspend)
+ {
+ /* Need to notify Mali driver about this event */
+ ret = device->driver->pm->suspend(device);
+ }
+ mali_pmu_power_down_all(pmu);
+ return ret;
+}
+
+static int mali_cri_deep_resume(size_t param)
+{
+ int ret;
+ struct device *device;
+ struct mali_pmu_core *pmu;
+
+ ret = 0;
+ device = (struct device *)param;
+ pmu = mali_pmu_get_global_pmu_core();
+
+ mali_pmu_power_up_all(pmu);
+ if (NULL != device->driver &&
+ NULL != device->driver->pm &&
+ NULL != device->driver->pm->resume)
+ {
+ /* Need to notify Mali driver about this event */
+ ret = device->driver->pm->resume(device);
+ }
+ return ret;
+
+}
+
+int mali_light_suspend(struct device *device)
+{
+ int ret = 0;
+#ifdef CONFIG_MALI400_PROFILING
+ _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
+ MALI_PROFILING_EVENT_CHANNEL_GPU |
+ MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
+ 0, 0, 0, 0, 0);
+#endif
+
+ /* clock scaling. Kasin..*/
+ ret = mali_clock_critical(mali_cri_light_suspend, (size_t)device);
+ disable_clock();
+ return ret;
+}
+
+int mali_light_resume(struct device *device)
+{
+ int ret = 0;
+ enable_clock();
+ ret = mali_clock_critical(mali_cri_light_resume, (size_t)device);
+#ifdef CONFIG_MALI400_PROFILING
+ _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
+ MALI_PROFILING_EVENT_CHANNEL_GPU |
+ MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
+ get_current_frequency(), 0, 0, 0, 0);
+#endif
+ return ret;
+}
+
+int mali_deep_suspend(struct device *device)
+{
+ int ret = 0;
+ struct mali_pmu_core *pmu;
+
+ mali_pm_statue = 1;
+ pmu = mali_pmu_get_global_pmu_core();
+ enable_clock();
+#ifndef CONFIG_MALI_DVFS
+ flush_scaling_job();
+#endif
+
+ /* clock scaling off. Kasin... */
+ ret = mali_clock_critical(mali_cri_deep_suspend, (size_t)device);
+ disable_clock();
+ return ret;
+}
+
+int mali_deep_resume(struct device *device)
+{
+ int ret = 0;
+
+ /* clock scaling up. Kasin.. */
+ enable_clock();
+ ret = mali_clock_critical(mali_cri_deep_resume, (size_t)device);
+ mali_pm_statue = 0;
+ return ret;
+}
+
+void mali_post_init(void)
+{
+#ifdef CONFIG_GPU_THERMAL
+ int err;
+ struct gpufreq_cooling_device *gcdev = NULL;
+ struct gpucore_cooling_device *gccdev = NULL;
+
+ gcdev = gpufreq_cooling_alloc();
+ register_gpu_freq_info(get_current_frequency);
+ if (IS_ERR(gcdev))
+ printk("malloc gpu cooling buffer error!!\n");
+ else if (!gcdev)
+ printk("system does not enable thermal driver\n");
+ else {
+ gcdev->get_gpu_freq_level = get_mali_freq_level;
+ gcdev->get_gpu_max_level = get_mali_max_level;
+ gcdev->set_gpu_freq_idx = set_limit_mali_freq;
+ gcdev->get_gpu_current_max_level = get_limit_mali_freq;
+ err = gpufreq_cooling_register(gcdev);
+ if (err < 0)
+ printk("register GPU cooling error\n");
+ printk("gpu cooling register okay with err=%d\n",err);
+ }
+
+ gccdev = gpucore_cooling_alloc();
+ if (IS_ERR(gccdev))
+ printk("malloc gpu core cooling buffer error!!\n");
+ else if (!gccdev)
+ printk("system does not enable thermal driver\n");
+ else {
+ gccdev->max_gpu_core_num=mali_plat_data.cfg_pp;
+ gccdev->set_max_pp_num=set_limit_pp_num;
+ err = (int)gpucore_cooling_register(gccdev);
+ if (err < 0)
+ printk("register GPU cooling error\n");
+ printk("gpu core cooling register okay with err=%d\n",err);
+ }
+#endif
+}
--- /dev/null
+/*
+ * Copyright (C) 2013 ARM Limited. All rights reserved.
+ *
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ *
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+/**
+ * @file arm_core_scaling.c
+ * Example core scaling policy.
+ */
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/workqueue.h>
+#include <linux/mali/mali_utgard.h>
+#include <mali_kernel_common.h>
+#include <mali_osk_profiling.h>
+
+#include <meson_main.h>
+
+#define LOG_MALI_SCALING 0
+
+
+static int currentStep;
+#ifndef CONFIG_MALI_DVFS
+static int num_cores_enabled;
+static int lastStep;
+static struct work_struct wq_work;
+static mali_plat_info_t* pmali_plat = NULL;
+#endif
+static int scaling_mode = MALI_PP_FS_SCALING;
+
+
+static unsigned scaling_dbg_level = 0;
+module_param(scaling_dbg_level, uint, 0644);
+MODULE_PARM_DESC(scaling_dbg_level , "scaling debug level");
+
+#define scalingdbg(level, fmt, arg...) \
+ do { \
+ if (scaling_dbg_level >= (level)) \
+ printk(fmt , ## arg); \
+ } while (0)
+
+#ifndef CONFIG_MALI_DVFS
+static void do_scaling(struct work_struct *work)
+{
+ mali_dvfs_threshold_table * pdvfs = pmali_plat->dvfs_table;
+ int err = mali_perf_set_num_pp_cores(num_cores_enabled);
+ scalingdbg(1, "set pp cores to %d\n", num_cores_enabled);
+ MALI_DEBUG_ASSERT(0 == err);
+ MALI_IGNORE(err);
+ if (pdvfs[currentStep].freq_index != pdvfs[lastStep].freq_index) {
+ mali_dev_pause();
+ mali_clock_set(pdvfs[currentStep].freq_index);
+ mali_dev_resume();
+ lastStep = currentStep;
+ }
+#ifdef CONFIG_MALI400_PROFILING
+ _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
+ MALI_PROFILING_EVENT_CHANNEL_GPU |
+ MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
+ get_current_frequency(),
+ 0, 0, 0, 0);
+#endif
+}
+#endif
+
+u32 revise_set_clk(u32 val, u32 flush)
+{
+ u32 ret = 0;
+#ifndef CONFIG_MALI_DVFS
+ mali_scale_info_t* pinfo;
+
+ pinfo = &pmali_plat->scale_info;
+
+ if (val < pinfo->minclk)
+ val = pinfo->minclk;
+ else if (val > pinfo->maxclk)
+ val = pinfo->maxclk;
+
+ if (val != currentStep) {
+ currentStep = val;
+ if (flush)
+ schedule_work(&wq_work);
+ else
+ ret = 1;
+ }
+#endif
+ return ret;
+}
+
+void get_mali_rt_clkpp(u32* clk, u32* pp)
+{
+#ifndef CONFIG_MALI_DVFS
+ *clk = currentStep;
+ *pp = num_cores_enabled;
+#endif
+}
+
+u32 set_mali_rt_clkpp(u32 clk, u32 pp, u32 flush)
+{
+ u32 ret = 0;
+#ifndef CONFIG_MALI_DVFS
+ mali_scale_info_t* pinfo;
+ u32 flush_work = 0;
+
+ pinfo = &pmali_plat->scale_info;
+ if (clk < pinfo->minclk)
+ clk = pinfo->minclk;
+ else if (clk > pinfo->maxclk)
+ clk = pinfo->maxclk;
+
+ if (clk != currentStep) {
+ currentStep = clk;
+ if (flush)
+ flush_work++;
+ else
+ ret = 1;
+ }
+ if (pp < pinfo->minpp)
+ pp = pinfo->minpp;
+ else if (pp > pinfo->maxpp)
+ pp = pinfo->maxpp;
+
+ if (pp != num_cores_enabled) {
+ num_cores_enabled = pp;
+ if (flush)
+ flush_work++;
+ else
+ ret = 1;
+ }
+
+ if (flush_work)
+ schedule_work(&wq_work);
+#endif
+ return ret;
+}
+
+void revise_mali_rt(void)
+{
+#ifndef CONFIG_MALI_DVFS
+ set_mali_rt_clkpp(currentStep, num_cores_enabled, 1);
+#endif
+}
+
+void flush_scaling_job(void)
+{
+#ifndef CONFIG_MALI_DVFS
+ cancel_work_sync(&wq_work);
+#endif
+}
+
+#ifndef CONFIG_MALI_DVFS
+static u32 enable_one_core(void)
+{
+ scalingdbg(2, "meson: one more pp, curent has %d pp cores\n", num_cores_enabled + 1);
+ return set_mali_rt_clkpp(currentStep, num_cores_enabled + 1, 0);
+}
+
+static u32 disable_one_core(void)
+{
+ scalingdbg(2, "meson: disable one pp, current has %d pp cores\n", num_cores_enabled - 1);
+ return set_mali_rt_clkpp(currentStep, num_cores_enabled - 1, 0);
+}
+
+static u32 enable_max_num_cores(void)
+{
+ return set_mali_rt_clkpp(currentStep, pmali_plat->scale_info.maxpp, 0);
+}
+
+static u32 enable_pp_cores(u32 val)
+{
+ scalingdbg(2, "meson: enable %d pp cores\n", val);
+ return set_mali_rt_clkpp(currentStep, val, 0);
+}
+#endif
+
+int mali_core_scaling_init(mali_plat_info_t *mali_plat)
+{
+#ifndef CONFIG_MALI_DVFS
+ if (mali_plat == NULL) {
+ scalingdbg(2, " Mali platform data is NULL!!!\n");
+ return -1;
+ }
+
+ pmali_plat = mali_plat;
+ num_cores_enabled = pmali_plat->sc_mpp;
+
+ currentStep = pmali_plat->def_clock;
+ lastStep = currentStep;
+ INIT_WORK(&wq_work, do_scaling);
+#endif
+ return 0;
+ /* NOTE: Mali is not fully initialized at this point. */
+}
+
+void mali_core_scaling_term(void)
+{
+#ifndef CONFIG_MALI_DVFS
+ flush_scheduled_work();
+#endif
+}
+
+#ifndef CONFIG_MALI_DVFS
+static u32 mali_threshold [] = {
+ 102, /* 40% */
+ 128, /* 50% */
+ 230, /* 90% */
+};
+#endif
+
+void mali_pp_scaling_update(struct mali_gpu_utilization_data *data)
+{
+#ifndef CONFIG_MALI_DVFS
+ int ret = 0;
+
+ if (mali_threshold[2] < data->utilization_pp)
+ ret = enable_max_num_cores();
+ else if (mali_threshold[1]< data->utilization_pp)
+ ret = enable_one_core();
+ else if (0 < data->utilization_pp)
+ ret = disable_one_core();
+ if (ret == 1)
+ schedule_work(&wq_work);
+#endif
+}
+
+#if LOG_MALI_SCALING
+void trace_utilization(struct mali_gpu_utilization_data *data, u32 current_idx, u32 next,
+ u32 current_pp, u32 next_pp)
+{
+ char direction;
+ if (next > current_idx)
+ direction = '>';
+ else if ((current_idx > pmali_plat->scale_info.minpp) && (next < current_idx))
+ direction = '<';
+ else
+ direction = '~';
+
+ scalingdbg(2, "[SCALING]%c (%3d-->%3d)@%3d{%3d - %3d}. pp:(%d-->%d)\n",
+ direction,
+ get_mali_freq(current_idx),
+ get_mali_freq(next),
+ data->utilization_gpu,
+ pmali_plat->dvfs_table[current_idx].downthreshold,
+ pmali_plat->dvfs_table[current_idx].upthreshold,
+ current_pp, next_pp);
+}
+#endif
+
+#ifndef CONFIG_MALI_DVFS
+static int mali_stay_count = 0;
+static void mali_decide_next_status(struct mali_gpu_utilization_data *data, int* next_fs_idx,
+ int* pp_change_flag)
+{
+ u32 utilization, mali_up_limit, decided_fs_idx;
+ u32 ld_left, ld_right;
+ u32 ld_up, ld_down;
+ u32 change_mode;
+
+ *pp_change_flag = 0;
+ change_mode = 0;
+ utilization = data->utilization_gpu;
+
+ mali_up_limit = (scaling_mode == MALI_TURBO_MODE) ?
+ pmali_plat->turbo_clock : pmali_plat->scale_info.maxclk;
+ decided_fs_idx = currentStep;
+
+ ld_up = pmali_plat->dvfs_table[currentStep].upthreshold;
+ ld_down = pmali_plat->dvfs_table[currentStep].downthreshold;
+
+ scalingdbg(2, "utilization=%d, ld_up=%d\n ", utilization, ld_up);
+ if (utilization >= ld_up) { /* go up */
+
+ scalingdbg(2, "currentStep=%d, mali_up_limit=%d\n ", currentStep, mali_up_limit);
+ if (currentStep < mali_up_limit) {
+ change_mode = 1;
+ if ((currentStep < pmali_plat->def_clock) && (utilization > pmali_plat->bst_gpu))
+ decided_fs_idx = pmali_plat->def_clock;
+ else
+ decided_fs_idx++;
+ }
+ if ((data->utilization_pp >= ld_up) &&
+ (num_cores_enabled < pmali_plat->scale_info.maxpp)) {
+ if ((num_cores_enabled < pmali_plat->sc_mpp) && (data->utilization_pp >= pmali_plat->bst_pp)) {
+ *pp_change_flag = 1;
+ change_mode = 1;
+ } else if (change_mode == 0) {
+ *pp_change_flag = 2;
+ change_mode = 1;
+ }
+ }
+#if LOG_MALI_SCALING
+ scalingdbg(2, "[nexting..] [LD:%d]-> FS[CRNT:%d LMT:%d NEXT:%d] PP[NUM:%d LMT:%d MD:%d][F:%d]\n",
+ data->utilization_pp, currentStep, mali_up_limit, decided_fs_idx,
+ num_cores_enabled, pmali_plat->scale_info.maxpp, *pp_change_flag, change_mode);
+#endif
+ } else if (utilization <= ld_down) { /* go down */
+ if (mali_stay_count > 0) {
+ *next_fs_idx = decided_fs_idx;
+ mali_stay_count--;
+ return;
+ }
+
+ if (num_cores_enabled > pmali_plat->sc_mpp) {
+ change_mode = 1;
+ if (data->utilization_pp <= ld_down) {
+ ld_left = data->utilization_pp * num_cores_enabled;
+ ld_right = (pmali_plat->dvfs_table[currentStep].upthreshold) *
+ (num_cores_enabled - 1);
+ if (ld_left < ld_right) {
+ change_mode = 2;
+ }
+ }
+ } else if (currentStep > pmali_plat->scale_info.minclk) {
+ change_mode = 1;
+ } else if (num_cores_enabled > 1) { /* decrease PPS */
+ if (data->utilization_pp <= ld_down) {
+ ld_left = data->utilization_pp * num_cores_enabled;
+ ld_right = (pmali_plat->dvfs_table[currentStep].upthreshold) *
+ (num_cores_enabled - 1);
+ scalingdbg(2, "ld_left=%d, ld_right=%d\n", ld_left, ld_right);
+ if (ld_left < ld_right) {
+ change_mode = 2;
+ }
+ }
+ }
+
+ if (change_mode == 1) {
+ decided_fs_idx--;
+ } else if (change_mode == 2) { /* decrease PPS */
+ *pp_change_flag = -1;
+ }
+ }
+ if (change_mode)
+ mali_stay_count = pmali_plat->dvfs_table[decided_fs_idx].keep_count;
+ *next_fs_idx = decided_fs_idx;
+}
+#endif
+
+void mali_pp_fs_scaling_update(struct mali_gpu_utilization_data *data)
+{
+#ifndef CONFIG_MALI_DVFS
+ int ret = 0;
+ int pp_change_flag = 0;
+ u32 next_idx = 0;
+
+#if LOG_MALI_SCALING
+ u32 last_pp = num_cores_enabled;
+#endif
+ mali_decide_next_status(data, &next_idx, &pp_change_flag);
+
+ if (pp_change_flag == 1)
+ ret = enable_pp_cores(pmali_plat->sc_mpp);
+ else if (pp_change_flag == 2)
+ ret = enable_one_core();
+ else if (pp_change_flag == -1) {
+ ret = disable_one_core();
+ }
+
+#if LOG_MALI_SCALING
+ if (pp_change_flag || (next_idx != currentStep))
+ trace_utilization(data, currentStep, next_idx, last_pp, num_cores_enabled);
+#endif
+
+ if (next_idx != currentStep) {
+ ret = 1;
+ currentStep = next_idx;
+ }
+
+ if (ret == 1)
+ schedule_work(&wq_work);
+#ifdef CONFIG_MALI400_PROFILING
+ else
+ _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
+ MALI_PROFILING_EVENT_CHANNEL_GPU |
+ MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
+ get_current_frequency(),
+ 0, 0, 0, 0);
+#endif
+#endif
+}
+
+u32 get_mali_schel_mode(void)
+{
+ return scaling_mode;
+}
+
+void set_mali_schel_mode(u32 mode)
+{
+#ifndef CONFIG_MALI_DVFS
+ MALI_DEBUG_ASSERT(mode < MALI_SCALING_MODE_MAX);
+ if (mode >= MALI_SCALING_MODE_MAX)
+ return;
+ scaling_mode = mode;
+
+ /* set default performance range. */
+ pmali_plat->scale_info.minclk = pmali_plat->cfg_min_clock;
+ pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
+ pmali_plat->scale_info.minpp = pmali_plat->cfg_min_pp;
+ pmali_plat->scale_info.maxpp = pmali_plat->cfg_pp;
+
+ /* set current status and tune max freq */
+ if (scaling_mode == MALI_PP_FS_SCALING) {
+ pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
+ enable_pp_cores(pmali_plat->sc_mpp);
+ } else if (scaling_mode == MALI_SCALING_DISABLE) {
+ pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
+ enable_max_num_cores();
+ } else if (scaling_mode == MALI_TURBO_MODE) {
+ pmali_plat->scale_info.maxclk = pmali_plat->turbo_clock;
+ enable_max_num_cores();
+ }
+ currentStep = pmali_plat->scale_info.maxclk;
+ schedule_work(&wq_work);
+#endif
+}
+
+u32 get_current_frequency(void)
+{
+ return get_mali_freq(currentStep);
+}
+
+void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data)
+{
+#ifndef CONFIG_MALI_DVFS
+ if (mali_pm_statue)
+ return;
+
+ switch (scaling_mode) {
+ case MALI_PP_FS_SCALING:
+ mali_pp_fs_scaling_update(data);
+ break;
+ case MALI_PP_SCALING:
+ mali_pp_scaling_update(data);
+ break;
+ default:
+ break;
+ }
+#endif
+}
+
+void mali_dev_restore(void)
+{
+#ifndef CONFIG_MALI_DVFS
+ mali_dvfs_threshold_table * pdvfs = pmali_plat->dvfs_table;
+
+ //mali_perf_set_num_pp_cores(num_cores_enabled);
+ mali_clock_set(pdvfs[currentStep].freq_index);
+#endif
+}
#
# This file is called by the Linux build system.
-include $(src)/Kbuild.amlogic
-# set up defaults if not defined by the user
-TIMESTAMP ?= default
-ifeq ($(CONFIG_UMP), m)
- USING_UMP ?= 1
-else
- USING_UMP ?= 0
-endif
-ifneq ($(KBUILD_SRC),)
- ifneq ($(wildcard $(KBUILD_SRC)/$(src)),)
- TOP_KBUILD_SRC := $(KBUILD_SRC)/
- endif
-endif
+# set up defaults if not defined by the user
+include $(src)/platform/Kbuild.amlogic
+TIMESTAMP ?= default
OS_MEMORY_KERNEL_BUFFER_SIZE_IN_MB ?= 16
-
-#USING_GPU_UTILIZATION ?= 0
-#PROFILING_SKIP_PP_JOBS ?= 0
-#PROFILING_SKIP_PP_AND_GP_JOBS ?= 0
-ifeq ($(CONFIG_MALI_DVFS),y)
- ccflags-y += -DCONFIG_MALI_DVFS
- USING_GPU_UTILIZATION=0
- USING_DVFS=1
-else
- USING_GPU_UTILIZATION=1
- USING_DVFS=0
-endif
+USING_GPU_UTILIZATION ?= 0
PROFILING_SKIP_PP_JOBS ?= 0
PROFILING_SKIP_PP_AND_GP_JOBS ?= 0
-############## Kasin Added, for platform. ################
-
-ifeq ($(CONFIG_MALI400_DEBUG),y)
- BUILD ?= debug
-else
- BUILD ?= release
- ldflags-y += --strip-debug
-
-endif
-##################### end Kasin Added. ###################
-
MALI_PP_SCHEDULER_FORCE_NO_JOB_OVERLAP ?= 0
MALI_PP_SCHEDULER_KEEP_SUB_JOB_STARTS_ALIGNED ?= 0
MALI_PP_SCHEDULER_FORCE_NO_JOB_OVERLAP_BETWEEN_APPS ?= 0
MALI_UPPER_HALF_SCHEDULING ?= 1
-
-############## Kasin Added, useless now. ################
-# Get path to driver source from Linux build system
-DRIVER_DIR=$(src)
-##################### end Kasin Added. ###################
-
MALI_ENABLE_CPU_CYCLES ?= 0
# For customer releases the Linux Device Drivers will be provided as ARM proprietary and GPL releases:
# The ARM proprietary product will only include the license/proprietary directory
# The GPL product will only include the license/gpl directory
-ifeq ($(wildcard $(TOP_KBUILD_SRC)$(DRIVER_DIR)/linux/license/gpl/*),)
- ccflags-y += -I$(TOP_KBUILD_SRC)$(DRIVER_DIR)/linux/license/proprietary
+ifeq ($(wildcard $(src)/linux/license/gpl/*),)
+ ccflags-y += -I$(src)/linux/license/proprietary
ifeq ($(CONFIG_MALI400_PROFILING),y)
$(error Profiling is incompatible with non-GPL license)
endif
endif
$(error Linux Device integration is incompatible with non-GPL license)
else
- ccflags-y += -I$(TOP_KBUILD_SRC)$(DRIVER_DIR)/linux/license/gpl
+ ccflags-y += -I$(src)/linux/license/gpl
endif
ifeq ($(USING_GPU_UTILIZATION), 1)
linux/mali_memory_manager.o \
linux/mali_memory_virtual.o \
linux/mali_memory_util.o
+
mali-y += \
linux/mali_ukk_mem.o \
linux/mali_ukk_gp.o \
linux/mali_pmu_power_up_down.o \
__malidrv_build_info.o
-############## Kasin Added, for platform. ################
-ifeq (true,false)
-mali-y += \
- platform/meson_main.o \
- platform/mali_pm_device.o \
- platform/mali_clock.o \
- platform/mpgpu.o
-else
-mali-y += \
- platform/mali_pm_device.o \
- platform/meson_bu/meson_main2.o \
- platform/meson_bu/mali_clock.o \
- platform/meson_bu/mpgpu.o \
- platform/meson_bu/platform_gx.o
-endif
-ifeq ($(CONFIG_MALI_DVFS),y)
- mali-y += platform/meson_bu/mali_dvfs.o
-else
- mali-y += platform/meson_bu/scaling.o
-endif
-
-ifeq ($(TARGET_PLATFORM),meson_m400)
-MALI_PLATFORM_FILES:= \
- platform/meson_m400/mali_fix.o \
- platform/meson_m400/mali_platform.o \
- platform/meson_m400/platform_mx.o
-endif
-
-ifeq ($(TARGET_PLATFORM),meson_m450)
-ccflags-y += -DCONFIG_MALI450=y
-mali-y += \
- platform/meson_m450/scaling.o
-
-mali-$(CONFIG_ARCH_MESON) += \
- platform/meson_m450/platform_m8.o
-
-mali-$(CONFIG_ARCH_MESON8) += \
- platform/meson_m450/platform_m8.o
-
-mali-$(CONFIG_ARCH_MESON6TVD) += \
- platform/meson_m450/platform_m6tvd.o
-
-mali-$(CONFIG_ARCH_MESON8B) += \
- platform/meson_m450/platform_m8b.o
-
-mali-$(CONFIG_ARCH_MESONG9TV) += \
- platform/meson_m450/platform_m8.o
-
-mali-$(CONFIG_ARCH_MESONG9BB) += \
- platform/meson_m450/platform_m8b.o
-endif
-##################### end Kasin Added. ###################
-
ifneq ($(MALI_PLATFORM_FILES),)
mali-y += $(MALI_PLATFORM_FILES:.c=.o)
endif
+ifneq ($(MALI_PLATFORM_FILES_ADD_PREFIX),)
+ mali-y += $(MALI_PLATFORM_FILES_ADD_PREFIX:.c=.o)
+endif
+
mali-$(CONFIG_MALI400_PROFILING) += linux/mali_ukk_profiling.o
mali-$(CONFIG_MALI400_PROFILING) += linux/mali_osk_profiling.o
ccflags-y += -DMALI_OS_MEMORY_KERNEL_BUFFER_SIZE_IN_MB=$(OS_MEMORY_KERNEL_BUFFER_SIZE_IN_MB)
ccflags-y += -DUSING_GPU_UTILIZATION=$(USING_GPU_UTILIZATION)
ccflags-y += -DMALI_ENABLE_CPU_CYCLES=$(MALI_ENABLE_CPU_CYCLES)
-ccflags-y += -DMALI_FAKE_PLATFORM_DEVICE
ifeq ($(MALI_UPPER_HALF_SCHEDULING),1)
ccflags-y += -DMALI_UPPER_HALF_SCHEDULING
endif
-ccflags-$(CONFIG_MALI400_UMP) += -I$(src)/../ump/include/ump
+ccflags-$(CONFIG_MALI400_UMP) += -I$(src)/../../ump/include/ump
ccflags-$(CONFIG_MALI400_DEBUG) += -DDEBUG
# Use our defines when compiling
-ccflags-y += -I$(src) -I$(src)/include -I$(src)/common -I$(src)/linux -I$(src)/platform
+ccflags-y += -I$(src) -I$(src)/include -I$(src)/common -I$(src)/linux -I$(src)/platform
# Get subversion revision number, fall back to only ${MALI_RELEASE_NAME} if no svn info is available
-MALI_RELEASE_NAME=$(shell cat $(TOP_KBUILD_SRC)$(DRIVER_DIR)/.version 2> /dev/null)
+MALI_RELEASE_NAME=$(shell cat $(src)/.version 2> /dev/null)
-SVN_INFO = (cd $(TOP_KBUILD_SRC)$(DRIVER_DIR); svn info 2>/dev/null)
+SVN_INFO = (cd $(src); svn info 2>/dev/null)
ifneq ($(shell $(SVN_INFO) 2>/dev/null),)
# SVN detected
REPO_URL := $(shell $(SVN_INFO) | grep '^URL: ' | cut -d: -f2- | cut -b2-)
else # SVN
-GIT_REV := $(shell cd $(TOP_KBUILD_SRC)$(DRIVER_DIR); git describe --always 2>/dev/null)
+GIT_REV := $(shell cd $(src); git describe --always 2>/dev/null)
ifneq ($(GIT_REV),)
# Git detected
DRIVER_REV := $(MALI_RELEASE_NAME)-$(GIT_REV)
-CHANGE_DATE := $(shell cd $(TOP_KBUILD_SRC)$(DRIVER_DIR); git log -1 --format="%ci")
+CHANGE_DATE := $(shell cd $(src); git log -1 --format="%ci")
CHANGED_REVISION := $(GIT_REV)
-REPO_URL := $(shell cd $(TOP_KBUILD_SRC)$(DRIVER_DIR); git describe --all --always 2>/dev/null)
+REPO_URL := $(shell cd $(src); git describe --all --always 2>/dev/null)
else # Git
# No Git or SVN detected
ccflags-y += -DSVN_REV_STRING=\"$(DRIVER_REV)\"
VERSION_STRINGS :=
-VERSION_STRINGS += API_VERSION=$(shell cd $(TOP_KBUILD_SRC)$(DRIVER_DIR); grep "\#define _MALI_API_VERSION" $(FILES_PREFIX)include/linux/mali/mali_utgard_uk_types.h | cut -d' ' -f 3 )
+VERSION_STRINGS += API_VERSION=$(shell cd $(src); grep "\#define _MALI_API_VERSION" $(FILES_PREFIX)include/linux/mali/mali_utgard_uk_types.h | cut -d' ' -f 3 )
VERSION_STRINGS += REPO_URL=$(REPO_URL)
VERSION_STRINGS += REVISION=$(DRIVER_REV)
VERSION_STRINGS += CHANGED_REVISION=$(CHANGED_REVISION)
VERSION_STRINGS += MALI_UPPER_HALF_SCHEDULING=$(MALI_UPPER_HALF_SCHEDULING)
# Create file with Mali driver configuration
-$(TOP_KBUILD_SRC)$(DRIVER_DIR)/__malidrv_build_info.c:
- @echo 'const char *__malidrv_build_info(void) { return "malidrv: $(VERSION_STRINGS)";}' > $(TOP_KBUILD_SRC)$(DRIVER_DIR)/__malidrv_build_info.c
+$(src)/__malidrv_build_info.c:
+ @echo 'const char *__malidrv_build_info(void) { return "malidrv: $(VERSION_STRINGS)";}' > $(src)/__malidrv_build_info.c
+++ /dev/null
-############## Kasin Added, for platform. ################
-
-ifndef CONFIG_MALI_DMA_BUF_MAP_ON_ATTACH
- ccflags-y += -DCONFIG_MALI_DMA_BUF_MAP_ON_ATTACH=y
-endif
-
-ccflags-y += -DCONFIG_MALI_DT=y
-ccflags-y += -DMESON_CPU_TYPE=0x80
-ccflags-y += -DMESON_CPU_TYPE_MESON6=0x60
-ccflags-y += -DMESON_CPU_TYPE_MESON6TVD=0x75
-ccflags-y += -DMESON_CPU_TYPE_MESON8=0x80
-ccflags-y += -DMESON_CPU_TYPE_MESON8B=0x8B
-
-USE_GPPLL?=0
-ifdef CONFIG_AM_VIDEO
- USE_GPPLL:=1
-endif
-
-ccflags-y += -DAMLOGIC_GPU_USE_GPPLL=$(USE_GPPLL)
+++ /dev/null
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#include <plat/io.h>
-#endif
-
-#include <linux/io.h>
-
-#include <asm/io.h>
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 29))
-#include <linux/amlogic/iomap.h>
-#endif
-#include "meson_main.h"
-
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6TVD
-
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 29))
-#define HHI_MALI_CLK_CNTL 0x106C
-#define mplt_read(r) aml_read_cbus((r))
-#define mplt_write(v, r) aml_write_cbus((r), (v))
-#define mplt_setbits(r, m) aml_write_cbus((r), (aml_read_cbus(r) | (m)));
-#define mplt_clrbits(r, m) aml_write_cbus((r), (aml_read_cbus(r) & (~(m))));
-#else
-#define mplt_read(r) aml_read_reg32((P_##r))
-#define mplt_write(v, r) aml_write_reg32((P_##r), (v))
-#define mplt_setbits(r, m) aml_write_reg32((P_##r), (aml_read_reg32(P_##r) | (m)));
-#define mplt_clrbits(r, m) aml_write_reg32((P_##r), (aml_read_reg32(P_##r) & (~(m))));
-#endif
-#define FCLK_MPLL2 (2 << 9)
-static DEFINE_SPINLOCK(lock);
-static mali_plat_info_t* pmali_plat = NULL;
-static u32 mali_extr_backup = 0;
-static u32 mali_extr_sample_backup = 0;
-
-int mali_clock_init(mali_plat_info_t* mali_plat)
-{
- u32 def_clk_data;
- if (mali_plat == NULL) {
- printk(" Mali platform data is NULL!!!\n");
- return -1;
- }
-
- pmali_plat = mali_plat;
- if (pmali_plat->have_switch) {
- def_clk_data = pmali_plat->clk[pmali_plat->def_clock];
- mplt_write(def_clk_data | (def_clk_data << 16), HHI_MALI_CLK_CNTL);
- mplt_setbits(HHI_MALI_CLK_CNTL, 1 << 24);
- mplt_setbits(HHI_MALI_CLK_CNTL, 1 << 8);
- } else {
- mali_clock_set(pmali_plat->def_clock);
- }
-
- mali_extr_backup = pmali_plat->clk[pmali_plat->clk_len - 1];
- mali_extr_sample_backup = pmali_plat->clk_sample[pmali_plat->clk_len - 1];
- return 0;
-}
-
-int mali_clock_critical(critical_t critical, size_t param)
-{
- int ret = 0;
- unsigned long flags;
-
- spin_lock_irqsave(&lock, flags);
- ret = critical(param);
- spin_unlock_irqrestore(&lock, flags);
- return ret;
-}
-
-static int critical_clock_set(size_t param)
-{
- unsigned int idx = param;
- if (pmali_plat->have_switch) {
- u32 clk_value;
- mplt_setbits(HHI_MALI_CLK_CNTL, 1 << 31);
- clk_value = mplt_read(HHI_MALI_CLK_CNTL) & 0xffff0000;
- clk_value = clk_value | pmali_plat->clk[idx] | (1 << 8);
- mplt_write(clk_value, HHI_MALI_CLK_CNTL);
- mplt_clrbits(HHI_MALI_CLK_CNTL, 1 << 31);
- } else {
- mplt_clrbits(HHI_MALI_CLK_CNTL, 1 << 8);
- mplt_clrbits(HHI_MALI_CLK_CNTL, (0x7F | (0x7 << 9)));
- mplt_write(pmali_plat->clk[idx], HHI_MALI_CLK_CNTL);
- mplt_setbits(HHI_MALI_CLK_CNTL, 1 << 8);
- }
- return 0;
-}
-
-int mali_clock_set(unsigned int clock)
-{
- return mali_clock_critical(critical_clock_set, (size_t)clock);
-}
-
-void disable_clock(void)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&lock, flags);
- mplt_clrbits(HHI_MALI_CLK_CNTL, 1 << 8);
- spin_unlock_irqrestore(&lock, flags);
-}
-
-void enable_clock(void)
-{
- u32 ret;
- unsigned long flags;
-
- spin_lock_irqsave(&lock, flags);
- mplt_setbits(HHI_MALI_CLK_CNTL, 1 << 8);
- ret = mplt_read(HHI_MALI_CLK_CNTL) & (1 << 8);
- spin_unlock_irqrestore(&lock, flags);
-}
-
-u32 get_mali_freq(u32 idx)
-{
- if (!mali_pm_statue) {
- return pmali_plat->clk_sample[idx];
- } else {
- return 0;
- }
-}
-
-void set_str_src(u32 data)
-{
-#if 0
- if (data == 11) {
- writel(0x0004d000, (u32*)P_HHI_MPLL_CNTL9);
- } else if (data > 11) {
- writel(data, (u32*)P_HHI_MPLL_CNTL9);
- }
-#endif
- if (data == 0) {
- pmali_plat->clk[pmali_plat->clk_len - 1] = mali_extr_backup;
- pmali_plat->clk_sample[pmali_plat->clk_len - 1] = mali_extr_sample_backup;
- } else if (data > 10) {
- pmali_plat->clk_sample[pmali_plat->clk_len - 1] = 600;
- pmali_plat->clk[pmali_plat->clk_len - 1] = FCLK_MPLL2;
- }
-}
-#endif
+++ /dev/null
-#ifndef _MALI_CLOCK_H_
-#define _MALI_CLOCK_H_
-
-typedef int (*critical_t)(size_t param);
-int mali_clock_critical(critical_t critical, size_t param);
-
-int mali_clock_init(mali_plat_info_t*);
-int mali_clock_set(unsigned int index);
-void disable_clock(void);
-void enable_clock(void);
-u32 get_mali_freq(u32 idx);
-void set_str_src(u32 data);
-#endif /* _MALI_CLOCK_H_ */
+++ /dev/null
-/*
- * mali_platform.h
- *
- * Created on: Nov 8, 2013
- * Author: amlogic
- */
-
-#include <linux/kernel.h>
-#ifndef MALI_PLATFORM_H_
-#define MALI_PLATFORM_H_
-
-extern u32 mali_gp_reset_fail;
-extern u32 mali_core_timeout;
-
-#endif /* MALI_PLATFORM_H_ */
+++ /dev/null
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/module.h> /* kernel module definitions */
-#include <linux/ioport.h> /* request_mem_region */
-#include <linux/slab.h>
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#endif
-#include "meson_main.h"
-#include <common/mali_kernel_common.h>
-#include <common/mali_osk_profiling.h>
-#include <common/mali_pmu.h>
-#include <linux/mali/mali_utgard.h>
-
-static int mali_os_suspend(struct device *device)
-{
- int ret = 0;
-
- MALI_DEBUG_PRINT(4, ("mali_os_suspend() called\n"));
- ret = mali_deep_suspend(device);
-
- return ret;
-}
-
-static int mali_os_resume(struct device *device)
-{
- int ret = 0;
-
- MALI_DEBUG_PRINT(4, ("mali_os_resume() called\n"));
-
- ret = mali_deep_resume(device);
-
- return ret;
-}
-
-static int mali_os_freeze(struct device *device)
-{
- int ret = 0;
-
- MALI_DEBUG_PRINT(4, ("mali_os_freeze() called\n"));
-
- mali_dev_freeze();
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->freeze)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->freeze(device);
- }
-
- return ret;
-}
-//copy from r4p1 linux/mali_pmu_power_up_down.c
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
-static int mali_pmu_powerup(void)
-{
- struct mali_pmu_core *pmu = mali_pmu_get_global_pmu_core();
-
- MALI_DEBUG_PRINT(5, ("Mali PMU: Power up\n"));
-
- MALI_DEBUG_ASSERT_POINTER(pmu);
- if (NULL == pmu) {
- return -ENXIO;
- }
-
- mali_pmu_power_up_all(pmu);
-
- return 0;
-}
-#endif
-
-static int mali_os_thaw(struct device *device)
-{
- int ret = 0;
-
- MALI_DEBUG_PRINT(4, ("mali_os_thaw() called\n"));
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
- enable_clock();
- mali_pmu_powerup();
-#endif
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->thaw)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->thaw(device);
- }
-
- return ret;
-}
-
-static int mali_os_restore(struct device *device)
-{
- MALI_DEBUG_PRINT(4, ("mali_os_thaw() called\n"));
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
- mali_dev_restore();
-#endif
- return mali_os_resume(device);
-}
-
-#ifdef CONFIG_PM_RUNTIME
-#if 0
-static int mali_runtime_suspend(struct device *device)
-{
- int ret = 0;
-
- MALI_DEBUG_PRINT(4, ("mali_runtime_suspend() called\n"));
- ret = mali_light_suspend(device);
-
- return ret;
-}
-
-static int mali_runtime_resume(struct device *device)
-{
- int ret = 0;
-
- MALI_DEBUG_PRINT(4, ("mali_run time_resume() called\n"));
- ret = mali_light_resume(device);
-
- return ret;
-}
-
-static int mali_runtime_idle(struct device *device)
-{
- MALI_DEBUG_PRINT(4, ("mali_runtime_idle() called\n"));
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_idle)
- {
- /* Need to notify Mali driver about this event */
- int ret = device->driver->pm->runtime_idle(device);
- if (0 != ret)
- {
- return ret;
- }
- }
-
- pm_runtime_suspend(device);
-
- return 0;
-}
-#endif
-#endif
-
-static struct dev_pm_ops mali_gpu_device_type_pm_ops =
-{
- .suspend = mali_os_suspend,
- .resume = mali_os_resume,
- .freeze = mali_os_freeze,
- .thaw = mali_os_thaw,
- .restore = mali_os_restore,
-#if 0//def CONFIG_PM_RUNTIME
- .runtime_suspend = mali_runtime_suspend,
- .runtime_resume = mali_runtime_resume,
- .runtime_idle = mali_runtime_idle,
-#endif
-};
-
-struct device_type mali_pm_device =
-{
- .pm = &mali_gpu_device_type_pm_ops,
-};
+++ /dev/null
-/*
- * Copyright (C) 2013 ARM Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
- *
- * A copy of the licence is included with the program, and can also be obtained from Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-/**
- * @file arm_core_scaling.h
- * Example core scaling policy.
- */
-
-#ifndef __ARM_CORE_SCALING_H__
-#define __ARM_CORE_SCALING_H__
-
-#include <linux/types.h>
-#include <linux/workqueue.h>
-#include <linux/clk-provider.h>
-#include <linux/clk.h>
-
-enum mali_scale_mode_t {
- MALI_PP_SCALING = 0,
- MALI_PP_FS_SCALING,
- MALI_SCALING_DISABLE,
- MALI_TURBO_MODE,
- MALI_SCALING_MODE_MAX
-};
-
-typedef struct mali_dvfs_threshold_table {
- uint32_t freq_index;
- uint32_t voltage;
- uint32_t keep_count;
- uint32_t downthreshold;
- uint32_t upthreshold;
- uint32_t clk_freq;
- const char *clk_parent;
- struct clk *clkp_handle;
- uint32_t clkp_freq;
-} mali_dvfs_threshold_table;
-
-/**
- * restrictions on frequency and number of pp.
- */
-typedef struct mali_scale_info_t {
- u32 minpp;
- u32 maxpp;
- u32 minclk;
- u32 maxclk;
-} mali_scale_info_t;
-
-/**
- * Platform spesific data for meson chips.
- */
-typedef struct mali_plat_info_t {
- u32 cfg_pp; /* number of pp. */
- u32 cfg_min_pp;
- u32 turbo_clock; /* reserved clock src. */
- u32 def_clock; /* gpu clock used most of time.*/
- u32 cfg_clock; /* max clock could be used.*/
- u32 cfg_clock_bkup; /* same as cfg_clock, for backup. */
- u32 cfg_min_clock;
-
- u32 sc_mpp; /* number of pp used most of time.*/
- u32 bst_gpu; /* threshold for boosting gpu. */
- u32 bst_pp; /* threshold for boosting PP. */
-
- u32 *clk;
- u32 *clk_sample;
- u32 clk_len;
- u32 have_switch; /* have clock gate switch or not. */
-
- mali_dvfs_threshold_table *dvfs_table;
- struct mali_gpu_clk_item *clk_items;
- u32 dvfs_table_size;
-
- mali_scale_info_t scale_info;
- u32 maxclk_sysfs;
- u32 maxpp_sysfs;
-
- /* set upper limit of pp or frequency, for THERMAL thermal or band width saving.*/
- u32 limit_on;
-
- /* for boost up gpu by user. */
- void (*plat_preheat)(void);
-
- struct platform_device *pdev;
- void __iomem *reg_base_hiubus;
- void __iomem *reg_base_aobus;
- struct work_struct wq_work;
- struct clk *clk_mali;
- struct clk *clk_mali_0;
- struct clk *clk_mali_1;
-} mali_plat_info_t;
-mali_plat_info_t* get_mali_plat_data(void);
-
-/**
- * Initialize core scaling policy.
- *
- * @note The core scaling policy will assume that all PP cores are on initially.
- *
- * @param num_pp_cores Total number of PP cores.
- */
-int mali_core_scaling_init(mali_plat_info_t*);
-
-/**
- * Terminate core scaling policy.
- */
-void mali_core_scaling_term(void);
-
-/**
- * cancel and flush scaling job queue.
- */
-void flush_scaling_job(void);
-
-/* get current state(pp, clk). */
-void get_mali_rt_clkpp(u32* clk, u32* pp);
-u32 set_mali_rt_clkpp(u32 clk, u32 pp, u32 flush);
-void revise_mali_rt(void);
-/* get max gpu clk level of this chip*/
-int get_gpu_max_clk_level(void);
-
-/* get or set the scale mode. */
-u32 get_mali_schel_mode(void);
-void set_mali_schel_mode(u32 mode);
-
-/* for frequency reporter in DS-5 streamline. */
-u32 get_current_frequency(void);
-void mali_dev_freeze(void);
-void mali_dev_restore(void);
-
-extern int mali_pm_statue;
-#endif /* __ARM_CORE_SCALING_H__ */
+++ /dev/null
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <linux/clk-provider.h>
-#include <linux/clk.h>
-#include <linux/of_address.h>
-#include <linux/delay.h>
-#include <linux/mali/mali_utgard.h>
-#include <linux/amlogic/cpu_version.h>
-#include "mali_scaling.h"
-#include "mali_clock.h"
-
-#ifndef AML_CLK_LOCK_ERROR
-#define AML_CLK_LOCK_ERROR 1
-#endif
-#define GXBBM_MAX_GPU_FREQ 700000000UL
-struct clk;
-static unsigned gpu_dbg_level = 0;
-module_param(gpu_dbg_level, uint, 0644);
-MODULE_PARM_DESC(gpu_dbg_level, "gpu debug level");
-
-#define gpu_dbg(level, fmt, arg...) \
- do { \
- if (gpu_dbg_level >= (level)) \
- printk("gpu_debug"fmt , ## arg); \
- } while (0)
-
-#define GPU_CLK_DBG(fmt, arg...)
-
-//disable print
-#define _dev_info(...)
-
-//static DEFINE_SPINLOCK(lock);
-static mali_plat_info_t* pmali_plat = NULL;
-//static u32 mali_extr_backup = 0;
-//static u32 mali_extr_sample_backup = 0;
-struct timeval start;
-struct timeval end;
-
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 16))
-int mali_clock_init_clk_tree(struct platform_device* pdev)
-{
- mali_dvfs_threshold_table *dvfs_tbl = &pmali_plat->dvfs_table[pmali_plat->def_clock];
- struct clk *clk_mali_0_parent = dvfs_tbl->clkp_handle;
- struct clk *clk_mali_0 = pmali_plat->clk_mali_0;
-#ifdef AML_CLK_LOCK_ERROR
- struct clk *clk_mali_1 = pmali_plat->clk_mali_1;
-#endif
- struct clk *clk_mali = pmali_plat->clk_mali;
-
- clk_set_parent(clk_mali_0, clk_mali_0_parent);
-
- clk_prepare_enable(clk_mali_0);
-
- clk_set_parent(clk_mali, clk_mali_0);
-
-#ifdef AML_CLK_LOCK_ERROR
- clk_set_parent(clk_mali_1, clk_mali_0_parent);
- clk_prepare_enable(clk_mali_1);
-#endif
-
- GPU_CLK_DBG("%s:enable(%d), %s:enable(%d)\n",
- clk_mali_0->name, clk_mali_0->enable_count,
- clk_mali_0_parent->name, clk_mali_0_parent->enable_count);
-
- return 0;
-}
-
-int mali_clock_init(mali_plat_info_t *pdev)
-{
- *pdev = *pdev;
- return 0;
-}
-
-int mali_clock_critical(critical_t critical, size_t param)
-{
- int ret = 0;
-
- ret = critical(param);
-
- return ret;
-}
-
-static int critical_clock_set(size_t param)
-{
- int ret = 0;
- unsigned int idx = param;
- mali_dvfs_threshold_table *dvfs_tbl = &pmali_plat->dvfs_table[idx];
-
- struct clk *clk_mali_0 = pmali_plat->clk_mali_0;
- struct clk *clk_mali_1 = pmali_plat->clk_mali_1;
- struct clk *clk_mali_x = NULL;
- struct clk *clk_mali_x_parent = NULL;
- struct clk *clk_mali_x_old = NULL;
- struct clk *clk_mali = pmali_plat->clk_mali;
- unsigned long time_use=0;
-
- clk_mali_x_old = clk_get_parent(clk_mali);
-
- if (!clk_mali_x_old) {
- printk("gpu: could not get clk_mali_x_old or clk_mali_x_old\n");
- return 0;
- }
- if (clk_mali_x_old == clk_mali_0) {
- clk_mali_x = clk_mali_1;
- } else if (clk_mali_x_old == clk_mali_1) {
- clk_mali_x = clk_mali_0;
- } else {
- printk("gpu: unmatched clk_mali_x_old\n");
- return 0;
- }
-
- GPU_CLK_DBG("idx=%d, clk_freq=%d\n", idx, dvfs_tbl->clk_freq);
- clk_mali_x_parent = dvfs_tbl->clkp_handle;
- if (!clk_mali_x_parent) {
- printk("gpu: could not get clk_mali_x_parent\n");
- return 0;
- }
-
- GPU_CLK_DBG();
- ret = clk_set_rate(clk_mali_x_parent, dvfs_tbl->clkp_freq);
- GPU_CLK_DBG();
- ret = clk_set_parent(clk_mali_x, clk_mali_x_parent);
- GPU_CLK_DBG();
- ret = clk_set_rate(clk_mali_x, dvfs_tbl->clk_freq);
- GPU_CLK_DBG();
-#ifndef AML_CLK_LOCK_ERROR
- ret = clk_prepare_enable(clk_mali_x);
-#endif
- GPU_CLK_DBG("new %s:enable(%d)\n", clk_mali_x->name, clk_mali_x->enable_count);
- do_gettimeofday(&start);
- udelay(1);// delay 10ns
- do_gettimeofday(&end);
- ret = clk_set_parent(clk_mali, clk_mali_x);
- GPU_CLK_DBG();
-
-#ifndef AML_CLK_LOCK_ERROR
- clk_disable_unprepare(clk_mali_x_old);
-#endif
- GPU_CLK_DBG("old %s:enable(%d)\n", clk_mali_x_old->name, clk_mali_x_old->enable_count);
- time_use = (end.tv_sec - start.tv_sec)*1000000 + end.tv_usec - start.tv_usec;
- GPU_CLK_DBG("step 1, mali_mux use: %ld us\n", time_use);
-
- return 0;
-}
-
-int mali_clock_set(unsigned int clock)
-{
- return mali_clock_critical(critical_clock_set, (size_t)clock);
-}
-
-void disable_clock(void)
-{
- struct clk *clk_mali = pmali_plat->clk_mali;
- struct clk *clk_mali_x = NULL;
-
- clk_mali_x = clk_get_parent(clk_mali);
- GPU_CLK_DBG();
-#ifndef AML_CLK_LOCK_ERROR
- clk_disable_unprepare(clk_mali_x);
-#endif
- GPU_CLK_DBG();
-}
-
-void enable_clock(void)
-{
- struct clk *clk_mali = pmali_plat->clk_mali;
- struct clk *clk_mali_x = NULL;
-
- clk_mali_x = clk_get_parent(clk_mali);
- GPU_CLK_DBG();
-#ifndef AML_CLK_LOCK_ERROR
- clk_prepare_enable(clk_mali_x);
-#endif
- GPU_CLK_DBG();
-}
-
-u32 get_mali_freq(u32 idx)
-{
- if (!mali_pm_statue) {
- return pmali_plat->clk_sample[idx];
- } else {
- return 0;
- }
-}
-
-void set_str_src(u32 data)
-{
- printk("gpu: %s, %s, %d\n", __FILE__, __func__, __LINE__);
-}
-
-int mali_dt_info(struct platform_device *pdev, struct mali_plat_info_t *mpdata)
-{
- struct device_node *gpu_dn = pdev->dev.of_node;
- struct device_node *gpu_clk_dn;
- struct mali_gpu_clk_item *clk_item;
- phandle dvfs_clk_hdl;
- mali_dvfs_threshold_table *dvfs_tbl = NULL;
- uint32_t *clk_sample = NULL;
-
- struct property *prop;
- const __be32 *p;
- int length = 0, i = 0;
- u32 u;
-
- int ret = 0;
- if (!gpu_dn) {
- dev_notice(&pdev->dev, "gpu device node not right\n");
- return -ENODEV;
- }
-
- ret = of_property_read_u32(gpu_dn,"num_of_pp",
- &mpdata->cfg_pp);
- if (ret) {
- dev_notice(&pdev->dev, "set max pp to default 6\n");
- mpdata->cfg_pp = 6;
- }
- mpdata->scale_info.maxpp = mpdata->cfg_pp;
- mpdata->maxpp_sysfs = mpdata->cfg_pp;
- _dev_info(&pdev->dev, "max pp is %d\n", mpdata->scale_info.maxpp);
-
- ret = of_property_read_u32(gpu_dn,"min_pp",
- &mpdata->cfg_min_pp);
- if (ret) {
- dev_notice(&pdev->dev, "set min pp to default 1\n");
- mpdata->cfg_min_pp = 1;
- }
- mpdata->scale_info.minpp = mpdata->cfg_min_pp;
- _dev_info(&pdev->dev, "min pp is %d\n", mpdata->scale_info.minpp);
-
- ret = of_property_read_u32(gpu_dn,"min_clk",
- &mpdata->cfg_min_clock);
- if (ret) {
- dev_notice(&pdev->dev, "set min clk default to 0\n");
- mpdata->cfg_min_clock = 0;
- }
- mpdata->scale_info.minclk = mpdata->cfg_min_clock;
- _dev_info(&pdev->dev, "min clk is %d\n", mpdata->scale_info.minclk);
-
- mpdata->reg_base_hiubus = of_iomap(gpu_dn, 1);
- _dev_info(&pdev->dev, "hiu io source 0x%p\n", mpdata->reg_base_hiubus);
-
- mpdata->reg_base_aobus = of_iomap(gpu_dn, 2);
- _dev_info(&pdev->dev, "hiu io source 0x%p\n", mpdata->reg_base_aobus);
-
- ret = of_property_read_u32(gpu_dn,"sc_mpp",
- &mpdata->sc_mpp);
- if (ret) {
- dev_notice(&pdev->dev, "set pp used most of time default to %d\n", mpdata->cfg_pp);
- mpdata->sc_mpp = mpdata->cfg_pp;
- }
- _dev_info(&pdev->dev, "num of pp used most of time %d\n", mpdata->sc_mpp);
-
- of_get_property(gpu_dn, "tbl", &length);
-
- length = length /sizeof(u32);
- _dev_info(&pdev->dev, "clock dvfs cfg table size is %d\n", length);
-
- mpdata->dvfs_table = devm_kzalloc(&pdev->dev,
- sizeof(struct mali_dvfs_threshold_table)*length,
- GFP_KERNEL);
- dvfs_tbl = mpdata->dvfs_table;
- if (mpdata->dvfs_table == NULL) {
- dev_err(&pdev->dev, "failed to alloc dvfs table\n");
- return -ENOMEM;
- }
- mpdata->clk_sample = devm_kzalloc(&pdev->dev, sizeof(u32)*length, GFP_KERNEL);
- if (mpdata->clk_sample == NULL) {
- dev_err(&pdev->dev, "failed to alloc clk_sample table\n");
- return -ENOMEM;
- }
- clk_sample = mpdata->clk_sample;
-///////////
- mpdata->clk_items = devm_kzalloc(&pdev->dev, sizeof(struct mali_gpu_clk_item) * length, GFP_KERNEL);
- if (mpdata->clk_items == NULL) {
- dev_err(&pdev->dev, "failed to alloc clk_item table\n");
- return -ENOMEM;
- }
- clk_item = mpdata->clk_items;
-//
- of_property_for_each_u32(gpu_dn, "tbl", prop, p, u) {
- dvfs_clk_hdl = (phandle) u;
- gpu_clk_dn = of_find_node_by_phandle(dvfs_clk_hdl);
- ret = of_property_read_u32(gpu_clk_dn,"clk_freq", &dvfs_tbl->clk_freq);
- if (ret) {
- dev_notice(&pdev->dev, "read clk_freq failed\n");
- }
-#if 0
-#ifdef MESON_CPU_VERSION_OPS
- if (is_meson_gxbbm_cpu()) {
- if (dvfs_tbl->clk_freq >= GXBBM_MAX_GPU_FREQ)
- continue;
- }
-#endif
-#endif
- ret = of_property_read_string(gpu_clk_dn,"clk_parent",
- &dvfs_tbl->clk_parent);
- if (ret) {
- dev_notice(&pdev->dev, "read clk_parent failed\n");
- }
- dvfs_tbl->clkp_handle = devm_clk_get(&pdev->dev, dvfs_tbl->clk_parent);
- if (IS_ERR(dvfs_tbl->clkp_handle)) {
- dev_notice(&pdev->dev, "failed to get %s's clock pointer\n", dvfs_tbl->clk_parent);
- }
- ret = of_property_read_u32(gpu_clk_dn,"clkp_freq", &dvfs_tbl->clkp_freq);
- if (ret) {
- dev_notice(&pdev->dev, "read clk_parent freq failed\n");
- }
- ret = of_property_read_u32(gpu_clk_dn,"voltage", &dvfs_tbl->voltage);
- if (ret) {
- dev_notice(&pdev->dev, "read voltage failed\n");
- }
- ret = of_property_read_u32(gpu_clk_dn,"keep_count", &dvfs_tbl->keep_count);
- if (ret) {
- dev_notice(&pdev->dev, "read keep_count failed\n");
- }
- //downthreshold and upthreshold shall be u32
- ret = of_property_read_u32_array(gpu_clk_dn,"threshold",
- &dvfs_tbl->downthreshold, 2);
- if (ret) {
- dev_notice(&pdev->dev, "read threshold failed\n");
- }
- dvfs_tbl->freq_index = i;
- clk_item->clock = dvfs_tbl->clk_freq / 1000000;
- clk_item->vol = dvfs_tbl->voltage;
-
- *clk_sample = dvfs_tbl->clk_freq / 1000000;
-
- dvfs_tbl ++;
- clk_item ++;
- clk_sample ++;
- i++;
- mpdata->dvfs_table_size ++;
- }
-
- ret = of_property_read_u32(gpu_dn,"max_clk",
- &mpdata->cfg_clock);
- if (ret) {
- dev_notice(&pdev->dev, "max clk set %d\n", mpdata->dvfs_table_size-2);
- mpdata->cfg_clock = mpdata->dvfs_table_size-2;
- }
-
- mpdata->cfg_clock_bkup = mpdata->cfg_clock;
- mpdata->maxclk_sysfs = mpdata->cfg_clock;
- mpdata->scale_info.maxclk = mpdata->cfg_clock;
- _dev_info(&pdev->dev, "max clk is %d\n", mpdata->scale_info.maxclk);
-
- ret = of_property_read_u32(gpu_dn,"turbo_clk",
- &mpdata->turbo_clock);
- if (ret) {
- dev_notice(&pdev->dev, "turbo clk set to %d\n", mpdata->dvfs_table_size-1);
- mpdata->turbo_clock = mpdata->dvfs_table_size-1;
- }
- _dev_info(&pdev->dev, "turbo clk is %d\n", mpdata->turbo_clock);
-
- ret = of_property_read_u32(gpu_dn,"def_clk",
- &mpdata->def_clock);
- if (ret) {
- dev_notice(&pdev->dev, "default clk set to %d\n", mpdata->dvfs_table_size/2-1);
- mpdata->def_clock = mpdata->dvfs_table_size/2 - 1;
- }
- _dev_info(&pdev->dev, "default clk is %d\n", mpdata->def_clock);
-
- dvfs_tbl = mpdata->dvfs_table;
- clk_sample = mpdata->clk_sample;
- for (i = 0; i< mpdata->dvfs_table_size; i++) {
- _dev_info(&pdev->dev, "====================%d====================\n"
- "clk_freq=%10d, clk_parent=%9s, voltage=%d, keep_count=%d, threshod=<%d %d>, clk_sample=%d\n",
- i,
- dvfs_tbl->clk_freq, dvfs_tbl->clk_parent,
- dvfs_tbl->voltage, dvfs_tbl->keep_count,
- dvfs_tbl->downthreshold, dvfs_tbl->upthreshold, *clk_sample);
- dvfs_tbl ++;
- clk_sample ++;
- }
- _dev_info(&pdev->dev, "clock dvfs table size is %d\n", mpdata->dvfs_table_size);
-
- mpdata->clk_mali = devm_clk_get(&pdev->dev, "clk_mali");
- mpdata->clk_mali_0 = devm_clk_get(&pdev->dev, "clk_mali_0");
- mpdata->clk_mali_1 = devm_clk_get(&pdev->dev, "clk_mali_1");
- if (IS_ERR(mpdata->clk_mali) || IS_ERR(mpdata->clk_mali_0) || IS_ERR(mpdata->clk_mali_1)) {
- dev_err(&pdev->dev, "failed to get clock pointer\n");
- return -EFAULT;
- }
-
- pmali_plat = mpdata;
- mpdata->pdev = pdev;
- return 0;
-}
-#else
-int mali_clock_init_clk_tree(struct platform_device* pdev)
-{
-
- //mali_dvfs_threshold_table *dvfs_tbl = &pmali_plat->dvfs_table[pmali_plat->def_clock];
- struct clk *clk_mali = pmali_plat->clk_mali;
-
- clk_prepare_enable(clk_mali);
-
- return 0;
-}
-
-int mali_clock_init(mali_plat_info_t *pdev)
-{
- *pdev = *pdev;
- return 0;
-}
-
-int mali_clock_critical(critical_t critical, size_t param)
-{
- int ret = 0;
-
- ret = critical(param);
-
- return ret;
-}
-
-static int critical_clock_set(size_t param)
-{
- int ret = 0;
- unsigned int idx = param;
- mali_dvfs_threshold_table *dvfs_tbl = &pmali_plat->dvfs_table[idx];
-
- struct clk *clk_mali = pmali_plat->clk_mali;
- unsigned long time_use=0;
-
-
- GPU_CLK_DBG();
- do_gettimeofday(&start);
- ret = clk_set_rate(clk_mali, dvfs_tbl->clk_freq);
- do_gettimeofday(&end);
- GPU_CLK_DBG();
-
-#ifndef AML_CLK_LOCK_ERROR
- clk_disable_unprepare(clk_mali_x_old);
-#endif
- time_use = (end.tv_sec - start.tv_sec)*1000000 + end.tv_usec - start.tv_usec;
- GPU_CLK_DBG("step 1, mali_mux use: %ld us\n", time_use);
-
- return 0;
-}
-
-int mali_clock_set(unsigned int clock)
-{
- return mali_clock_critical(critical_clock_set, (size_t)clock);
-}
-
-void disable_clock(void)
-{
-#ifndef AML_CLK_LOCK_ERROR
- struct clk *clk_mali = pmali_plat->clk_mali;
-
- GPU_CLK_DBG();
- clk_disable_unprepare(clk_mali);
-#endif
- GPU_CLK_DBG();
-}
-
-void enable_clock(void)
-{
-#ifndef AML_CLK_LOCK_ERROR
- struct clk *clk_mali = pmali_plat->clk_mali;
-
- clk_prepare_enable(clk_mali);
-#endif
- GPU_CLK_DBG();
-}
-
-u32 get_mali_freq(u32 idx)
-{
- if (!mali_pm_statue) {
- return pmali_plat->clk_sample[idx];
- } else {
- return 0;
- }
-}
-
-void set_str_src(u32 data)
-{
- printk("gpu: %s, %s, %d\n", __FILE__, __func__, __LINE__);
-}
-
-int mali_dt_info(struct platform_device *pdev, struct mali_plat_info_t *mpdata)
-{
- struct device_node *gpu_dn = pdev->dev.of_node;
- struct device_node *gpu_clk_dn;
- struct mali_gpu_clk_item *clk_item;
- phandle dvfs_clk_hdl;
- mali_dvfs_threshold_table *dvfs_tbl = NULL;
- uint32_t *clk_sample = NULL;
-
- struct property *prop;
- const __be32 *p;
- int length = 0, i = 0;
- u32 u;
-
- int ret = 0;
- if (!gpu_dn) {
- dev_notice(&pdev->dev, "gpu device node not right\n");
- return -ENODEV;
- }
-
- ret = of_property_read_u32(gpu_dn,"num_of_pp",
- &mpdata->cfg_pp);
- if (ret) {
- dev_notice(&pdev->dev, "set max pp to default 6\n");
- mpdata->cfg_pp = 6;
- }
- mpdata->scale_info.maxpp = mpdata->cfg_pp;
- mpdata->maxpp_sysfs = mpdata->cfg_pp;
- _dev_info(&pdev->dev, "max pp is %d\n", mpdata->scale_info.maxpp);
-
- ret = of_property_read_u32(gpu_dn,"min_pp",
- &mpdata->cfg_min_pp);
- if (ret) {
- dev_notice(&pdev->dev, "set min pp to default 1\n");
- mpdata->cfg_min_pp = 1;
- }
- mpdata->scale_info.minpp = mpdata->cfg_min_pp;
- _dev_info(&pdev->dev, "min pp is %d\n", mpdata->scale_info.minpp);
-
- ret = of_property_read_u32(gpu_dn,"min_clk",
- &mpdata->cfg_min_clock);
- if (ret) {
- dev_notice(&pdev->dev, "set min clk default to 0\n");
- mpdata->cfg_min_clock = 0;
- }
- mpdata->scale_info.minclk = mpdata->cfg_min_clock;
- _dev_info(&pdev->dev, "min clk is %d\n", mpdata->scale_info.minclk);
-
- mpdata->reg_base_hiubus = of_iomap(gpu_dn, 1);
- _dev_info(&pdev->dev, "hiu io source 0x%p\n", mpdata->reg_base_hiubus);
-
- mpdata->reg_base_aobus = of_iomap(gpu_dn, 2);
- _dev_info(&pdev->dev, "hiu io source 0x%p\n", mpdata->reg_base_aobus);
-
- ret = of_property_read_u32(gpu_dn,"sc_mpp",
- &mpdata->sc_mpp);
- if (ret) {
- dev_notice(&pdev->dev, "set pp used most of time default to %d\n", mpdata->cfg_pp);
- mpdata->sc_mpp = mpdata->cfg_pp;
- }
- _dev_info(&pdev->dev, "num of pp used most of time %d\n", mpdata->sc_mpp);
-
- of_get_property(gpu_dn, "tbl", &length);
-
- length = length /sizeof(u32);
- _dev_info(&pdev->dev, "clock dvfs cfg table size is %d\n", length);
-
- mpdata->dvfs_table = devm_kzalloc(&pdev->dev,
- sizeof(struct mali_dvfs_threshold_table)*length,
- GFP_KERNEL);
- dvfs_tbl = mpdata->dvfs_table;
- if (mpdata->dvfs_table == NULL) {
- dev_err(&pdev->dev, "failed to alloc dvfs table\n");
- return -ENOMEM;
- }
- mpdata->clk_sample = devm_kzalloc(&pdev->dev, sizeof(u32)*length, GFP_KERNEL);
- if (mpdata->clk_sample == NULL) {
- dev_err(&pdev->dev, "failed to alloc clk_sample table\n");
- return -ENOMEM;
- }
- clk_sample = mpdata->clk_sample;
-///////////
- mpdata->clk_items = devm_kzalloc(&pdev->dev, sizeof(struct mali_gpu_clk_item) * length, GFP_KERNEL);
- if (mpdata->clk_items == NULL) {
- dev_err(&pdev->dev, "failed to alloc clk_item table\n");
- return -ENOMEM;
- }
- clk_item = mpdata->clk_items;
-//
- of_property_for_each_u32(gpu_dn, "tbl", prop, p, u) {
- dvfs_clk_hdl = (phandle) u;
- gpu_clk_dn = of_find_node_by_phandle(dvfs_clk_hdl);
- ret = of_property_read_u32(gpu_clk_dn,"clk_freq", &dvfs_tbl->clk_freq);
- if (ret) {
- dev_notice(&pdev->dev, "read clk_freq failed\n");
- }
-#if 0
-#ifdef MESON_CPU_VERSION_OPS
- if (is_meson_gxbbm_cpu()) {
- if (dvfs_tbl->clk_freq >= GXBBM_MAX_GPU_FREQ)
- continue;
- }
-#endif
-#endif
-#if 0
- ret = of_property_read_string(gpu_clk_dn,"clk_parent",
- &dvfs_tbl->clk_parent);
- if (ret) {
- dev_notice(&pdev->dev, "read clk_parent failed\n");
- }
- dvfs_tbl->clkp_handle = devm_clk_get(&pdev->dev, dvfs_tbl->clk_parent);
- if (IS_ERR(dvfs_tbl->clkp_handle)) {
- dev_notice(&pdev->dev, "failed to get %s's clock pointer\n", dvfs_tbl->clk_parent);
- }
- ret = of_property_read_u32(gpu_clk_dn,"clkp_freq", &dvfs_tbl->clkp_freq);
- if (ret) {
- dev_notice(&pdev->dev, "read clk_parent freq failed\n");
- }
-#endif
- ret = of_property_read_u32(gpu_clk_dn,"voltage", &dvfs_tbl->voltage);
- if (ret) {
- dev_notice(&pdev->dev, "read voltage failed\n");
- }
- ret = of_property_read_u32(gpu_clk_dn,"keep_count", &dvfs_tbl->keep_count);
- if (ret) {
- dev_notice(&pdev->dev, "read keep_count failed\n");
- }
- //downthreshold and upthreshold shall be u32
- ret = of_property_read_u32_array(gpu_clk_dn,"threshold",
- &dvfs_tbl->downthreshold, 2);
- if (ret) {
- dev_notice(&pdev->dev, "read threshold failed\n");
- }
- dvfs_tbl->freq_index = i;
- clk_item->clock = dvfs_tbl->clk_freq / 1000000;
- clk_item->vol = dvfs_tbl->voltage;
-
- *clk_sample = dvfs_tbl->clk_freq / 1000000;
-
- dvfs_tbl ++;
- clk_item ++;
- clk_sample ++;
- i++;
- mpdata->dvfs_table_size ++;
- }
-
- ret = of_property_read_u32(gpu_dn,"max_clk",
- &mpdata->cfg_clock);
- if (ret) {
- dev_notice(&pdev->dev, "max clk set %d\n", mpdata->dvfs_table_size-2);
- mpdata->cfg_clock = mpdata->dvfs_table_size-2;
- }
-
- mpdata->cfg_clock_bkup = mpdata->cfg_clock;
- mpdata->maxclk_sysfs = mpdata->cfg_clock;
- mpdata->scale_info.maxclk = mpdata->cfg_clock;
- _dev_info(&pdev->dev, "max clk is %d\n", mpdata->scale_info.maxclk);
-
- ret = of_property_read_u32(gpu_dn,"turbo_clk",
- &mpdata->turbo_clock);
- if (ret) {
- dev_notice(&pdev->dev, "turbo clk set to %d\n", mpdata->dvfs_table_size-1);
- mpdata->turbo_clock = mpdata->dvfs_table_size-1;
- }
- _dev_info(&pdev->dev, "turbo clk is %d\n", mpdata->turbo_clock);
-
- ret = of_property_read_u32(gpu_dn,"def_clk",
- &mpdata->def_clock);
- if (ret) {
- dev_notice(&pdev->dev, "default clk set to %d\n", mpdata->dvfs_table_size/2-1);
- mpdata->def_clock = mpdata->dvfs_table_size/2 - 1;
- }
- _dev_info(&pdev->dev, "default clk is %d\n", mpdata->def_clock);
-
- dvfs_tbl = mpdata->dvfs_table;
- clk_sample = mpdata->clk_sample;
- for (i = 0; i< mpdata->dvfs_table_size; i++) {
- _dev_info(&pdev->dev, "====================%d====================\n"
- "clk_freq=%10d, clk_parent=%9s, voltage=%d, keep_count=%d, threshod=<%d %d>, clk_sample=%d\n",
- i,
- dvfs_tbl->clk_freq, dvfs_tbl->clk_parent,
- dvfs_tbl->voltage, dvfs_tbl->keep_count,
- dvfs_tbl->downthreshold, dvfs_tbl->upthreshold, *clk_sample);
- dvfs_tbl ++;
- clk_sample ++;
- }
- _dev_info(&pdev->dev, "clock dvfs table size is %d\n", mpdata->dvfs_table_size);
-
- mpdata->clk_mali = devm_clk_get(&pdev->dev, "gpu_mux");
-#if 0
- mpdata->clk_mali_0 = devm_clk_get(&pdev->dev, "clk_mali_0");
- mpdata->clk_mali_1 = devm_clk_get(&pdev->dev, "clk_mali_1");
-#endif
- if (IS_ERR(mpdata->clk_mali)) {
- dev_err(&pdev->dev, "failed to get clock pointer\n");
- return -EFAULT;
- }
-
- pmali_plat = mpdata;
- mpdata->pdev = pdev;
- return 0;
-}
-
-#endif
+++ /dev/null
-#ifndef __MALI_CLOCK_H__
-#define __MALI_CLOCK_H__
-#include <linux/version.h>
-#include <linux/pm.h>
-#include <linux/io.h>
-#include <linux/types.h>
-#include <linux/of.h>
-
-#include <asm/io.h>
-#include <linux/clk.h>
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 29))
-#include <linux/amlogic/iomap.h>
-#endif
-
-#ifndef HHI_MALI_CLK_CNTL
-#define HHI_MALI_CLK_CNTL 0x6C
-#define mplt_read(r) readl((pmali_plat->reg_base_hiubus) + ((r)<<2))
-#define mplt_write(r, v) writel((v), ((pmali_plat->reg_base_hiubus) + ((r)<<2)))
-#define mplt_setbits(r, m) mplt_write((r), (mplt_read(r) | (m)));
-#define mplt_clrbits(r, m) mplt_write((r), (mplt_read(r) & (~(m))));
-#endif
-
-//extern int mali_clock_init(struct platform_device *dev);
-int mali_clock_init_clk_tree(struct platform_device *pdev);
-
-typedef int (*critical_t)(size_t param);
-int mali_clock_critical(critical_t critical, size_t param);
-
-int mali_clock_init(mali_plat_info_t*);
-int mali_clock_set(unsigned int index);
-void disable_clock(void);
-void enable_clock(void);
-u32 get_mali_freq(u32 idx);
-void set_str_src(u32 data);
-int mali_dt_info(struct platform_device *pdev,
- struct mali_plat_info_t *mpdata);
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2013 ARM Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
- *
- * A copy of the licence is included with the program, and can also be obtained from Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-/**
- * @file arm_core_scaling.c
- * Example core scaling policy.
- */
-
-#include <linux/version.h>
-#include <linux/module.h>
-#include <linux/workqueue.h>
-#include <linux/mali/mali_utgard.h>
-#include <mali_kernel_common.h>
-#include <mali_osk_profiling.h>
-#include <linux/time.h>
-
-//#include <linux/amlogic/amports/gp_pll.h>
-#include "meson_main2.h"
-
-
-static int currentStep;
-static int scaling_mode = MALI_PP_FS_SCALING;
-//static int scaling_mode = MALI_SCALING_DISABLE;
-//static int scaling_mode = MALI_PP_SCALING;
-
-//static struct gp_pll_user_handle_s *gp_pll_user_gpu;
-//static int is_gp_pll_get;
-//static int is_gp_pll_put;
-
-static unsigned scaling_dbg_level = 0;
-module_param(scaling_dbg_level, uint, 0644);
-MODULE_PARM_DESC(scaling_dbg_level , "scaling debug level");
-
-static mali_plat_info_t* pmali_plat = NULL;
-static struct workqueue_struct *mali_scaling_wq = NULL;
-//static DEFINE_SPINLOCK(lock);
-
-static int cur_gpu_clk_index = 0;
-static int exec_gpu_clk_index = 0;
-#define scalingdbg(level, fmt, arg...) \
- do { \
- if (scaling_dbg_level >= (level)) \
- printk(fmt , ## arg); \
- } while (0)
-
-struct mali_gpu_clock meson_gpu_clk_info = {
- .item = NULL,
- .num_of_steps = 0,
-};
-
-u32 revise_set_clk(u32 val, u32 flush)
-{
- u32 ret = 0;
- return ret;
-}
-
-void get_mali_rt_clkpp(u32* clk, u32* pp)
-{
-}
-
-u32 set_mali_rt_clkpp(u32 clk, u32 pp, u32 flush)
-{
- u32 ret = 0;
- return ret;
-}
-
-void revise_mali_rt(void)
-{
-}
-
-static void do_scaling(struct work_struct *work)
-{
- //unsigned long flags;
- mali_plat_info_t *pinfo = container_of(work, struct mali_plat_info_t, wq_work);
-
- *pinfo = *pinfo;
- //mali_dev_pause();
- //spin_lock_irqsave(&lock, flags);
- mali_clock_set(exec_gpu_clk_index);
- cur_gpu_clk_index = exec_gpu_clk_index;
- //spin_unlock_irqrestore(&lock, flags);
- //mali_dev_resume();
-}
-void flush_scaling_job(void)
-{
- if (mali_scaling_wq == NULL) return;
-
- flush_workqueue(mali_scaling_wq);
- printk("%s, %d\n", __func__, __LINE__);
-}
-
-
-int mali_core_scaling_init(mali_plat_info_t *mali_plat)
-{
- pmali_plat = mali_plat;
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)
- mali_scaling_wq = alloc_workqueue("gpu_scaling_wq", WQ_HIGHPRI | WQ_UNBOUND, 0);
-#else
- mali_scaling_wq = create_workqueue("gpu_scaling_wq");
-#endif
- INIT_WORK(&pmali_plat->wq_work, do_scaling);
- if (mali_scaling_wq == NULL) printk("Unable to create gpu scaling workqueue\n");
-
- meson_gpu_clk_info.num_of_steps = pmali_plat->scale_info.maxclk;
-
- return 0;
-}
-
-void mali_core_scaling_term(void)
-{
- flush_scaling_job();
- destroy_workqueue(mali_scaling_wq);
- mali_scaling_wq = NULL;
-}
-
-void mali_pp_scaling_update(struct mali_gpu_utilization_data *data)
-{
-}
-
-void mali_pp_fs_scaling_update(struct mali_gpu_utilization_data *data)
-{
-}
-
-u32 get_mali_schel_mode(void)
-{
- return scaling_mode;
-}
-
-void set_mali_schel_mode(u32 mode)
-{
- scaling_mode = mode;
- if (scaling_mode == MALI_TURBO_MODE) {
- printk ("turbo mode\n");
- pmali_plat->limit_on = 0;
- meson_gpu_clk_info.num_of_steps = pmali_plat->turbo_clock;
- } else {
- printk ("not turbo mode\n");
- pmali_plat->limit_on = 1;
- meson_gpu_clk_info.num_of_steps = pmali_plat->scale_info.maxclk;
- }
-
- printk("total_enable_steps = %d\n", meson_gpu_clk_info.num_of_steps);
-}
-
-u32 get_current_frequency(void)
-{
- return get_mali_freq(currentStep);
-}
-
-void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data)
-{
-}
-
-void mali_dev_restore(void)
-{
- //TO add this
- //mali_perf_set_num_pp_cores(num_cores_enabled);
- if (pmali_plat && pmali_plat->pdev) {
- mali_clock_init_clk_tree(pmali_plat->pdev);
- } else {
- printk("error: init clock failed, pmali_plat=%p, pmali_plat->pdev=%p\n",
- pmali_plat, pmali_plat == NULL ? NULL: pmali_plat->pdev);
- }
-}
-
-/* Function that platfrom report it's clock info which driver can set, needed when CONFIG_MALI_DVFS enabled */
-static void meson_platform_get_clock_info(struct mali_gpu_clock **data) {
- if (pmali_plat) {
- meson_gpu_clk_info.item = pmali_plat->clk_items;
- meson_gpu_clk_info.num_of_steps = pmali_plat->scale_info.maxclk;
- printk("get clock info\n");
- } else {
- printk("error pmali_plat is null");
- }
- *data = &meson_gpu_clk_info;
-}
-
-/* Function that get the current clock info, needed when CONFIG_MALI_DVFS enabled */
-static int meson_platform_get_freq(void) {
- scalingdbg(1, "cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
- //dynamically changed the num of steps;
- return cur_gpu_clk_index;
-}
-
-/* Fuction that platform callback for freq setting, needed when CONFIG_MALI_DVFS enabled */
-static int meson_platform_set_freq(int setting_clock_step) {
-
- if (exec_gpu_clk_index == setting_clock_step) {
- return 0;
- }
-
- queue_work(mali_scaling_wq, &pmali_plat->wq_work);
- exec_gpu_clk_index = setting_clock_step;
- scalingdbg(1, "set cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
- return 0;
-}
-
-int mali_meson_get_gpu_data(struct mali_gpu_device_data *mgpu_data)
-{
- mgpu_data->get_clock_info = meson_platform_get_clock_info,
- mgpu_data->get_freq = meson_platform_get_freq,
- mgpu_data->set_freq = meson_platform_set_freq,
- mgpu_data->utilization_callback = NULL;
- return 0;
-}
+++ /dev/null
-/*
- * mali_platform.h
- *
- * Created on: Nov 8, 2013
- * Author: amlogic
- */
-
-#include <linux/kernel.h>
-#ifndef MALI_PLATFORM_H_
-#define MALI_PLATFORM_H_
-
-extern u32 mali_gp_reset_fail;
-extern u32 mali_core_timeout;
-
-#endif /* MALI_PLATFORM_H_ */
+++ /dev/null
-../mali_scaling.h
\ No newline at end of file
+++ /dev/null
-/*
- * Copyright (C) 2010, 2012-2014 Amlogic Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
- *
- */
-
-/**
- * @file mali_platform.c
- * Platform specific Mali driver functions for:
- * meson8m2 and the newer chip
- */
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#ifdef CONFIG_PM_RUNTIME
-#include <linux/pm_runtime.h>
-#endif
-#include <asm/io.h>
-#include <linux/mali/mali_utgard.h>
-#include "mali_kernel_common.h"
-#include <linux/dma-mapping.h>
-#include <linux/moduleparam.h>
-
-#include "mali_executor.h"
-#include "mali_scaling.h"
-#include "mali_clock.h"
-#include "meson_main2.h"
-
-int mali_pm_statue = 0;
-extern void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data);
-
-u32 mali_gp_reset_fail = 0;
-module_param(mali_gp_reset_fail, int, S_IRUSR | S_IWUSR | S_IWGRP | S_IRGRP | S_IROTH); /* rw-rw-r-- */
-MODULE_PARM_DESC(mali_gp_reset_fail, "times of failed to reset GP");
-u32 mali_core_timeout = 0;
-module_param(mali_core_timeout, int, S_IRUSR | S_IWUSR | S_IWGRP | S_IRGRP | S_IROTH); /* rw-rw-r-- */
-MODULE_PARM_DESC(mali_core_timeout, "timeout of failed to reset GP");
-
-static struct mali_gpu_device_data mali_gpu_data = {
-
-#if defined(CONFIG_ARCH_REALVIEW)
- .dedicated_mem_start = 0x80000000, /* Physical start address (use 0xD0000000 for old indirect setup) */
- .dedicated_mem_size = 0x10000000, /* 256MB */
-#endif
-#if defined(CONFIG_ARM64)
- .fb_start = 0x5f000000,
- .fb_size = 0x91000000,
-#else
- .fb_start = 0xe0000000,
- .fb_size = 0x01000000,
-#endif
- .control_interval = 200, /* 1000ms */
-};
-
-int mali_platform_device_init(struct platform_device *device)
-{
- int err = -1;
-
- err = mali_meson_init_start(device);
- if (0 != err) printk("mali init failed\n");
- err = mali_meson_get_gpu_data(&mali_gpu_data);
- if (0 != err) printk("mali get gpu data failed\n");
-
- err = platform_device_add_data(device, &mali_gpu_data, sizeof(mali_gpu_data));
-
- if (0 == err) {
- device->dev.type = &mali_pm_device; /* We should probably use the pm_domain instead of type on newer kernels */
-#ifdef CONFIG_PM_RUNTIME
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
- pm_runtime_set_autosuspend_delay(&device->dev, 1000);
- pm_runtime_use_autosuspend(&device->dev);
-#endif
- pm_runtime_enable(&device->dev);
-#endif
- mali_meson_init_finish(device);
- }
-
- mali_gp_reset_fail = 0;
- mali_core_timeout = 0;
-
- return err;
-}
-
-int mali_platform_device_deinit(struct platform_device *device)
-{
- MALI_IGNORE(device);
-
- printk("%s, %d\n", __FILE__, __LINE__);
- MALI_DEBUG_PRINT(4, ("mali_platform_device_deinit() called\n"));
-
-
- mali_meson_uninit(device);
-
- return 0;
-}
-
-#if 0
-static int param_set_core_scaling(const char *val, const struct kernel_param *kp)
-{
- int ret = param_set_int(val, kp);
- printk("%s, %d\n", __FILE__, __LINE__);
-
- if (1 == mali_core_scaling_enable) {
- mali_core_scaling_sync(mali_executor_get_num_cores_enabled());
- }
- return ret;
-}
-
-static struct kernel_param_ops param_ops_core_scaling = {
- .set = param_set_core_scaling,
- .get = param_get_int,
-};
-
-module_param_cb(mali_core_scaling_enable, ¶m_ops_core_scaling, &mali_core_scaling_enable, 0644);
-MODULE_PARM_DESC(mali_core_scaling_enable, "1 means to enable core scaling policy, 0 means to disable core scaling policy");
-#endif
+++ /dev/null
-/*
- * mali_platform.h
- *
- * Created on: Nov 8, 2013
- * Author: amlogic
- */
-
-#ifndef MESON_MAIN_H_
-#define MESON_MAIN_H_
-#include <linux/version.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#ifdef CONFIG_PM_RUNTIME
-#include <linux/pm_runtime.h>
-#endif
-#include <linux/mali/mali_utgard.h>
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/cpu.h>
-#endif
-
-#include "mali_scaling.h"
-#include "mali_clock.h"
-
-extern struct device_type mali_pm_device;
-extern int mali_pm_statue;
-
-u32 set_max_mali_freq(u32 idx);
-u32 get_max_mali_freq(void);
-
-int mali_meson_init_start(struct platform_device* ptr_plt_dev);
-int mali_meson_get_gpu_data(struct mali_gpu_device_data *mgpu_data);
-int mali_meson_init_finish(struct platform_device* ptr_plt_dev);
-int mali_meson_uninit(struct platform_device* ptr_plt_dev);
-int mali_light_suspend(struct device *device);
-int mali_light_resume(struct device *device);
-int mali_deep_suspend(struct device *device);
-int mali_deep_resume(struct device *device);
-
-#endif /* MESON_MAIN_H_ */
+++ /dev/null
-/*******************************************************************
- *
- * Copyright C 2013 by Amlogic, Inc. All Rights Reserved.
- *
- * Description:
- *
- * Author: Amlogic Software
- * Created: 2010/4/1 19:46
- *
- *******************************************************************/
-/* Standard Linux headers */
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/string.h>
-#include <linux/slab.h>
-#include <linux/list.h>
-
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/io.h>
-#include <plat/io.h>
-#include <asm/io.h>
-#endif
-
-#include <linux/mali/mali_utgard.h>
-#include <common/mali_kernel_common.h>
-#include <common/mali_pmu.h>
-//#include "mali_pp_scheduler.h"
-#include "meson_main.h"
-
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
-static ssize_t domain_stat_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- unsigned int val;
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
-
- val = readl(pmali_plat->reg_base_aobus + 0xf0) & 0xff;
- return sprintf(buf, "%x\n", val>>4);
- return 0;
-}
-
-#define PREHEAT_CMD "preheat"
-#define PLL2_CMD "mpl2" /* mpl2 [11] or [0xxxxxxx] */
-#define SCMPP_CMD "scmpp" /* scmpp [number of pp your want in most of time]. */
-#define BSTGPU_CMD "bstgpu" /* bstgpu [0-256] */
-#define BSTPP_CMD "bstpp" /* bstpp [0-256] */
-#define LIMIT_CMD "lmt" /* lmt [0 or 1] */
-#define MAX_TOKEN 20
-#define FULL_UTILIZATION 256
-
-static ssize_t mpgpu_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- char *pstart, *cprt = NULL;
- u32 val = 0;
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
-
- cprt = skip_spaces(buf);
- pstart = strsep(&cprt," ");
- if (strlen(pstart) < 1)
- goto quit;
-
- if (!strncmp(pstart, PREHEAT_CMD, MAX_TOKEN)) {
- if (pmali_plat->plat_preheat) {
- pmali_plat->plat_preheat();
- }
- } else if (!strncmp(pstart, PLL2_CMD, MAX_TOKEN)) {
- int base = 10;
- if ((strlen(cprt) > 2) && (cprt[0] == '0') &&
- (cprt[1] == 'x' || cprt[1] == 'X'))
- base = 16;
- if (kstrtouint(cprt, base, &val) <0)
- goto quit;
- if (val < 11)
- pmali_plat->cfg_clock = pmali_plat->cfg_clock_bkup;
- else
- pmali_plat->cfg_clock = pmali_plat->turbo_clock;
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- set_str_src(val);
- } else if (!strncmp(pstart, SCMPP_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
- if ((val > 0) && (val < pmali_plat->cfg_pp)) {
- pmali_plat->sc_mpp = val;
- }
- } else if (!strncmp(pstart, BSTGPU_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
- if ((val > 0) && (val < FULL_UTILIZATION)) {
- pmali_plat->bst_gpu = val;
- }
- } else if (!strncmp(pstart, BSTPP_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
- if ((val > 0) && (val < FULL_UTILIZATION)) {
- pmali_plat->bst_pp = val;
- }
- } else if (!strncmp(pstart, LIMIT_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
-
- if (val < 2) {
- pmali_plat->limit_on = val;
- if (val == 0) {
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- pmali_plat->scale_info.maxpp = pmali_plat->cfg_pp;
- revise_mali_rt();
- }
- }
- }
-quit:
- return count;
-}
-
-static ssize_t scale_mode_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- return sprintf(buf, "%d\n", get_mali_schel_mode());
-}
-
-static ssize_t scale_mode_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
-
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- {
- return -EINVAL;
- }
-
- set_mali_schel_mode(val);
-
- return count;
-}
-
-static ssize_t max_pp_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- printk("maxpp:%d, maxpp_sysfs:%d, total=%d\n",
- pmali_plat->scale_info.maxpp, pmali_plat->maxpp_sysfs,
- pmali_plat->cfg_pp);
- return sprintf(buf, "%d\n", pmali_plat->cfg_pp);
-}
-
-static ssize_t max_pp_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pmali_plat->cfg_pp) || (val < pinfo->minpp))
- return -EINVAL;
-
- pmali_plat->maxpp_sysfs = val;
- pinfo->maxpp = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t min_pp_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- return sprintf(buf, "%d\n", pmali_plat->scale_info.minpp);
-}
-
-static ssize_t min_pp_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pinfo->maxpp) || (val < 1))
- return -EINVAL;
-
- pinfo->minpp = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t max_freq_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- printk("maxclk:%d, maxclk_sys:%d, max gpu level=%d\n",
- pmali_plat->scale_info.maxclk, pmali_plat->maxclk_sysfs, get_gpu_max_clk_level());
- return sprintf(buf, "%d\n", get_gpu_max_clk_level());
-}
-
-static ssize_t max_freq_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pmali_plat->cfg_clock) || (val < pinfo->minclk))
- return -EINVAL;
-
- pmali_plat->maxclk_sysfs = val;
- pinfo->maxclk = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t min_freq_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- return sprintf(buf, "%d\n", pmali_plat->scale_info.minclk);
-}
-
-static ssize_t min_freq_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pinfo->maxclk))
- return -EINVAL;
-
- pinfo->minclk = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t freq_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- return sprintf(buf, "%d\n", get_current_frequency());
-}
-
-static ssize_t freq_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- u32 clk, pp;
- get_mali_rt_clkpp(&clk, &pp);
-
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- return -EINVAL;
-
- set_mali_rt_clkpp(val, pp, 1);
-
- return count;
-}
-
-static ssize_t current_pp_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- u32 clk, pp;
- get_mali_rt_clkpp(&clk, &pp);
- return sprintf(buf, "%d\n", pp);
-}
-
-static ssize_t current_pp_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- u32 clk, pp;
-
- get_mali_rt_clkpp(&clk, &pp);
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- {
- return -EINVAL;
- }
-
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- return -EINVAL;
-
- set_mali_rt_clkpp(clk, val, 1);
-
- return count;
-}
-
-static struct class_attribute mali_class_attrs[] = {
- __ATTR(domain_stat, 0644, domain_stat_read, NULL),
- __ATTR(mpgpucmd, 0644, NULL, mpgpu_write),
- __ATTR(scale_mode, 0644, scale_mode_read, scale_mode_write),
- __ATTR(min_freq, 0644, min_freq_read, min_freq_write),
- __ATTR(max_freq, 0644, max_freq_read, max_freq_write),
- __ATTR(min_pp, 0644, min_pp_read, min_pp_write),
- __ATTR(max_pp, 0644, max_pp_read, max_pp_write),
- __ATTR(cur_freq, 0644, freq_read, freq_write),
- __ATTR(cur_pp, 0644, current_pp_read, current_pp_write),
-};
-
-static struct class mpgpu_class = {
- .name = "mpgpu",
-};
-#endif
-
-int mpgpu_class_init(void)
-{
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
- int ret = 0;
- int i;
- int attr_num = ARRAY_SIZE(mali_class_attrs);
-
- ret = class_register(&mpgpu_class);
- if (ret) {
- printk(KERN_ERR "%s: class_register failed\n", __func__);
- return ret;
- }
- for (i = 0; i< attr_num; i++) {
- ret = class_create_file(&mpgpu_class, &mali_class_attrs[i]);
- if (ret) {
- printk(KERN_ERR "%d ST: class item failed to register\n", i);
- }
- }
- return ret;
-#else
- return 0;
-#endif
-}
-
-void mpgpu_class_exit(void)
-{
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
- class_unregister(&mpgpu_class);
-#endif
-}
-
+++ /dev/null
-/*
- * platform.c
- *
- * clock source setting and resource config
- *
- * Created on: Dec 4, 2013
- * Author: amlogic
- */
-
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/module.h> /* kernel module definitions */
-#include <linux/ioport.h> /* request_mem_region */
-#include <linux/slab.h>
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#endif
-#include <asm/io.h>
-#include <linux/mali/mali_utgard.h>
-#ifdef CONFIG_GPU_THERMAL
-#include <linux/gpu_cooling.h>
-#include <linux/gpucore_cooling.h>
-#ifdef CONFIG_DEVFREQ_THERMAL
-#include <linux/amlogic/aml_thermal_hw.h>
-#include <common/mali_ukk.h>
-#endif
-#endif
-#include <common/mali_kernel_common.h>
-#include <common/mali_osk_profiling.h>
-#include <common/mali_pmu.h>
-
-#include "mali_scaling.h"
-#include "mali_clock.h"
-#include "meson_main.h"
-#ifdef CONFIG_DEVFREQ_THERMAL
-#include "mali_executor.h"
-#endif
-
-/*
- * For Meson 8 M2.
- *
- */
-static void mali_plat_preheat(void);
-static mali_plat_info_t mali_plat_data = {
- .bst_gpu = 210, /* threshold for boosting gpu. */
- .bst_pp = 160, /* threshold for boosting PP. */
- .have_switch = 1,
- .limit_on = 1,
- .plat_preheat = mali_plat_preheat,
-};
-
-static void mali_plat_preheat(void)
-{
-#ifndef CONFIG_MALI_DVFS
- u32 pre_fs;
- u32 clk, pp;
-
- if (get_mali_schel_mode() != MALI_PP_FS_SCALING)
- return;
-
- get_mali_rt_clkpp(&clk, &pp);
- pre_fs = mali_plat_data.def_clock + 1;
- if (clk < pre_fs)
- clk = pre_fs;
- if (pp < mali_plat_data.sc_mpp)
- pp = mali_plat_data.sc_mpp;
- set_mali_rt_clkpp(clk, pp, 1);
-#endif
-}
-
-mali_plat_info_t* get_mali_plat_data(void) {
- return &mali_plat_data;
-}
-
-int get_mali_freq_level(int freq)
-{
- int i = 0, level = -1;
- int mali_freq_num;
-
- if (freq < 0)
- return level;
-
- mali_freq_num = mali_plat_data.dvfs_table_size - 1;
- if (freq < mali_plat_data.clk_sample[0])
- level = mali_freq_num-1;
- else if (freq >= mali_plat_data.clk_sample[mali_freq_num - 1])
- level = 0;
- else {
- for (i=0; i<mali_freq_num - 1 ;i++) {
- if (freq >= mali_plat_data.clk_sample[i] && freq < mali_plat_data.clk_sample[i + 1]) {
- level = i;
- level = mali_freq_num-level - 1;
- break;
- }
- }
- }
- return level;
-}
-
-unsigned int get_mali_max_level(void)
-{
- return mali_plat_data.dvfs_table_size - 1;
-}
-
-int get_gpu_max_clk_level(void)
-{
- return mali_plat_data.cfg_clock;
-}
-
-#ifdef CONFIG_GPU_THERMAL
-static void set_limit_mali_freq(u32 idx)
-{
- if (mali_plat_data.limit_on == 0)
- return;
- if (idx > mali_plat_data.turbo_clock || idx < mali_plat_data.scale_info.minclk)
- return;
- if (idx > mali_plat_data.maxclk_sysfs) {
- printk("idx > max freq\n");
- return;
- }
- mali_plat_data.scale_info.maxclk= idx;
- revise_mali_rt();
-}
-
-static u32 get_limit_mali_freq(void)
-{
- return mali_plat_data.scale_info.maxclk;
-}
-
-#ifdef CONFIG_DEVFREQ_THERMAL
-static u32 get_mali_utilization(void)
-{
- return (_mali_ukk_utilization_pp() * 100) / 256;
-}
-#endif
-#endif
-
-#ifdef CONFIG_GPU_THERMAL
-static u32 set_limit_pp_num(u32 num)
-{
- u32 ret = -1;
- if (mali_plat_data.limit_on == 0)
- goto quit;
- if (num > mali_plat_data.cfg_pp ||
- num < mali_plat_data.scale_info.minpp)
- goto quit;
-
- if (num > mali_plat_data.maxpp_sysfs) {
- printk("pp > sysfs set pp\n");
- goto quit;
- }
-
- mali_plat_data.scale_info.maxpp = num;
- revise_mali_rt();
- ret = 0;
-quit:
- return ret;
-}
-#ifdef CONFIG_DEVFREQ_THERMAL
-static u32 mali_get_online_pp(void)
-{
- unsigned int val;
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
-
- val = readl(pmali_plat->reg_base_aobus + 0xf0) & 0xff;
- if (val == 0x07) /* No pp is working */
- return 0;
-
- return mali_executor_get_num_cores_enabled();
-}
-#endif
-#endif
-
-void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data);
-int mali_meson_init_start(struct platform_device* ptr_plt_dev)
-{
- dev_set_drvdata(&ptr_plt_dev->dev, &mali_plat_data);
- mali_dt_info(ptr_plt_dev, &mali_plat_data);
- mali_clock_init_clk_tree(ptr_plt_dev);
- return 0;
-}
-
-int mali_meson_init_finish(struct platform_device* ptr_plt_dev)
-{
- if (mali_core_scaling_init(&mali_plat_data) < 0)
- return -1;
- return 0;
-}
-
-int mali_meson_uninit(struct platform_device* ptr_plt_dev)
-{
- mali_core_scaling_term();
- return 0;
-}
-
-static int mali_cri_light_suspend(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- mali_pm_statue = 1;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_suspend(device);
- }
- mali_pmu_power_down_all(pmu);
- return ret;
-}
-
-static int mali_cri_light_resume(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- mali_pmu_power_up_all(pmu);
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_resume(device);
- }
- mali_pm_statue = 0;
- return ret;
-}
-
-static int mali_cri_deep_suspend(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->suspend(device);
- }
- mali_pmu_power_down_all(pmu);
- return ret;
-}
-
-static int mali_cri_deep_resume(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- mali_pmu_power_up_all(pmu);
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->resume(device);
- }
- return ret;
-
-}
-
-int mali_light_suspend(struct device *device)
-{
- int ret = 0;
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- 0, 0, 0, 0, 0);
-#endif
-
- flush_scaling_job();
- /* clock scaling. Kasin..*/
- ret = mali_clock_critical(mali_cri_light_suspend, (size_t)device);
- disable_clock();
- return ret;
-}
-
-int mali_light_resume(struct device *device)
-{
- int ret = 0;
- enable_clock();
- ret = mali_clock_critical(mali_cri_light_resume, (size_t)device);
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- get_current_frequency(), 0, 0, 0, 0);
-#endif
- return ret;
-}
-
-int mali_deep_suspend(struct device *device)
-{
- int ret = 0;
-
- mali_pm_statue = 1;
- flush_scaling_job();
-
-
- /* clock scaling off. Kasin... */
- ret = mali_clock_critical(mali_cri_deep_suspend, (size_t)device);
- disable_clock();
- return ret;
-}
-
-int mali_deep_resume(struct device *device)
-{
- int ret = 0;
-
- /* clock scaling up. Kasin.. */
- enable_clock();
- ret = mali_clock_critical(mali_cri_deep_resume, (size_t)device);
- mali_pm_statue = 0;
- return ret;
-
-}
-
-void mali_post_init(void)
-{
-#ifdef CONFIG_GPU_THERMAL
- int err;
- struct gpufreq_cooling_device *gcdev = NULL;
- struct gpucore_cooling_device *gccdev = NULL;
-
- gcdev = gpufreq_cooling_alloc();
- register_gpu_freq_info(get_current_frequency);
- if (IS_ERR(gcdev))
- printk("malloc gpu cooling buffer error!!\n");
- else if (!gcdev)
- printk("system does not enable thermal driver\n");
- else {
- gcdev->get_gpu_freq_level = get_mali_freq_level;
- gcdev->get_gpu_max_level = get_mali_max_level;
- gcdev->set_gpu_freq_idx = set_limit_mali_freq;
- gcdev->get_gpu_current_max_level = get_limit_mali_freq;
-#ifdef CONFIG_DEVFREQ_THERMAL
- gcdev->get_gpu_freq = get_mali_freq;
- gcdev->get_gpu_loading = get_mali_utilization;
- gcdev->get_online_pp = mali_get_online_pp;
-#endif
- err = gpufreq_cooling_register(gcdev);
-#ifdef CONFIG_DEVFREQ_THERMAL
- aml_thermal_min_update(gcdev->cool_dev);
-#endif
- if (err < 0)
- printk("register GPU cooling error\n");
- printk("gpu cooling register okay with err=%d\n",err);
- }
-
- gccdev = gpucore_cooling_alloc();
- if (IS_ERR(gccdev))
- printk("malloc gpu core cooling buffer error!!\n");
- else if (!gccdev)
- printk("system does not enable thermal driver\n");
- else {
- gccdev->max_gpu_core_num=mali_plat_data.cfg_pp;
- gccdev->set_max_pp_num=set_limit_pp_num;
- err = (int)gpucore_cooling_register(gccdev);
-#ifdef CONFIG_DEVFREQ_THERMAL
- aml_thermal_min_update(gccdev->cool_dev);
-#endif
- if (err < 0)
- printk("register GPU cooling error\n");
- printk("gpu core cooling register okay with err=%d\n",err);
- }
-#endif
-}
+++ /dev/null
-/*
- * Copyright (C) 2013 ARM Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
- *
- * A copy of the licence is included with the program, and can also be obtained from Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-/**
- * @file arm_core_scaling.c
- * Example core scaling policy.
- */
-
-#include <linux/version.h>
-#include <linux/module.h>
-#include <linux/workqueue.h>
-#include <linux/mali/mali_utgard.h>
-#include <mali_kernel_common.h>
-#include <mali_osk_profiling.h>
-
-#if AMLOGIC_GPU_USE_GPPLL
-#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 16)
-#include <linux/amlogic/amports/gp_pll.h>
-#else
-#include <linux/amlogic/media/clk/gp_pll.h>
-#endif
-#endif
-#define LOG_MALI_SCALING 1
-#include "meson_main2.h"
-#include "mali_clock.h"
-
-static int currentStep;
-#ifndef CONFIG_MALI_DVFS
-static int num_cores_enabled;
-static int lastStep;
-static struct work_struct wq_work;
-static mali_plat_info_t* pmali_plat = NULL;
-#endif
-static int scaling_mode = MALI_PP_FS_SCALING;
-//static int scaling_mode = MALI_SCALING_DISABLE;
-//static int scaling_mode = MALI_PP_SCALING;
-
-#if AMLOGIC_GPU_USE_GPPLL
-static struct gp_pll_user_handle_s *gp_pll_user_gpu;
-static int is_gp_pll_get;
-static int is_gp_pll_put;
-#endif
-
-static unsigned scaling_dbg_level = 0;
-module_param(scaling_dbg_level, uint, 0644);
-MODULE_PARM_DESC(scaling_dbg_level , "scaling debug level");
-
-#define scalingdbg(level, fmt, arg...) \
- do { \
- if (scaling_dbg_level >= (level)) \
- printk(fmt , ## arg); \
- } while (0)
-
-#ifndef CONFIG_MALI_DVFS
-static inline void mali_clk_exected(void)
-{
- mali_dvfs_threshold_table * pdvfs = pmali_plat->dvfs_table;
- uint32_t execStep = currentStep;
-#if AMLOGIC_GPU_USE_GPPLL
- mali_dvfs_threshold_table *dvfs_tbl = &pmali_plat->dvfs_table[currentStep];
-#endif
-
- //if (pdvfs[currentStep].freq_index == pdvfs[lastStep].freq_index) return;
- if ((pdvfs[execStep].freq_index == pdvfs[lastStep].freq_index) ||
- (pdvfs[execStep].clk_freq == pdvfs[lastStep].clk_freq)){
- return;
- }
-
-#if AMLOGIC_GPU_USE_GPPLL
- if (0 == strcmp(dvfs_tbl->clk_parent, "gp0_pll")) {
- gp_pll_request(gp_pll_user_gpu);
- if (!is_gp_pll_get) {
- //printk("not get pll\n");
- execStep = currentStep - 1;
- }
- } else {
- //not get the gp pll, do need put
- is_gp_pll_get = 0;
- is_gp_pll_put = 0;
- gp_pll_release(gp_pll_user_gpu);
- }
-#endif
-
- //mali_dev_pause();
- mali_clock_set(pdvfs[execStep].freq_index);
- //mali_dev_resume();
- lastStep = execStep;
-#if AMLOGIC_GPU_USE_GPPLL
- if (is_gp_pll_put) {
- //printk("release gp0 pll\n");
- gp_pll_release(gp_pll_user_gpu);
- gp_pll_request(gp_pll_user_gpu);
- is_gp_pll_get = 0;
- is_gp_pll_put = 0;
- }
-#endif
-
-}
-#if AMLOGIC_GPU_USE_GPPLL
-static int gp_pll_user_cb_gpu(struct gp_pll_user_handle_s *user,
- int event)
-{
- if (event == GP_PLL_USER_EVENT_GRANT) {
- //printk("granted\n");
- is_gp_pll_get = 1;
- is_gp_pll_put = 0;
- schedule_work(&wq_work);
- } else if (event == GP_PLL_USER_EVENT_YIELD) {
- //printk("ask for yield\n");
- is_gp_pll_get = 0;
- is_gp_pll_put = 1;
- schedule_work(&wq_work);
- }
-
- return 0;
-}
-#endif
-
-static void do_scaling(struct work_struct *work)
-{
- mali_dvfs_threshold_table * pdvfs = pmali_plat->dvfs_table;
- int err = mali_perf_set_num_pp_cores(num_cores_enabled);
- scalingdbg(1, "set pp cores to %d\n", num_cores_enabled);
- MALI_DEBUG_ASSERT(0 == err);
- MALI_IGNORE(err);
- scalingdbg(1, "pdvfs[%d].freq_index=%d, pdvfs[%d].freq_index=%d\n",
- currentStep, pdvfs[currentStep].freq_index,
- lastStep, pdvfs[lastStep].freq_index);
- mali_clk_exected();
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- get_current_frequency(),
- 0, 0, 0, 0);
-#endif
-}
-#endif
-
-u32 revise_set_clk(u32 val, u32 flush)
-{
- u32 ret = 0;
-#ifndef CONFIG_MALI_DVFS
- mali_scale_info_t* pinfo;
-
- pinfo = &pmali_plat->scale_info;
-
- if (val < pinfo->minclk)
- val = pinfo->minclk;
- else if (val > pinfo->maxclk)
- val = pinfo->maxclk;
-
- if (val != currentStep) {
- currentStep = val;
- if (flush)
- schedule_work(&wq_work);
- else
- ret = 1;
- }
-#endif
- return ret;
-}
-
-void get_mali_rt_clkpp(u32* clk, u32* pp)
-{
-#ifndef CONFIG_MALI_DVFS
- *clk = currentStep;
- *pp = num_cores_enabled;
-#endif
-}
-
-u32 set_mali_rt_clkpp(u32 clk, u32 pp, u32 flush)
-{
- u32 ret = 0;
-#ifndef CONFIG_MALI_DVFS
- mali_scale_info_t* pinfo;
- u32 flush_work = 0;
-
- pinfo = &pmali_plat->scale_info;
- if (clk < pinfo->minclk)
- clk = pinfo->minclk;
- else if (clk > pinfo->maxclk)
- clk = pinfo->maxclk;
-
- if (clk != currentStep) {
- currentStep = clk;
- if (flush)
- flush_work++;
- else
- ret = 1;
- }
- if (pp < pinfo->minpp)
- pp = pinfo->minpp;
- else if (pp > pinfo->maxpp)
- pp = pinfo->maxpp;
-
- if (pp != num_cores_enabled) {
- num_cores_enabled = pp;
- if (flush)
- flush_work++;
- else
- ret = 1;
- }
-
- if (flush_work)
- schedule_work(&wq_work);
-#endif
- return ret;
-}
-
-void revise_mali_rt(void)
-{
-#ifndef CONFIG_MALI_DVFS
- set_mali_rt_clkpp(currentStep, num_cores_enabled, 1);
-#endif
-}
-
-void flush_scaling_job(void)
-{
-#ifndef CONFIG_MALI_DVFS
- cancel_work_sync(&wq_work);
-#endif
-}
-
-#ifndef CONFIG_MALI_DVFS
-static u32 enable_one_core(void)
-{
- scalingdbg(2, "meson: one more pp, curent has %d pp cores\n", num_cores_enabled + 1);
- return set_mali_rt_clkpp(currentStep, num_cores_enabled + 1, 0);
-}
-
-static u32 disable_one_core(void)
-{
- scalingdbg(2, "meson: disable one pp, current has %d pp cores\n", num_cores_enabled - 1);
- return set_mali_rt_clkpp(currentStep, num_cores_enabled - 1, 0);
-}
-
-static u32 enable_max_num_cores(void)
-{
- return set_mali_rt_clkpp(currentStep, pmali_plat->scale_info.maxpp, 0);
-}
-
-static u32 enable_pp_cores(u32 val)
-{
- scalingdbg(2, "meson: enable %d pp cores\n", val);
- return set_mali_rt_clkpp(currentStep, val, 0);
-}
-#endif
-
-int mali_core_scaling_init(mali_plat_info_t *mali_plat)
-{
-#ifndef CONFIG_MALI_DVFS
- if (mali_plat == NULL) {
- scalingdbg(2, " Mali platform data is NULL!!!\n");
- return -1;
- }
-
- pmali_plat = mali_plat;
- num_cores_enabled = pmali_plat->sc_mpp;
-#if AMLOGIC_GPU_USE_GPPLL
- gp_pll_user_gpu = gp_pll_user_register("gpu", 1,
- gp_pll_user_cb_gpu);
- //not get the gp pll, do need put
- is_gp_pll_get = 0;
- is_gp_pll_put = 0;
- if (gp_pll_user_gpu == NULL) printk("register gp pll user for gpu failed\n");
-#endif
-
- currentStep = pmali_plat->def_clock;
- lastStep = currentStep;
- INIT_WORK(&wq_work, do_scaling);
-#endif
- return 0;
- /* NOTE: Mali is not fully initialized at this point. */
-}
-
-void mali_core_scaling_term(void)
-{
-#ifndef CONFIG_MALI_DVFS
- flush_scheduled_work();
-#if AMLOGIC_GPU_USE_GPPLL
- gp_pll_user_unregister(gp_pll_user_gpu);
-#endif
-#endif
-}
-
-#ifndef CONFIG_MALI_DVFS
-static u32 mali_threshold [] = {
- 102, /* 40% */
- 128, /* 50% */
- 230, /* 90% */
-};
-#endif
-
-void mali_pp_scaling_update(struct mali_gpu_utilization_data *data)
-{
-#ifndef CONFIG_MALI_DVFS
- int ret = 0;
-
- if (mali_threshold[2] < data->utilization_pp)
- ret = enable_max_num_cores();
- else if (mali_threshold[1]< data->utilization_pp)
- ret = enable_one_core();
- else if (0 < data->utilization_pp)
- ret = disable_one_core();
- if (ret == 1)
- schedule_work(&wq_work);
-#endif
-}
-
-#if LOG_MALI_SCALING
-void trace_utilization(struct mali_gpu_utilization_data *data, u32 current_idx, u32 next,
- u32 current_pp, u32 next_pp)
-{
- char direction;
- if (next > current_idx)
- direction = '>';
- else if ((current_idx > pmali_plat->scale_info.minpp) && (next < current_idx))
- direction = '<';
- else
- direction = '~';
-
- scalingdbg(2, "[SCALING]%c (%3d-->%3d)@%3d{%3d - %3d}. pp:(%d-->%d)\n",
- direction,
- get_mali_freq(current_idx),
- get_mali_freq(next),
- data->utilization_gpu,
- pmali_plat->dvfs_table[current_idx].downthreshold,
- pmali_plat->dvfs_table[current_idx].upthreshold,
- current_pp, next_pp);
-}
-#endif
-
-#ifndef CONFIG_MALI_DVFS
-static int mali_stay_count = 0;
-static void mali_decide_next_status(struct mali_gpu_utilization_data *data, int* next_fs_idx,
- int* pp_change_flag)
-{
- u32 utilization, mali_up_limit, decided_fs_idx;
- u32 ld_left, ld_right;
- u32 ld_up, ld_down;
- u32 change_mode;
-
- *pp_change_flag = 0;
- change_mode = 0;
- utilization = data->utilization_gpu;
-
- scalingdbg(5, "line(%d), scaling_mode=%d, MALI_TURBO_MODE=%d, turbo=%d, maxclk=%d\n",
- __LINE__, scaling_mode, MALI_TURBO_MODE,
- pmali_plat->turbo_clock, pmali_plat->scale_info.maxclk);
-
- mali_up_limit = (scaling_mode == MALI_TURBO_MODE) ?
- pmali_plat->turbo_clock : pmali_plat->scale_info.maxclk;
- decided_fs_idx = currentStep;
-
- ld_up = pmali_plat->dvfs_table[currentStep].upthreshold;
- ld_down = pmali_plat->dvfs_table[currentStep].downthreshold;
-
- scalingdbg(2, "utilization=%d, ld_up=%d\n ", utilization, ld_up);
- if (utilization >= ld_up) { /* go up */
-
- scalingdbg(2, "currentStep=%d, mali_up_limit=%d\n ", currentStep, mali_up_limit);
- if (currentStep < mali_up_limit) {
- change_mode = 1;
- if ((currentStep < pmali_plat->def_clock) && (utilization > pmali_plat->bst_gpu))
- decided_fs_idx = pmali_plat->def_clock;
- else
- decided_fs_idx++;
- }
- if ((data->utilization_pp >= ld_up) &&
- (num_cores_enabled < pmali_plat->scale_info.maxpp)) {
- if ((num_cores_enabled < pmali_plat->sc_mpp) && (data->utilization_pp >= pmali_plat->bst_pp)) {
- *pp_change_flag = 1;
- change_mode = 1;
- } else if (change_mode == 0) {
- *pp_change_flag = 2;
- change_mode = 1;
- }
- }
-#if LOG_MALI_SCALING
- scalingdbg(2, "[nexting..] [LD:%d]-> FS[CRNT:%d LMT:%d NEXT:%d] PP[NUM:%d LMT:%d MD:%d][F:%d]\n",
- data->utilization_pp, currentStep, mali_up_limit, decided_fs_idx,
- num_cores_enabled, pmali_plat->scale_info.maxpp, *pp_change_flag, change_mode);
-#endif
- } else if (utilization <= ld_down) { /* go down */
- if (mali_stay_count > 0) {
- *next_fs_idx = decided_fs_idx;
- mali_stay_count--;
- return;
- }
-
- if (num_cores_enabled > pmali_plat->sc_mpp) {
- change_mode = 1;
- if (data->utilization_pp <= ld_down) {
- ld_left = data->utilization_pp * num_cores_enabled;
- ld_right = (pmali_plat->dvfs_table[currentStep].upthreshold) *
- (num_cores_enabled - 1);
- if (ld_left < ld_right) {
- change_mode = 2;
- }
- }
- } else if (currentStep > pmali_plat->scale_info.minclk) {
- change_mode = 1;
- } else if (num_cores_enabled > 1) { /* decrease PPS */
- if (data->utilization_pp <= ld_down) {
- ld_left = data->utilization_pp * num_cores_enabled;
- ld_right = (pmali_plat->dvfs_table[currentStep].upthreshold) *
- (num_cores_enabled - 1);
- scalingdbg(2, "ld_left=%d, ld_right=%d\n", ld_left, ld_right);
- if (ld_left < ld_right) {
- change_mode = 2;
- }
- }
- }
-
- if (change_mode == 1) {
- decided_fs_idx--;
- } else if (change_mode == 2) { /* decrease PPS */
- *pp_change_flag = -1;
- }
- }
-
- if (decided_fs_idx < 0 ) {
- printk("gpu debug, next index below 0\n");
- decided_fs_idx = 0;
- }
- if (decided_fs_idx > pmali_plat->scale_info.maxclk) {
- decided_fs_idx = pmali_plat->scale_info.maxclk;
- printk("gpu debug, next index above max, set to %d\n", decided_fs_idx);
- }
-
- if (change_mode)
- mali_stay_count = pmali_plat->dvfs_table[decided_fs_idx].keep_count;
- *next_fs_idx = decided_fs_idx;
-}
-#endif
-
-void mali_pp_fs_scaling_update(struct mali_gpu_utilization_data *data)
-{
-#ifndef CONFIG_MALI_DVFS
- int ret = 0;
- int pp_change_flag = 0;
- u32 next_idx = 0;
-
-#if LOG_MALI_SCALING
- u32 last_pp = num_cores_enabled;
-#endif
- mali_decide_next_status(data, &next_idx, &pp_change_flag);
-
- if (pp_change_flag == 1)
- ret = enable_pp_cores(pmali_plat->sc_mpp);
- else if (pp_change_flag == 2)
- ret = enable_one_core();
- else if (pp_change_flag == -1) {
- ret = disable_one_core();
- }
-
-#if LOG_MALI_SCALING
- if (pp_change_flag || (next_idx != currentStep))
- trace_utilization(data, currentStep, next_idx, last_pp, num_cores_enabled);
-#endif
-
- if (next_idx != currentStep) {
- ret = 1;
- currentStep = next_idx;
- }
-
- if (ret == 1)
- schedule_work(&wq_work);
-#ifdef CONFIG_MALI400_PROFILING
- else
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- get_current_frequency(),
- 0, 0, 0, 0);
-#endif
-#endif
-}
-
-u32 get_mali_schel_mode(void)
-{
- return scaling_mode;
-}
-
-void set_mali_schel_mode(u32 mode)
-{
-#ifndef CONFIG_MALI_DVFS
- MALI_DEBUG_ASSERT(mode < MALI_SCALING_MODE_MAX);
- if (mode >= MALI_SCALING_MODE_MAX)
- return;
- scaling_mode = mode;
-
- //disable thermal in turbo mode
- if (scaling_mode == MALI_TURBO_MODE) {
- pmali_plat->limit_on = 0;
- } else {
- pmali_plat->limit_on = 1;
- }
- /* set default performance range. */
- pmali_plat->scale_info.minclk = pmali_plat->cfg_min_clock;
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- pmali_plat->scale_info.minpp = pmali_plat->cfg_min_pp;
- pmali_plat->scale_info.maxpp = pmali_plat->cfg_pp;
-
- /* set current status and tune max freq */
- if (scaling_mode == MALI_PP_FS_SCALING) {
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- enable_pp_cores(pmali_plat->sc_mpp);
- } else if (scaling_mode == MALI_SCALING_DISABLE) {
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- enable_max_num_cores();
- } else if (scaling_mode == MALI_TURBO_MODE) {
- pmali_plat->scale_info.maxclk = pmali_plat->turbo_clock;
- enable_max_num_cores();
- }
- currentStep = pmali_plat->scale_info.maxclk;
- schedule_work(&wq_work);
-#endif
-}
-
-u32 get_current_frequency(void)
-{
- return get_mali_freq(currentStep);
-}
-
-void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data)
-{
-#ifndef CONFIG_MALI_DVFS
- if (mali_pm_statue)
- return;
-
- switch (scaling_mode) {
- case MALI_PP_FS_SCALING:
- mali_pp_fs_scaling_update(data);
- break;
- case MALI_PP_SCALING:
- mali_pp_scaling_update(data);
- break;
- default:
- break;
- }
-#endif
-}
-static u32 clk_cntl_save = 0;
-void mali_dev_freeze(void)
-{
- clk_cntl_save = mplt_read(HHI_MALI_CLK_CNTL);
-}
-
-void mali_dev_restore(void)
-{
-
- mplt_write(HHI_MALI_CLK_CNTL, clk_cntl_save);
- if (pmali_plat && pmali_plat->pdev) {
- mali_clock_init_clk_tree(pmali_plat->pdev);
- } else {
- printk("error: init clock failed, pmali_plat=%p, pmali_plat->pdev=%p\n",
- pmali_plat, pmali_plat == NULL ? NULL: pmali_plat->pdev);
- }
-}
-
-int mali_meson_get_gpu_data(struct mali_gpu_device_data *mgpu_data)
-{
- mgpu_data->get_clock_info = NULL;
- mgpu_data->get_freq = NULL;
- mgpu_data->set_freq = NULL;
- mgpu_data->utilization_callback = mali_gpu_utilization_callback;
- return 0;
-}
+++ /dev/null
-/*
- * AMLOGIC Mali fix driver.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the named License,
- * or any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
- *
- * Author: Tim Yao <timyao@amlogic.com>
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/timer.h>
-#include <asm/io.h>
-#include <linux/ioport.h>
-#include <linux/dma-mapping.h>
-
-#include <linux/module.h>
-
-#include <mach/am_regs.h>
-#include <mach/clock.h>
-#include <linux/io.h>
-#include <mach/io.h>
-#include <plat/io.h>
-#include <asm/io.h>
-
-#include "mali_kernel_common.h"
-#include "mali_osk.h"
-#include "mali_platform.h"
-#include "mali_fix.h"
-
-#define MALI_MM1_REG_ADDR 0xd0064000
-#define MALI_MMU_REGISTER_INT_STATUS 0x0008
-#define MALI_MM2_REG_ADDR 0xd0065000
-#define MALI_MMU_REGISTER_INT_STATUS 0x0008
-#define MALI_MM_REG_SIZE 0x1000
-
-#define READ_MALI_MMU1_REG(r) (ioread32(((u8*)mali_mm1_regs) + r))
-#define READ_MALI_MMU2_REG(r) (ioread32(((u8*)mali_mm2_regs) + r))
-
-extern int mali_PP0_int_cnt(void);
-extern int mali_PP1_int_cnt(void);
-
-#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
-static ulong * mali_mm1_regs = NULL;
-static ulong * mali_mm2_regs = NULL;
-static struct timer_list timer;
-
-static u32 mali_pp1_int_count = 0;
-static u32 mali_pp2_int_count = 0;
-static u32 mali_pp1_mmu_int_count = 0;
-static u32 mali_pp2_mmu_int_count = 0;
-static u32 mali_mmu_int_process_state[2];
-
-static void timer_callback(ulong data)
-{
- unsigned long mali_flags;
-
- mali_pp1_int_count = mali_PP0_int_cnt();
- mali_pp2_int_count = mali_PP1_int_cnt();
-
- /* lock mali_clock_gating when access Mali registers */
- mali_flags = mali_clock_gating_lock();
-
- if (readl((u32 *)P_HHI_MALI_CLK_CNTL) & 0x100) {
- /* polling for PP1 MMU interrupt */
- if (mali_mmu_int_process_state[0] == MMU_INT_NONE) {
- if (READ_MALI_MMU1_REG(MALI_MMU_REGISTER_INT_STATUS) != 0) {
- mali_pp1_mmu_int_count++;
- MALI_DEBUG_PRINT(3, ("Mali MMU: core0 page fault emit \n"));
- mali_mmu_int_process_state[0] = MMU_INT_HIT;
- __raw_writel(1, (volatile void *)P_ISA_TIMERC);
- }
- }
-
- /* polling for PP2 MMU interrupt */
- if (mali_mmu_int_process_state[1] == MMU_INT_NONE) {
- if (READ_MALI_MMU2_REG(MALI_MMU_REGISTER_INT_STATUS) != 0) {
- mali_pp2_mmu_int_count++;
- MALI_DEBUG_PRINT(3, ("Mali MMU: core1 page fault emit \n"));
- mali_mmu_int_process_state[1] = MMU_INT_HIT;
- __raw_writel(1, (volatile void *)P_ISA_TIMERC);
- }
- }
- }
-
- mali_clock_gating_unlock(mali_flags);
-
- timer.expires = jiffies + HZ/100;
-
- add_timer(&timer);
-}
-
-void malifix_set_mmu_int_process_state(int index, int state)
-{
- if (index < 2)
- mali_mmu_int_process_state[index] = state;
-}
-
-int malifix_get_mmu_int_process_state(int index)
-{
- if (index < 2)
- return mali_mmu_int_process_state[index];
- return 0;
-}
-#endif
-
-void malifix_init(void)
-{
-#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
- if (!mali_meson_is_revb())
- return;
-
- if ((mali_mm1_regs) && (mali_mm2_regs)) return;
- mali_mmu_int_process_state[0] = 0;
- mali_mmu_int_process_state[1] = 0;
-
- /* set up Timer C as a 1uS one-shot timer */
- aml_clr_reg32_mask(P_ISA_TIMER_MUX, (1<<18)|(1<<14)|(3<<4));
- aml_set_reg32_mask(P_ISA_TIMER_MUX, (1<<18)|(0<<14)|(0<<4));
-
- setup_timer(&timer, timer_callback, 0);
-
- mali_mm1_regs = (ulong *)ioremap_nocache(MALI_MM1_REG_ADDR, MALI_MM_REG_SIZE);
- if (mali_mm1_regs)
- printk("Mali pp1 MMU register mapped at %p...\n", mali_mm1_regs);
-
- mali_mm2_regs = (ulong *)ioremap_nocache(MALI_MM2_REG_ADDR, MALI_MM_REG_SIZE);
- if (mali_mm2_regs)
- printk("Mali pp2 MMU register mapped at %p...\n", mali_mm2_regs);
-
- if ((mali_mm1_regs != NULL) && (mali_mm2_regs != NULL))
- mod_timer(&timer, jiffies + HZ/100);
-#endif
-}
-
-void malifix_exit(void)
-{
-#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
- if (!mali_meson_is_revb())
- return;
-
- del_timer(&timer);
-
- if (mali_mm1_regs != NULL)
- iounmap(mali_mm1_regs);
- mali_mm1_regs = NULL;
-
- if (mali_mm2_regs != NULL)
- iounmap(mali_mm2_regs);
- mali_mm2_regs = NULL;
-
-#endif
- return;
-}
-
-#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
-module_param(mali_pp1_int_count, uint, 0664);
-MODULE_PARM_DESC(mali_pp1_int_count, "Mali PP1 interrupt count\n");
-
-module_param(mali_pp2_int_count, uint, 0664);
-MODULE_PARM_DESC(mali_pp2_int_count, "Mali PP1 interrupt count\n");
-
-module_param(mali_pp1_mmu_int_count, uint, 0664);
-MODULE_PARM_DESC(mali_pp1_mmu_int_count, "Mali PP1 mmu interrupt count\n");
-
-module_param(mali_pp2_mmu_int_count, uint, 0664);
-MODULE_PARM_DESC(mali_pp2_mmu_int_count, "Mali PP2 mmu interrupt count\n");
-#endif
-
-MODULE_DESCRIPTION("AMLOGIC mali fix driver");
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Tim Yao <timyao@amlogic.com>");
+++ /dev/null
-#ifndef MALI_FIX_H
-#define MALI_FIX_H
-
-#define MMU_INT_NONE 0
-#define MMU_INT_HIT 1
-#define MMU_INT_TOP 2
-#define MMU_INT_BOT 3
-
-extern void malifix_init(void);
-extern void malifix_exit(void);
-extern void malifix_set_mmu_int_process_state(int, int);
-extern int malifix_get_mmu_int_process_state(int);
-extern int mali_meson_is_revb(void);
-#endif /* MALI_FIX_H */
+++ /dev/null
-/*
- * This confidential and proprietary software may be used only as
- * authorised by a licensing agreement from AMLOGIC, INC.
- * (C) COPYRIGHT 2011 AMLOGIC, INC.
- * ALL RIGHTS RESERVED
- * The entire notice above must be reproduced on all authorised
- * copies and copies may only be made to the extent permitted
- * by a licensing agreement from AMLOGIC, INC.
- */
-
-/**
- * @file mali_platform.c
- * Platform specific Mali driver functions for meson platform
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/dma-mapping.h>
-#include <linux/spinlock.h>
-#include <linux/spinlock_types.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <mach/am_regs.h>
-#include <mach/clock.h>
-
-#include "mali_kernel_common.h"
-#include "mali_osk.h"
-#include "mali_platform.h"
-#include "mali_poweron_reg.h"
-#include "mali_fix.h"
-#include "mali_platform.h"
-
-static int last_power_mode = -1;
-static int mali_init_flag = 0;
-static const u32 poweron_data[] =
-{
-/* commands */
-/* 000 */ 0x00000040, 0x20400000, 0x00000300, 0x30040000,
-/* 010 */ 0x00000400, 0x400a0000, 0x0f000033, 0x10000042,
-/* 020 */ 0x00300c00, 0x10000040, 0x4c000001, 0x00000000,
-/* 030 */ 0x00000000, 0x60000000, 0x00000000, 0x00000000,
-/* 040 */ 0x00004000, 0x00002000, 0x00000210, 0x0000203f,
-/* 050 */ 0x00000220, 0x0000203f, 0x00000230, 0x0000203f,
-/* 060 */ 0x00000240, 0x0000203f, 0x00000250, 0x0000203f,
-/* 070 */ 0x00000260, 0x0000203f, 0x00000270, 0x0000203f,
-/* 080 */ 0x00000280, 0x0000203f, 0x00000290, 0x0000203f,
-/* 090 */ 0x000002a0, 0x0000203f, 0x000002b0, 0x0000203f,
-/* 0a0 */ 0x000002c0, 0x0000203f, 0x000002d0, 0x0000203f,
-/* 0b0 */ 0x000002e0, 0x0000203f, 0x000002f0, 0x0000203f,
-/* 0c0 */ 0x00002000, 0x00002000, 0x00002010, 0x0000203f,
-/* 0d0 */ 0x00002020, 0x0000203f, 0x00002030, 0x0000203f,
-/* 0e0 */ 0x00002040, 0x0000203f, 0x00002050, 0x0000203f,
-/* 0f0 */ 0x00002060, 0x0000203f, 0x00002070, 0x0000203f,
-/* 100 */ 0x00002080, 0x0000203f, 0x00002090, 0x0000203f,
-/* 110 */ 0x000020a0, 0x0000203f, 0x000020b0, 0x0000203f,
-/* 120 */ 0x000020c0, 0x0000203f, 0x000020d0, 0x0000203f,
-/* 130 */ 0x000020e0, 0x0000203f, 0x000020f0, 0x0000203f,
-/* 140 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 150 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 160 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 170 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 180 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 190 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 1a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 1b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 1c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 1d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 1e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 1f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 200 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 210 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 220 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 230 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 240 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 250 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 260 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 270 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 280 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 290 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 2a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 2b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 2c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 2d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 2e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 2f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* const */
-/* 300 */ 0x3f2a6400, 0xbf317600, 0x3e8d8e00, 0x00000000,
-/* 310 */ 0x3f2f7000, 0x3f36e200, 0x3e10c500, 0x00000000,
-/* 320 */ 0xbe974e00, 0x3dc35300, 0x3f735800, 0x00000000,
-/* 330 */ 0x00000000, 0x00000000, 0x00000000, 0x3f800000,
-/* 340 */ 0x42b00000, 0x42dc0000, 0x3f800000, 0x3f800000,
-/* 350 */ 0x42b00000, 0x42dc0000, 0x00000000, 0x00000000,
-/* 360 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 370 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 380 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 390 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 3a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 3b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 3c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 3d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 3e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 3f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* inst */
-/* 400 */ 0xad4ad6b5, 0x438002b5, 0x0007ffe0, 0x00001e00,
-/* 410 */ 0xad4ad694, 0x038002b5, 0x0087ffe0, 0x00005030,
-/* 420 */ 0xad4bda56, 0x038002b5, 0x0007ffe0, 0x00001c10,
-/* 430 */ 0xad4ad6b5, 0x038002b5, 0x4007fee0, 0x00001c00
-};
-
-static struct clk *mali_clk = NULL;
-
-#if MESON_CPU_TYPE <= MESON_CPU_TYPE_MESON6
-
-#define OFFSET_MMU_DTE 0
-#define OFFSET_MMU_PTE 4096
-#define OFFSET_MMU_VIRTUAL_ZERO 8192
-
-#define INT_MALI_GP_BITS (1<<16)
-#define INT_MALI_PP_BITS (1<<18)
-#define INT_MALI_PP_MMU_BITS (1<<19)
-#define INT_ALL (0xffffffff)
-
-#define INT_MALI_PP_MMU_PAGE_FAULT (1<<0)
-
-#define MMU_FLAG_DTE_PRESENT 0x01
-#define MMU_FLAG_PTE_PAGE_PRESENT 0x01
-#define MMU_FLAG_PTE_RD_PERMISSION 0x02
-#define MMU_FLAG_PTE_WR_PERMISSION 0x04
-
-//static int mali_revb_flag = -1;
-static DEFINE_SPINLOCK(lock);
-extern int mali_revb_flag;
-int mali_meson_is_revb(void)
-{
- printk("mail version=%d\n",mali_revb_flag);
- if (mali_revb_flag == -1)
- mali_revb_flag = 1;
- else if (mali_revb_flag == 0)
- panic("rev-a! you should neet earlier version of mali_driver.!\n");
-
- return mali_revb_flag;
-}
-
-static void mali_meson_poweron(int first_poweron)
-{
- unsigned long flags;
- u32 p, p_aligned;
- dma_addr_t p_phy;
- int i;
- unsigned int_mask;
-
- if(!first_poweron) {
- if ((last_power_mode != -1) && (last_power_mode != MALI_POWER_MODE_DEEP_SLEEP)) {
- MALI_DEBUG_PRINT(3, ("Maybe your system not deep sleep now.......\n"));
- //printk("Maybe your system not deep sleep now.......\n");
- return;
- }
- }
-
- MALI_DEBUG_PRINT(2, ("mali_meson_poweron: Mali APB bus accessing\n"));
- if (READ_MALI_REG(MALI_PP_PP_VERSION) != MALI_PP_PP_VERSION_MAGIC) {
- MALI_DEBUG_PRINT(3, ("mali_meson_poweron: Mali APB bus access failed\n"));
- //printk("mali_meson_poweron: Mali APB bus access failed.");
- return;
- }
- MALI_DEBUG_PRINT(2, ("..........accessing done.\n"));
- if (READ_MALI_REG(MALI_MMU_DTE_ADDR) != 0) {
- MALI_DEBUG_PRINT(3, ("mali_meson_poweron: Mali is not really powered off\n"));
- //printk("mali_meson_poweron: Mali is not really powered off.");
- return;
- }
-
- p = (u32)kcalloc(4096 * 4, 1, GFP_KERNEL);
- if (!p) {
- printk("mali_meson_poweron: NOMEM in meson_poweron\n");
- return;
- }
-
- p_aligned = __ALIGN_MASK(p, 4096);
-
- /* DTE */
- *(u32 *)(p_aligned) = (virt_to_phys((void *)p_aligned) + OFFSET_MMU_PTE) | MMU_FLAG_DTE_PRESENT;
- /* PTE */
- for (i=0; i<1024; i++) {
- *(u32 *)(p_aligned + OFFSET_MMU_PTE + i*4) =
- (virt_to_phys((void *)p_aligned) + OFFSET_MMU_VIRTUAL_ZERO + 4096 * i) |
- MMU_FLAG_PTE_PAGE_PRESENT |
- MMU_FLAG_PTE_RD_PERMISSION;
- }
-
- /* command & data */
- memcpy((void *)(p_aligned + OFFSET_MMU_VIRTUAL_ZERO), poweron_data, 4096);
-
- p_phy = dma_map_single(NULL, (void *)p_aligned, 4096 * 3, DMA_TO_DEVICE);
-
- /* Set up Mali GP MMU */
- WRITE_MALI_REG(MALI_MMU_DTE_ADDR, p_phy);
- WRITE_MALI_REG(MALI_MMU_CMD, 0);
-
- if ((READ_MALI_REG(MALI_MMU_STATUS) & 1) != 1)
- printk("mali_meson_poweron: MMU enabling failed.\n");
-
- /* Set up Mali command registers */
- WRITE_MALI_REG(MALI_APB_GP_VSCL_START, 0);
- WRITE_MALI_REG(MALI_APB_GP_VSCL_END, 0x38);
-
- spin_lock_irqsave(&lock, flags);
-
- int_mask = READ_MALI_REG(MALI_APB_GP_INT_MASK);
- WRITE_MALI_REG(MALI_APB_GP_INT_CLEAR, 0x707bff);
- WRITE_MALI_REG(MALI_APB_GP_INT_MASK, 0);
-
- /* Start GP */
- WRITE_MALI_REG(MALI_APB_GP_CMD, 1);
-
- for (i = 0; i<100; i++)
- udelay(500);
-
- /* check Mali GP interrupt */
- if (READ_MALI_REG(MALI_APB_GP_INT_RAWSTAT) & 0x707bff)
- printk("mali_meson_poweron: Interrupt received.\n");
- else
- printk("mali_meson_poweron: No interrupt received.\n");
-
- /* force reset GP */
- WRITE_MALI_REG(MALI_APB_GP_CMD, 1 << 5);
-
- /* stop MMU paging and reset */
- WRITE_MALI_REG(MALI_MMU_CMD, 1);
- WRITE_MALI_REG(MALI_MMU_CMD, 6);
-
- for (i = 0; i<100; i++)
- udelay(500);
-
- WRITE_MALI_REG(MALI_APB_GP_INT_CLEAR, 0x3ff);
- WRITE_MALI_REG(MALI_MMU_INT_CLEAR, INT_ALL);
- WRITE_MALI_REG(MALI_MMU_INT_MASK, 0);
-
- WRITE_MALI_REG(MALI_APB_GP_INT_CLEAR, 0x707bff);
- WRITE_MALI_REG(MALI_APB_GP_INT_MASK, int_mask);
-
- spin_unlock_irqrestore(&lock, flags);
-
- dma_unmap_single(NULL, p_phy, 4096 * 3, DMA_TO_DEVICE);
-
- kfree((void *)p);
-
- /* Mali revision detection */
- if (last_power_mode == -1)
- mali_revb_flag = mali_meson_is_revb();
-}
-#else
-static void mali_meson_poweron(int first_poweron) {
- return;
-}
-#endif /*MESON_CPU_TYPE <= MESON_CPU_TYPE_MESON6 */
-
-_mali_osk_errcode_t mali_platform_init(void)
-{
- mali_clk = clk_get_sys("mali", "pll_fixed");
-
- if (mali_clk ) {
- if (!mali_init_flag) {
- clk_set_rate(mali_clk, 333000000);
- mali_clk->enable(mali_clk);
- malifix_init();
- mali_meson_poweron(1);
- mali_init_flag = 1;
- }
- MALI_SUCCESS;
- } else
- panic("linux kernel should > 3.0\n");
-
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6
- MALI_PRINT_ERROR(("Failed to lookup mali clock"));
- MALI_ERROR(_MALI_OSK_ERR_FAULT);
-#else
- MALI_SUCCESS;
-#endif /* CONFIG_ARCH_MESON6 */
-}
-
-_mali_osk_errcode_t mali_platform_deinit(void)
-{
- mali_init_flag =0;
- printk("MALI:mali_platform_deinit\n");
- malifix_exit();
-
- MALI_SUCCESS;
-}
-
-_mali_osk_errcode_t mali_platform_power_mode_change(mali_power_mode power_mode)
-{
- MALI_DEBUG_PRINT(3, ( "mali_platform_power_mode_change power_mode=%d\n", power_mode));
-
- switch (power_mode) {
- case MALI_POWER_MODE_LIGHT_SLEEP:
- case MALI_POWER_MODE_DEEP_SLEEP:
- /* Turn off mali clock gating */
- mali_clk->disable(mali_clk);
- break;
-
- case MALI_POWER_MODE_ON:
- /* Turn on MALI clock gating */
- mali_clk->enable(mali_clk);
- mali_meson_poweron(0);
- break;
- }
- last_power_mode = power_mode;
- MALI_SUCCESS;
-}
-
+++ /dev/null
-/*
- * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
- *
- * A copy of the licence is included with the program, and can also be obtained from Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-/**
- * @file mali_platform.h
- * Platform specific Mali driver functions
- */
-
-#ifndef __MALI_PLATFORM_H__
-#define __MALI_PLATFORM_H__
-
-#include "mali_osk.h"
-
-/** @brief description of power change reasons
- */
-typedef enum mali_power_mode_tag
-{
- MALI_POWER_MODE_ON, /**< Power Mali on */
- MALI_POWER_MODE_LIGHT_SLEEP, /**< Mali has been idle for a short time, or runtime PM suspend */
- MALI_POWER_MODE_DEEP_SLEEP, /**< Mali has been idle for a long time, or OS suspend */
-} mali_power_mode;
-
-/** @brief Platform specific setup and initialisation of MALI
- *
- * This is called from the entrypoint of the driver to initialize the platform
- *
- * @return _MALI_OSK_ERR_OK on success otherwise, a suitable _mali_osk_errcode_t error.
- */
-_mali_osk_errcode_t mali_platform_init(void);
-
-/** @brief Platform specific deinitialisation of MALI
- *
- * This is called on the exit of the driver to terminate the platform
- *
- * @return _MALI_OSK_ERR_OK on success otherwise, a suitable _mali_osk_errcode_t error.
- */
-_mali_osk_errcode_t mali_platform_deinit(void);
-
-/** @brief Platform specific powerdown sequence of MALI
- *
- * Notification from the Mali device driver stating the new desired power mode.
- * MALI_POWER_MODE_ON must be obeyed, while the other modes are optional.
- * @param power_mode defines the power modes
- * @return _MALI_OSK_ERR_OK on success otherwise, a suitable _mali_osk_errcode_t error.
- */
-_mali_osk_errcode_t mali_platform_power_mode_change(mali_power_mode power_mode);
-
-
-/** @brief Platform specific handling of GPU utilization data
- *
- * When GPU utilization data is enabled, this function will be
- * periodically called.
- *
- * @param utilization The workload utilization of the Mali GPU. 0 = no utilization, 256 = full utilization.
- */
-void mali_gpu_utilization_handler(u32 utilization);
-
-/** @brief Setting the power domain of MALI
- *
- * This function sets the power domain of MALI if Linux run time power management is enabled
- *
- * @param dev Reference to struct platform_device (defined in linux) used by MALI GPU
- */
-void set_mali_parent_power_domain(void* dev);
-
-#endif
+++ /dev/null
-/*
- * This confidential and proprietary software may be used only as
- * authorised by a licensing agreement from AMLOGIC, INC.
- * (C) COPYRIGHT 2011 AMLOGIC, INC.
- * ALL RIGHTS RESERVED
- * The entire notice above must be reproduced on all authorised
- * copies and copies may only be made to the extent permitted
- * by a licensing agreement from AMLOGIC, INC.
- */
-
-#ifndef MALI_POWERON_REG_H
-#define MALI_POWERON_REG_H
-
-#define MALI_PP_PP_VERSION_MAGIC 0xCD070100UL
-
-#if defined(IO_APB2_BUS_PHY_BASE)
-#define WRITE_MALI_REG(reg, val) \
- __raw_writel(val, (volatile void *)(reg - IO_APB2_BUS_PHY_BASE + IO_APB2_BUS_BASE))
-#define READ_MALI_REG(reg) \
- __raw_readl((volatile void *)(reg - IO_APB2_BUS_PHY_BASE + IO_APB2_BUS_BASE))
-#else
-#define WRITE_MALI_REG(reg, val) \
- __raw_writel(val, (volatile void *)(reg - IO_APB_BUS_PHY_BASE + IO_APB_BUS_BASE))
-#define READ_MALI_REG(reg) \
- __raw_readl((volatile void *)(reg - IO_APB_BUS_PHY_BASE + IO_APB_BUS_BASE))
-#endif
-
-#define MALI_APB_GP_VSCL_START 0xd0060000
-#define MALI_APB_GP_VSCL_END 0xd0060004
-#define MALI_APB_GP_CMD 0xd0060020
-#define MALI_APB_GP_INT_RAWSTAT 0xd0060024
-#define MALI_APB_GP_INT_CLEAR 0xd0060028
-#define MALI_APB_GP_INT_MASK 0xd006002c
-#define MALI_APB_GP_INT_STAT 0xd0060030
-
-#define MALI_MMU_DTE_ADDR 0xd0063000
-#define MALI_MMU_STATUS 0xd0063004
-#define MALI_MMU_CMD 0xd0063008
-#define MALI_MMU_RAW_STATUS 0xd0064014
-#define MALI_MMU_INT_CLEAR 0xd0064018
-#define MALI_MMU_INT_MASK 0xd006401c
-#define MALI_MMU_INT_STATUS 0xd0064020
-
-#define MALI_PP_MMU_DTE_ADDR 0xd0064000
-#define MALI_PP_MMU_STATUS 0xd0064004
-#define MALI_PP_MMU_CMD 0xd0064008
-#define MALI_PP_MMU_RAW_STATUS 0xd0064014
-#define MALI_PP_MMU_INT_CLEAR 0xd0064018
-#define MALI_PP_MMU_INT_MASK 0xd006401c
-#define MALI_PP_MMU_INT_STATUS 0xd0064020
-
-#define MALI_APB_PP_REND_LIST_ADDR 0xd0068000
-#define MALI_APB_PP_REND_RSW_BASE 0xd0068004
-#define MALI_APB_PP_REND_VERTEX_BASE 0xd0068008
-#define MALI_APB_PPSUBPIXEL_SPECIFIER 0xd0068048
-#define MALI_APB_WB0_SOURCE_SELECT 0xd0068100
-#define MALI_APB_WB0_TARGET_ADDR 0xd0068104
-#define MALI_APB_WB0_TARGET_SCANLINE_LENGTH 0xd0068114
-
-#define MALI_PP_PP_VERSION 0xd0069000
-#define MALI_PP_STATUS 0xd0069008
-#define MALI_PP_CTRL_MGMT 0xd006900C
-#define MALI_PP_INT_RAWSTAT 0xd0069020
-#define MALI_PP_INT_CLEAR 0xd0069024
-#define MALI_PP_INT_MASK 0xd0069028
-#define MALI_PP_INT_STAT 0xd006902C
-
-#endif /* MALI_POWERON_REG_H */
+++ /dev/null
-/*
- * platform.c
- *
- * clock source setting and resource config
- *
- * Created on: Dec 4, 2013
- * Author: amlogic
- */
-
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/module.h>
-#include <linux/ioport.h>
-#include <linux/slab.h>
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#include <asm/io.h>
-#include <linux/mali/mali_utgard.h>
-
-#include <common/mali_kernel_common.h>
-#include <common/mali_osk_profiling.h>
-#include <common/mali_pmu.h>
-
-#include "meson_main.h"
-#include "mali_fix.h"
-#include "mali_platform.h"
-
-/**
- * For Meson 6tvd.
- *
- */
-
-#if MESON_CPU_TYPE <= MESON_CPU_TYPE_MESON6TV
-
-u32 mali_dvfs_clk[1];
-u32 mali_dvfs_clk_sample[1];
-
-#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6TV
-#undef INT_MALI_GP
-#undef INT_MALI_GP_MMU
-#undef INT_MALI_PP
-#undef INT_MALI_PP2
-#undef INT_MALI_PP3
-#undef INT_MALI_PP4
-#undef INT_MALI_PP_MMU
-#undef INT_MALI_PP2_MMU
-#undef INT_MALI_PP3_MMU
-#undef INT_MALI_PP4_MMU
-
-#define INT_MALI_GP (48+32)
-#define INT_MALI_GP_MMU (49+32)
-#define INT_MALI_PP (50+32)
-#define INT_MALI_PP2 (58+32)
-#define INT_MALI_PP3 (60+32)
-#define INT_MALI_PP4 (62+32)
-#define INT_MALI_PP_MMU (51+32)
-#define INT_MALI_PP2_MMU (59+32)
-#define INT_MALI_PP3_MMU (61+32)
-#define INT_MALI_PP4_MMU (63+32)
-
-#ifndef CONFIG_MALI400_4_PP
-static struct resource meson_mali_resources[] =
-{
- MALI_GPU_RESOURCES_MALI400_MP2(0xd0060000,
- INT_MALI_GP, INT_MALI_GP_MMU,
- INT_MALI_PP, INT_MALI_PP_MMU,
- INT_MALI_PP2, INT_MALI_PP2_MMU)
-};
-#else
-static struct resource meson_mali_resources[] =
-{
- MALI_GPU_RESOURCES_MALI400_MP4(0xd0060000,
- INT_MALI_GP, INT_MALI_GP_MMU,
- INT_MALI_PP, INT_MALI_PP_MMU,
- INT_MALI_PP2, INT_MALI_PP2_MMU,
- INT_MALI_PP3, INT_MALI_PP3_MMU,
- INT_MALI_PP4, INT_MALI_PP4_MMU
- )
-};
-#endif
-
-#elif MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
-
-#undef INT_MALI_GP
-#undef INT_MALI_GP_MMU
-#undef INT_MALI_PP
-#undef INT_MALI_PP2
-#undef INT_MALI_PP_MMU
-#undef INT_MALI_PP2_MMU
-
-#define INT_MALI_GP (48+32)
-#define INT_MALI_GP_MMU (49+32)
-#define INT_MALI_PP (50+32)
-#define INT_MALI_PP_MMU (51+32)
-#define INT_MALI_PP2_MMU ( 6+32)
-
-static struct resource meson_mali_resources[] =
-{
- MALI_GPU_RESOURCES_MALI400_MP2(0xd0060000,
- INT_MALI_GP, INT_MALI_GP_MMU,
- INT_MALI_PP, INT_MALI_PP2_MMU,
- INT_MALI_PP_MMU, INT_MALI_PP2_MMU)
-};
-
-#else /* MESON_CPU_TYPE == MESON_CPU_TYPE_MESON3 */
-
-#undef INT_MALI_GP
-#undef INT_MALI_GP_MMU
-#undef INT_MALI_PP
-#undef INT_MALI_PP_MMU
-
-#define INT_MALI_GP 48
-#define INT_MALI_GP_MMU 49
-#define INT_MALI_PP 50
-#define INT_MALI_PP_MMU 51
-
-static struct resource meson_mali_resources[] =
-{
- MALI_GPU_RESOURCES_MALI400_MP1(0xd0060000,
- INT_MALI_GP, INT_MALI_GP_MMU, INT_MALI_PP, INT_MALI_PP_MMU)
-};
-#endif /* MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6TV */
-
-void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data)
-{
-
-}
-
-mali_plat_info_t mali_plat_data = {
-
-};
-
-int mali_meson_init_start(struct platform_device* ptr_plt_dev)
-{
- /* for mali platform data. */
- struct mali_gpu_device_data* pdev = ptr_plt_dev->dev.platform_data;
-
- pdev->control_interval = 1000;
- pdev->utilization_callback = mali_gpu_utilization_callback;
-
- /* for resource data. */
- ptr_plt_dev->num_resources = ARRAY_SIZE(meson_mali_resources);
- ptr_plt_dev->resource = meson_mali_resources;
- return 0;
-}
-
-int mali_meson_init_finish(struct platform_device* ptr_plt_dev)
-{
- mali_platform_init();
- return 0;
-}
-
-int mali_meson_uninit(struct platform_device* ptr_plt_dev)
-{
- mali_platform_deinit();
- return 0;
-}
-
-int mali_light_suspend(struct device *device)
-{
- int ret = 0;
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_suspend(device);
- }
-
- mali_platform_power_mode_change(MALI_POWER_MODE_LIGHT_SLEEP);
- return ret;
-}
-
-int mali_light_resume(struct device *device)
-{
- int ret = 0;
-
- mali_platform_power_mode_change(MALI_POWER_MODE_ON);
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_resume(device);
- }
- return ret;
-}
-
-int mali_deep_suspend(struct device *device)
-{
- int ret = 0;
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->suspend(device);
- }
-
- mali_platform_power_mode_change(MALI_POWER_MODE_DEEP_SLEEP);
- return ret;
-}
-
-int mali_deep_resume(struct device *device)
-{
- int ret = 0;
-
- mali_platform_power_mode_change(MALI_POWER_MODE_ON);
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->resume(device);
- }
- return ret;
-
-}
-
-void mali_core_scaling_term(void)
-{
-
-}
-
-int get_gpu_max_clk_level(void)
-{
- return 0;
-}
-
-void mali_post_init(void)
-{
-}
-#endif /* MESON_CPU_TYPE <= MESON_CPU_TYPE_MESON6 */
+++ /dev/null
-/*
- * platform.c
- *
- * clock source setting and resource config
- *
- * Created on: Dec 4, 2013
- * Author: amlogic
- */
-
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/module.h> /* kernel module definitions */
-#include <linux/ioport.h> /* request_mem_region */
-#include <linux/slab.h>
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#include <asm/io.h>
-#include <linux/mali/mali_utgard.h>
-
-#include <common/mali_kernel_common.h>
-#include <common/mali_osk_profiling.h>
-#include <common/mali_pmu.h>
-
-#include "meson_main.h"
-
-/*
- * For Meson 8TVD.
- *
- */
-
-#define CFG_PP 2
-#define CFG_CLOCK 3
-#define CFG_MIN_PP 1
-#define CFG_MIN_CLOCK 0
-
-/* fclk is 2Ghz. */
-#define FCLK_DEV5 (7 << 9) /* 400 Mhz */
-#define FCLK_DEV3 (6 << 9) /* 666 Mhz */
-#define FCLK_DEV2 (5 << 9) /* 1000 Mhz */
-#define FCLK_DEV7 (4 << 9) /* 285 Mhz */
-
-u32 mali_dvfs_clk[] = {
- FCLK_DEV7 | 9, /* 100 Mhz */
- FCLK_DEV2 | 4, /* 200 Mhz */
- FCLK_DEV3 | 1, /* 333 Mhz */
- FCLK_DEV5 | 0, /* 400 Mhz */
-};
-
-u32 mali_dvfs_clk_sample[] = {
- 100, /* 182.1 Mhz */
- 200, /* 318.7 Mhz */
- 333, /* 425 Mhz */
- 400, /* 510 Mhz */
-};
-
-static mali_plat_info_t mali_plat_data = {
- .cfg_pp = CFG_PP, /* number of pp. */
- .cfg_min_pp = CFG_MIN_PP,
- .def_clock = CFG_CLOCK, /* gpu clock used most of time.*/
- .cfg_clock = CFG_CLOCK, /* max gpu clock. */
- .cfg_min_clock = CFG_MIN_CLOCK,
-
- .clk = mali_dvfs_clk, /* clock source table. */
- .clk_sample = mali_dvfs_clk_sample, /* freqency table for show. */
- .clk_len = sizeof(mali_dvfs_clk) / sizeof(mali_dvfs_clk[0]),
- .have_switch = 0,
-};
-
-#define MALI_USER_PP0 AM_IRQ4(31)
-
-static struct resource mali_gpu_resources[] =
-{
-MALI_GPU_RESOURCES_MALI450_MP2_PMU(0xC9140000, INT_MALI_GP, INT_MALI_GP_MMU,
- MALI_USER_PP0, INT_MALI_PP_MMU,
- INT_MALI_PP1, INT_MALI_PP_MMU1,
- INT_MALI_PP)
-};
-
-int mali_meson_init_start(struct platform_device* ptr_plt_dev)
-{
- ptr_plt_dev->num_resources = ARRAY_SIZE(mali_gpu_resources);
- ptr_plt_dev->resource = mali_gpu_resources;
- return mali_clock_init(&mali_plat_data);
-}
-
-int mali_meson_init_finish(struct platform_device* ptr_plt_dev)
-{
- return 0;
-}
-
-int mali_meson_uninit(struct platform_device* ptr_plt_dev)
-{
- return 0;
-}
-
-static int mali_cri_pmu_on_off(size_t param)
-{
- struct mali_pmu_core *pmu;
-
- MALI_DEBUG_PRINT(4, ("mali_os_suspend() called\n"));
- pmu = mali_pmu_get_global_pmu_core();
- if (param == 0)
- mali_pmu_power_down_all(pmu);
- else
- mali_pmu_power_up_all(pmu);
- return 0;
-}
-
-int mali_light_suspend(struct device *device)
-{
- int ret = 0;
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- 0, 0, 0, 0, 0);
-#endif
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_suspend(device);
- }
-
- /* clock scaling. Kasin..*/
- mali_clock_critical(mali_cri_pmu_on_off, 0);
- disable_clock();
- return ret;
-}
-
-int mali_light_resume(struct device *device)
-{
- int ret = 0;
- /* clock scaling. Kasin..*/
- enable_clock();
-
- mali_clock_critical(mali_cri_pmu_on_off, 1);
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- 0, 0, 0, 0, 0);
-#endif
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_resume(device);
- }
- return ret;
-}
-
-int mali_deep_suspend(struct device *device)
-{
- int ret = 0;
- //enable_clock();
- //flush_scaling_job();
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->suspend(device);
- }
-
- /* clock scaling off. Kasin... */
- mali_clock_critical(mali_cri_pmu_on_off, 0);
- disable_clock();
- return ret;
-}
-
-int mali_deep_resume(struct device *device)
-{
- int ret = 0;
- /* clock scaling up. Kasin.. */
- enable_clock();
- mali_clock_critical(mali_cri_pmu_on_off, 1);
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->resume(device);
- }
- return ret;
-
-}
-
-void mali_post_init(void)
-{
-}
+++ /dev/null
-/*
- * platform.c
- *
- * clock source setting and resource config
- *
- * Created on: Dec 4, 2013
- * Author: amlogic
- */
-
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/module.h> /* kernel module definitions */
-#include <linux/ioport.h> /* request_mem_region */
-#include <linux/slab.h>
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#endif
-#include <asm/io.h>
-#include <linux/mali/mali_utgard.h>
-#ifdef CONFIG_GPU_THERMAL
-#include <linux/gpu_cooling.h>
-#include <linux/gpucore_cooling.h>
-#endif
-#include <common/mali_kernel_common.h>
-#include <common/mali_osk_profiling.h>
-#include <common/mali_pmu.h>
-
-#include "meson_main.h"
-
-/*
- * For Meson 8 M2.
- *
- */
-
-#define CFG_PP 6
-#define CFG_CLOCK 3
-#define CFG_MIN_PP 1
-#define CFG_MIN_CLOCK 0
-
-/* fclk is 2550Mhz. */
-#define FCLK_DEV3 (6 << 9) /* 850 Mhz */
-#define FCLK_DEV4 (5 << 9) /* 637.5 Mhz */
-#define FCLK_DEV5 (7 << 9) /* 510 Mhz */
-#define FCLK_DEV7 (4 << 9) /* 364.3 Mhz */
-
-static u32 mali_dvfs_clk[] = {
- FCLK_DEV7 | 1, /* 182.1 Mhz */
- FCLK_DEV4 | 1, /* 318.7 Mhz */
- FCLK_DEV3 | 1, /* 425 Mhz */
- FCLK_DEV5 | 0, /* 510 Mhz */
- FCLK_DEV4 | 0, /* 637.5 Mhz */
-};
-
-static u32 mali_dvfs_clk_sample[] = {
- 182, /* 182.1 Mhz */
- 319, /* 318.7 Mhz */
- 425, /* 425 Mhz */
- 510, /* 510 Mhz */
- 637, /* 637.5 Mhz */
-};
-//////////////////////////////////////
-//for dvfs
-struct mali_gpu_clk_item meson_gpu_clk[] = {
- {182, 1150}, /* 182.1 Mhz, 1150mV */
- {319, 1150}, /* 318.7 Mhz */
- {425, 1150}, /* 425 Mhz */
- {510, 1150}, /* 510 Mhz */
- {637, 1150}, /* 637.5 Mhz */
-};
-struct mali_gpu_clock meson_gpu_clk_info = {
- .item = meson_gpu_clk,
- .num_of_steps = ARRAY_SIZE(meson_gpu_clk),
-};
-static int cur_gpu_clk_index = 0;
-//////////////////////////////////////
-static mali_dvfs_threshold_table mali_dvfs_table[]={
- { 0, 0, 3, 30, 80}, /* for 182.1 */
- { 1, 1, 3, 40, 205}, /* for 318.7 */
- { 2, 2, 3, 150, 215}, /* for 425.0 */
- { 3, 3, 3, 170, 253}, /* for 510.0 */
- { 4, 4, 3, 230, 255}, /* for 637.5 */
- { 0, 0, 3, 0, 0}
-};
-
-static void mali_plat_preheat(void);
-static mali_plat_info_t mali_plat_data = {
- .cfg_pp = CFG_PP, /* number of pp. */
- .cfg_min_pp = CFG_MIN_PP,
- .turbo_clock = 4, /* reserved clock src. */
- .def_clock = 2, /* gpu clock used most of time.*/
- .cfg_clock = CFG_CLOCK, /* max gpu clock. */
- .cfg_clock_bkup = CFG_CLOCK,
- .cfg_min_clock = CFG_MIN_CLOCK,
-
- .sc_mpp = 3, /* number of pp used most of time.*/
- .bst_gpu = 210, /* threshold for boosting gpu. */
- .bst_pp = 160, /* threshold for boosting PP. */
-
- .clk = mali_dvfs_clk, /* clock source table. */
- .clk_sample = mali_dvfs_clk_sample, /* freqency table for show. */
- .clk_len = sizeof(mali_dvfs_clk) / sizeof(mali_dvfs_clk[0]),
- .have_switch = 1,
-
- .dvfs_table = mali_dvfs_table, /* DVFS table. */
- .dvfs_table_size = sizeof(mali_dvfs_table) / sizeof(mali_dvfs_threshold_table),
-
- .scale_info = {
- CFG_MIN_PP, /* minpp */
- CFG_PP, /* maxpp, should be same as cfg_pp */
- CFG_MIN_CLOCK, /* minclk */
- CFG_CLOCK, /* maxclk should be same as cfg_clock */
- },
-
- .limit_on = 1,
- .plat_preheat = mali_plat_preheat,
-};
-
-static void mali_plat_preheat(void)
-{
-#ifndef CONFIG_MALI_DVFS
- u32 pre_fs;
- u32 clk, pp;
-
- if (get_mali_schel_mode() != MALI_PP_FS_SCALING)
- return;
-
- get_mali_rt_clkpp(&clk, &pp);
- pre_fs = mali_plat_data.def_clock + 1;
- if (clk < pre_fs)
- clk = pre_fs;
- if (pp < mali_plat_data.sc_mpp)
- pp = mali_plat_data.sc_mpp;
- set_mali_rt_clkpp(clk, pp, 1);
-#endif
-}
-
-mali_plat_info_t* get_mali_plat_data(void) {
- return &mali_plat_data;
-}
-
-int get_mali_freq_level(int freq)
-{
- int i = 0, level = -1;
- int mali_freq_num;
-
- if (freq < 0)
- return level;
-
- mali_freq_num = mali_plat_data.dvfs_table_size - 1;
- if (freq <= mali_plat_data.clk_sample[0])
- level = mali_freq_num-1;
- if (freq >= mali_plat_data.clk_sample[mali_freq_num - 1])
- level = 0;
- for (i=0; i<mali_freq_num - 1 ;i++) {
- if (freq >= mali_plat_data.clk_sample[i] && freq <= mali_plat_data.clk_sample[i + 1]) {
- level = i;
- level = mali_freq_num-level - 1;
- }
- }
- return level;
-}
-
-unsigned int get_mali_max_level(void)
-{
- return mali_plat_data.dvfs_table_size - 1;
-}
-
-#if 0
-static struct resource mali_gpu_resources[] =
-{
- MALI_GPU_RESOURCES_MALI450_MP6_PMU(IO_MALI_APB_PHY_BASE, INT_MALI_GP, INT_MALI_GP_MMU,
- INT_MALI_PP0, INT_MALI_PP0_MMU,
- INT_MALI_PP1, INT_MALI_PP1_MMU,
- INT_MALI_PP2, INT_MALI_PP2_MMU,
- INT_MALI_PP4, INT_MALI_PP4_MMU,
- INT_MALI_PP5, INT_MALI_PP5_MMU,
- INT_MALI_PP6, INT_MALI_PP6_MMU,
- INT_MALI_PP)
-};
-#else
-static struct resource mali_gpu_resources[] =
-{
- { .name = "Mali_L2", .flags = 0x00000200, .start = 0xd00c0000 + 0x10000, .end = 0xd00c0000 + 0x10000 + 0x200, },
- { .name = "Mali_GP", .flags = 0x00000200, .start = 0xd00c0000 + 0x00000, .end = 0xd00c0000 + 0x00000 + 0x100, },
- { .name = "Mali_GP_IRQ", .flags = 0x00000400, .start = (160 + 32), .end = (160 + 32), },
- { .name = "Mali_GP_MMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x03000, .end = 0xd00c0000 + 0x03000 + 0x100, },
- { .name = "Mali_GP_MMU_IRQ", .flags = 0x00000400, .start = (161 + 32), .end = (161 + 32), },
- { .name = "Mali_L2", .flags = 0x00000200, .start = 0xd00c0000 + 0x01000, .end = 0xd00c0000 + 0x01000 + 0x200, },
- { .name = "Mali_PP" "0", .flags = 0x00000200, .start = 0xd00c0000 + 0x08000, .end = 0xd00c0000 + 0x08000 + 0x1100, },
- { .name = "Mali_PP" "0" "_IRQ", .flags = 0x00000400, .start = (164 + 32), .end = (164 + 32), },
- { .name = "Mali_PP" "0" "_MMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x04000, .end = 0xd00c0000 + 0x04000 + 0x100, },
- { .name = "Mali_PP" "0" "_MMU_IRQ", .flags = 0x00000400, .start = (165 + 32), .end = (165 + 32), },
- { .name = "Mali_PP" "1", .flags = 0x00000200, .start = 0xd00c0000 + 0x0A000, .end = 0xd00c0000 + 0x0A000 + 0x1100, },
- { .name = "Mali_PP" "1" "_IRQ", .flags = 0x00000400, .start = (166 + 32), .end = (166 + 32), },
- { .name = "Mali_PP" "1" "_MMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x05000, .end = 0xd00c0000 + 0x05000 + 0x100, },
- { .name = "Mali_PP" "1" "_MMU_IRQ", .flags = 0x00000400, .start = (167 + 32), .end = (167 + 32), },
- { .name = "Mali_PP" "2", .flags = 0x00000200, .start = 0xd00c0000 + 0x0C000, .end = 0xd00c0000 + 0x0C000 + 0x1100, },
- { .name = "Mali_PP" "2" "_IRQ", .flags = 0x00000400, .start = (168 + 32), .end = (168 + 32), },
- { .name = "Mali_PP" "2" "_MMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x06000, .end = 0xd00c0000 + 0x06000 + 0x100, },
- { .name = "Mali_PP" "2" "_MMU_IRQ", .flags = 0x00000400, .start = (169 + 32), .end = (169 + 32), },
- { .name = "Mali_L2", .flags = 0x00000200, .start = 0xd00c0000 + 0x11000, .end = 0xd00c0000 + 0x11000 + 0x200, },
- { .name = "Mali_PP" "3", .flags = 0x00000200, .start = 0xd00c0000 + 0x28000, .end = 0xd00c0000 + 0x28000 + 0x1100, },
- { .name = "Mali_PP" "3" "_IRQ", .flags = 0x00000400, .start = (172 + 32), .end = (172 + 32), },
- { .name = "Mali_PP" "3" "_MMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x1C000, .end = 0xd00c0000 + 0x1C000 + 0x100, },
- { .name = "Mali_PP" "3" "_MMU_IRQ", .flags = 0x00000400, .start = (173 + 32), .end = (173 + 32), },
- { .name = "Mali_PP" "4", .flags = 0x00000200, .start = 0xd00c0000 + 0x2A000, .end = 0xd00c0000 + 0x2A000 + 0x1100, },
- { .name = "Mali_PP" "4" "_IRQ", .flags = 0x00000400, .start = (174 + 32), .end = (174 + 32), },
- { .name = "Mali_PP" "4" "_MMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x1D000, .end = 0xd00c0000 + 0x1D000 + 0x100, },
- { .name = "Mali_PP" "4" "_MMU_IRQ", .flags = 0x00000400, .start = (175 + 32), .end = (175 + 32), },
- { .name = "Mali_PP" "5", .flags = 0x00000200, .start = 0xd00c0000 + 0x2C000, .end = 0xd00c0000 + 0x2C000 + 0x1100, },
- { .name = "Mali_PP" "5" "_IRQ", .flags = 0x00000400, .start = (176 + 32), .end = (176 + 32), },
- { .name = "Mali_PP" "5" "_MMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x1E000, .end = 0xd00c0000 + 0x1E000 + 0x100, },
- { .name = "Mali_PP" "5" "_MMU_IRQ", .flags = 0x00000400, .start = (177 + 32), .end = (177 + 32), },
- { .name = "Mali_Broadcast", .flags = 0x00000200, .start = 0xd00c0000 + 0x13000, .end = 0xd00c0000 + 0x13000 + 0x100, },
- { .name = "Mali_DLBU", .flags = 0x00000200, .start = 0xd00c0000 + 0x14000, .end = 0xd00c0000 + 0x14000 + 0x100, },
- { .name = "Mali_PP_Broadcast", .flags = 0x00000200, .start = 0xd00c0000 + 0x16000, .end = 0xd00c0000 + 0x16000 + 0x1100, },
- { .name = "Mali_PP_Broadcast_IRQ", .flags = 0x00000400, .start = (162 + 32), .end = (162 + 32), },
- { .name = "Mali_PP_MMU_Broadcast", .flags = 0x00000200, .start = 0xd00c0000 + 0x15000, .end = 0xd00c0000 + 0x15000 + 0x100, },
- { .name = "Mali_DMA", .flags = 0x00000200, .start = 0xd00c0000 + 0x12000, .end = 0xd00c0000 + 0x12000 + 0x100, },
- { .name = "Mali_PMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x02000, .end = 0xd00c0000 + 0x02000 + 0x100, },
-};
-#endif
-#ifdef CONFIG_GPU_THERMAL
-static void set_limit_mali_freq(u32 idx)
-{
- if (mali_plat_data.limit_on == 0)
- return;
- if (idx > mali_plat_data.turbo_clock || idx < mali_plat_data.scale_info.minclk)
- return;
- mali_plat_data.scale_info.maxclk= idx;
- revise_mali_rt();
-}
-
-static u32 get_limit_mali_freq(void)
-{
- return mali_plat_data.scale_info.maxclk;
-}
-#endif
-
-#ifdef CONFIG_GPU_THERMAL
-static u32 set_limit_pp_num(u32 num)
-{
- u32 ret = -1;
- if (mali_plat_data.limit_on == 0)
- goto quit;
- if (num > mali_plat_data.cfg_pp ||
- num < mali_plat_data.scale_info.minpp)
- goto quit;
- mali_plat_data.scale_info.maxpp = num;
- revise_mali_rt();
- ret = 0;
-quit:
- return ret;
-}
-#endif
-
-void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data);
-
-#if 0
-struct mali_gpu_clk_item {
- unsigned int clock; /* unit(MHz) */
- unsigned int vol;
-};
-
-struct mali_gpu_clock {
- struct mali_gpu_clk_item *item;
- unsigned int num_of_steps;
-};
-#endif
-
-/* Function that platfrom report it's clock info which driver can set, needed when CONFIG_MALI_DVFS enabled */
-void meson_platform_get_clock_info(struct mali_gpu_clock **data) {
- *data = &meson_gpu_clk_info;
-}
-
-/* Function that get the current clock info, needed when CONFIG_MALI_DVFS enabled */
-int meson_platform_get_freq(void) {
- printk("get cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
- return cur_gpu_clk_index;
-}
-
-/* Fuction that platform callback for freq setting, needed when CONFIG_MALI_DVFS enabled */
-int meson_platform_set_freq(int setting_clock_step) {
-
- if (cur_gpu_clk_index == setting_clock_step) {
- return 0;
- }
-
- mali_clock_set(setting_clock_step);
-
- cur_gpu_clk_index = setting_clock_step;
- printk("set cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
-
- return 0;
-}
-
-int mali_meson_init_start(struct platform_device* ptr_plt_dev)
-{
- struct mali_gpu_device_data* pdev = ptr_plt_dev->dev.platform_data;
-
- /* chip mark detect. */
-#ifdef IS_MESON_M8_CPU
- if (IS_MESON_M8_CPU) {
- mali_plat_data.have_switch = 0;
- }
-#endif
-
- /* for resource data. */
- ptr_plt_dev->num_resources = ARRAY_SIZE(mali_gpu_resources);
- ptr_plt_dev->resource = mali_gpu_resources;
-
- /*for dvfs*/
-#ifndef CONFIG_MALI_DVFS
- /* for mali platform data. */
- pdev->control_interval = 300;
- pdev->utilization_callback = mali_gpu_utilization_callback;
-#else
- pdev->get_clock_info = meson_platform_get_clock_info;
- pdev->get_freq = meson_platform_get_freq;
- pdev->set_freq = meson_platform_set_freq;
-#endif
-
- return mali_clock_init(&mali_plat_data);
-}
-
-int mali_meson_init_finish(struct platform_device* ptr_plt_dev)
-{
-#ifndef CONFIG_MALI_DVFS
- if (mali_core_scaling_init(&mali_plat_data) < 0)
- return -1;
-#else
- printk("disable meson own dvfs\n");
-#endif
- return 0;
-}
-
-int mali_meson_uninit(struct platform_device* ptr_plt_dev)
-{
- return 0;
-}
-
-static int mali_cri_light_suspend(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- mali_pm_statue = 1;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_suspend(device);
- }
- mali_pmu_power_down_all(pmu);
- return ret;
-}
-
-static int mali_cri_light_resume(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- mali_pmu_power_up_all(pmu);
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_resume(device);
- }
- mali_pm_statue = 0;
- return ret;
-}
-
-static int mali_cri_deep_suspend(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->suspend(device);
- }
- mali_pmu_power_down_all(pmu);
- return ret;
-}
-
-static int mali_cri_deep_resume(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- mali_pmu_power_up_all(pmu);
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->resume(device);
- }
- return ret;
-
-}
-
-int mali_light_suspend(struct device *device)
-{
- int ret = 0;
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- 0, 0, 0, 0, 0);
-#endif
-
- /* clock scaling. Kasin..*/
- ret = mali_clock_critical(mali_cri_light_suspend, (size_t)device);
- disable_clock();
- return ret;
-}
-
-int mali_light_resume(struct device *device)
-{
- int ret = 0;
- enable_clock();
- ret = mali_clock_critical(mali_cri_light_resume, (size_t)device);
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- get_current_frequency(), 0, 0, 0, 0);
-#endif
- return ret;
-}
-
-int mali_deep_suspend(struct device *device)
-{
- int ret = 0;
-
- mali_pm_statue = 1;
- enable_clock();
-#ifndef CONFIG_MALI_DVFS
- flush_scaling_job();
-#endif
-
- /* clock scaling off. Kasin... */
- ret = mali_clock_critical(mali_cri_deep_suspend, (size_t)device);
- disable_clock();
- return ret;
-}
-
-int mali_deep_resume(struct device *device)
-{
- int ret = 0;
-
- /* clock scaling up. Kasin.. */
- enable_clock();
- ret = mali_clock_critical(mali_cri_deep_resume, (size_t)device);
- mali_pm_statue = 0;
- return ret;
-
-}
-
-void mali_post_init(void)
-{
-#ifdef CONFIG_GPU_THERMAL
- int err;
- struct gpufreq_cooling_device *gcdev = NULL;
- struct gpucore_cooling_device *gccdev = NULL;
-
- gcdev = gpufreq_cooling_alloc();
- register_gpu_freq_info(get_current_frequency);
- if (IS_ERR(gcdev))
- printk("malloc gpu cooling buffer error!!\n");
- else if (!gcdev)
- printk("system does not enable thermal driver\n");
- else {
- gcdev->get_gpu_freq_level = get_mali_freq_level;
- gcdev->get_gpu_max_level = get_mali_max_level;
- gcdev->set_gpu_freq_idx = set_limit_mali_freq;
- gcdev->get_gpu_current_max_level = get_limit_mali_freq;
- err = gpufreq_cooling_register(gcdev);
- if (err < 0)
- printk("register GPU cooling error\n");
- printk("gpu cooling register okay with err=%d\n",err);
- }
-
- gccdev = gpucore_cooling_alloc();
- if (IS_ERR(gccdev))
- printk("malloc gpu core cooling buffer error!!\n");
- else if (!gccdev)
- printk("system does not enable thermal driver\n");
- else {
- gccdev->max_gpu_core_num=mali_plat_data.cfg_pp;
- gccdev->set_max_pp_num=set_limit_pp_num;
- err = (int)gpucore_cooling_register(gccdev);
- if (err < 0)
- printk("register GPU cooling error\n");
- printk("gpu core cooling register okay with err=%d\n",err);
- }
-#endif
-}
+++ /dev/null
-/*
- * platform.c
- *
- * clock source setting and resource config
- *
- * Created on: Dec 4, 2013
- * Author: amlogic
- */
-
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/module.h> /* kernel module definitions */
-#include <linux/ioport.h> /* request_mem_region */
-#include <linux/slab.h>
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#include <asm/io.h>
-#include <linux/mali/mali_utgard.h>
-#include <linux/gpu_cooling.h>
-#include <linux/gpucore_cooling.h>
-#include <common/mali_kernel_common.h>
-#include <common/mali_osk_profiling.h>
-#include <common/mali_pmu.h>
-
-#include "meson_main.h"
-
-/*
- * For Meson 8B.
- *
- */
-
-#define CFG_PP 2
-#define CFG_CLOCK 3
-#define CFG_MIN_PP 1
-#define CFG_MIN_CLOCK 0
-
-/* fclk is 2550Mhz. */
-#define FCLK_DEV3 (6 << 9) /* 850 Mhz */
-#define FCLK_DEV4 (5 << 9) /* 637.5 Mhz */
-#define FCLK_DEV5 (7 << 9) /* 510 Mhz */
-#define FCLK_DEV7 (4 << 9) /* 364.3 Mhz */
-
-static u32 mali_dvfs_clk[] = {
- FCLK_DEV5 | 1, /* 255 Mhz */
- FCLK_DEV7 | 0, /* 364 Mhz */
- FCLK_DEV3 | 1, /* 425 Mhz */
- FCLK_DEV5 | 0, /* 510 Mhz */
- FCLK_DEV4 | 0, /* 637.5 Mhz */
-};
-
-static u32 mali_dvfs_clk_sample[] = {
- 255, /* 182.1 Mhz */
- 364, /* 318.7 Mhz */
- 425, /* 425 Mhz */
- 510, /* 510 Mhz */
- 637, /* 637.5 Mhz */
-};
-
-//////////////////////////////////////
-//for dvfs
-struct mali_gpu_clk_item meson_gpu_clk[] = {
- {255, 1150}, /* 182.1 Mhz, 1150mV */
- {364, 1150}, /* 318.7 Mhz */
- {425, 1150}, /* 425 Mhz */
- {510, 1150}, /* 510 Mhz */
- {637, 1150}, /* 637.5 Mhz */
-};
-struct mali_gpu_clock meson_gpu_clk_info = {
- .item = meson_gpu_clk,
- .num_of_steps = ARRAY_SIZE(meson_gpu_clk),
-};
-static int cur_gpu_clk_index = 0;
-//////////////////////////////////////
-
-static mali_dvfs_threshold_table mali_dvfs_table[]={
- { 0, 0, 5, 30 , 180}, /* for 255 */
- { 1, 1, 5, 152, 205}, /* for 364 */
- { 2, 2, 5, 180, 212}, /* for 425 */
- { 3, 3, 5, 205, 236}, /* for 510 */
- { 4, 4, 5, 230, 255}, /* for 637 */
- { 0, 0, 5, 0, 0}
-};
-
-static void mali_plat_preheat(void);
-static mali_plat_info_t mali_plat_data = {
- .cfg_pp = CFG_PP, /* number of pp. */
- .cfg_min_pp = CFG_MIN_PP,
- .turbo_clock = 4, /* reserved clock src. */
- .def_clock = 2, /* gpu clock used most of time.*/
- .cfg_clock = CFG_CLOCK, /* max gpu clock. */
- .cfg_clock_bkup = CFG_CLOCK,
- .cfg_min_clock = CFG_MIN_CLOCK,
-
- .sc_mpp = 2, /* number of pp used most of time.*/
- .bst_gpu = 210, /* threshold for boosting gpu. */
- .bst_pp = 160, /* threshold for boosting PP. */
-
- .clk = mali_dvfs_clk, /* clock source table. */
- .clk_sample = mali_dvfs_clk_sample, /* freqency table for show. */
- .clk_len = sizeof(mali_dvfs_clk) / sizeof(mali_dvfs_clk[0]),
- .have_switch = 1,
-
- .dvfs_table = mali_dvfs_table, /* DVFS table. */
- .dvfs_table_size = sizeof(mali_dvfs_table) / sizeof(mali_dvfs_threshold_table),
-
- .scale_info = {
- CFG_MIN_PP, /* minpp */
- CFG_PP, /* maxpp, should be same as cfg_pp */
- CFG_MIN_CLOCK, /* minclk */
- CFG_CLOCK, /* maxclk should be same as cfg_clock */
- },
-
- .limit_on = 1,
- .plat_preheat = mali_plat_preheat,
-};
-
-static void mali_plat_preheat(void)
-{
-#ifndef CONFIG_MALI_DVFS
- u32 pre_fs;
- u32 clk, pp;
-
- if (get_mali_schel_mode() != MALI_PP_FS_SCALING)
- return;
-
- get_mali_rt_clkpp(&clk, &pp);
- pre_fs = mali_plat_data.def_clock + 1;
- if (clk < pre_fs)
- clk = pre_fs;
- if (pp < mali_plat_data.sc_mpp)
- pp = mali_plat_data.sc_mpp;
- set_mali_rt_clkpp(clk, pp, 1);
-#endif
-}
-
-mali_plat_info_t* get_mali_plat_data(void) {
- return &mali_plat_data;
-}
-
-int get_mali_freq_level(int freq)
-{
- int i = 0, level = -1;
- int mali_freq_num;
-
- if (freq < 0)
- return level;
- mali_freq_num = mali_plat_data.dvfs_table_size - 1;
- if (freq <= mali_plat_data.clk_sample[0])
- level = mali_freq_num-1;
- if (freq >= mali_plat_data.clk_sample[mali_freq_num - 1])
- level = 0;
- for (i=0; i<mali_freq_num - 1 ;i++) {
- if (freq >= mali_plat_data.clk_sample[i] && freq <= mali_plat_data.clk_sample[i + 1]) {
- level = i;
- level = mali_freq_num-level - 1;
- }
- }
- return level;
-}
-
-unsigned int get_mali_max_level(void)
-{
- return mali_plat_data.dvfs_table_size - 1;
-}
-
-static struct resource mali_gpu_resources[] =
-{
- MALI_GPU_RESOURCES_MALI450_MP2_PMU(IO_MALI_APB_PHY_BASE, INT_MALI_GP, INT_MALI_GP_MMU,
- INT_MALI_PP0, INT_MALI_PP0_MMU,
- INT_MALI_PP1, INT_MALI_PP1_MMU,
- INT_MALI_PP)
-};
-
-static void set_limit_mali_freq(u32 idx)
-{
- if (mali_plat_data.limit_on == 0)
- return;
- if (idx > mali_plat_data.turbo_clock || idx < mali_plat_data.scale_info.minclk)
- return;
- mali_plat_data.scale_info.maxclk= idx;
-
- revise_mali_rt();
-}
-
-static u32 get_limit_mali_freq(void)
-{
- return mali_plat_data.scale_info.maxclk;
-}
-
-static u32 set_limit_pp_num(u32 num)
-{
- u32 ret = -1;
- if (mali_plat_data.limit_on == 0)
- goto quit;
- if (num > mali_plat_data.cfg_pp ||
- num < mali_plat_data.scale_info.minpp)
- goto quit;
- mali_plat_data.scale_info.maxpp = num;
- revise_mali_rt();
- ret = 0;
-quit:
- return ret;
-}
-
-void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data);
-
-#if 0
-struct mali_gpu_clk_item {
- unsigned int clock; /* unit(MHz) */
- unsigned int vol;
-};
-
-struct mali_gpu_clock {
- struct mali_gpu_clk_item *item;
- unsigned int num_of_steps;
-};
-#endif
-
-/* Function that platfrom report it's clock info which driver can set, needed when CONFIG_MALI_DVFS enabled */
-void meson_platform_get_clock_info(struct mali_gpu_clock **data) {
- *data = &meson_gpu_clk_info;
-}
-
-/* Function that get the current clock info, needed when CONFIG_MALI_DVFS enabled */
-int meson_platform_get_freq(void) {
- printk("get cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
- return cur_gpu_clk_index;
-}
-
-/* Fuction that platform callback for freq setting, needed when CONFIG_MALI_DVFS enabled */
-int meson_platform_set_freq(int setting_clock_step) {
-
- if (cur_gpu_clk_index == setting_clock_step) {
- return 0;
- }
-
- mali_clock_set(setting_clock_step);
-
- cur_gpu_clk_index = setting_clock_step;
- printk("set cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
-
- return 0;
-}
-int mali_meson_init_start(struct platform_device* ptr_plt_dev)
-{
- struct mali_gpu_device_data* pdev = ptr_plt_dev->dev.platform_data;
-
-
- /* for resource data. */
- ptr_plt_dev->num_resources = ARRAY_SIZE(mali_gpu_resources);
- ptr_plt_dev->resource = mali_gpu_resources;
-
- /*for dvfs*/
-#ifndef CONFIG_MALI_DVFS
- /* for mali platform data. */
- pdev->control_interval = 200;
- pdev->utilization_callback = mali_gpu_utilization_callback;
-#else
- pdev->get_clock_info = meson_platform_get_clock_info;
- pdev->get_freq = meson_platform_get_freq;
- pdev->set_freq = meson_platform_set_freq;
-#endif
-
- return mali_clock_init(&mali_plat_data);
-}
-
-int mali_meson_init_finish(struct platform_device* ptr_plt_dev)
-{
-#ifndef CONFIG_MALI_DVFS
- if (mali_core_scaling_init(&mali_plat_data) < 0)
- return -1;
-#endif
- return 0;
-}
-
-int mali_meson_uninit(struct platform_device* ptr_plt_dev)
-{
- return 0;
-}
-
-static int mali_cri_light_suspend(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- mali_pm_statue = 1;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_suspend(device);
- }
- mali_pmu_power_down_all(pmu);
- return ret;
-}
-
-static int mali_cri_light_resume(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- mali_pmu_power_up_all(pmu);
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_resume(device);
- }
- mali_pm_statue = 0;
- return ret;
-}
-
-static int mali_cri_deep_suspend(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->suspend(device);
- }
- mali_pmu_power_down_all(pmu);
- return ret;
-}
-
-static int mali_cri_deep_resume(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- mali_pmu_power_up_all(pmu);
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->resume(device);
- }
- return ret;
-
-}
-
-int mali_light_suspend(struct device *device)
-{
- int ret = 0;
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- 0, 0, 0, 0, 0);
-#endif
-
- /* clock scaling. Kasin..*/
- ret = mali_clock_critical(mali_cri_light_suspend, (size_t)device);
- disable_clock();
- return ret;
-}
-
-int mali_light_resume(struct device *device)
-{
- int ret = 0;
- enable_clock();
- ret = mali_clock_critical(mali_cri_light_resume, (size_t)device);
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- get_current_frequency(), 0, 0, 0, 0);
-#endif
- return ret;
-}
-
-int mali_deep_suspend(struct device *device)
-{
- int ret = 0;
- struct mali_pmu_core *pmu;
-
- mali_pm_statue = 1;
- pmu = mali_pmu_get_global_pmu_core();
- enable_clock();
-#ifndef CONFIG_MALI_DVFS
- flush_scaling_job();
-#endif
-
- /* clock scaling off. Kasin... */
- ret = mali_clock_critical(mali_cri_deep_suspend, (size_t)device);
- disable_clock();
- return ret;
-}
-
-int mali_deep_resume(struct device *device)
-{
- int ret = 0;
-
- /* clock scaling up. Kasin.. */
- enable_clock();
- ret = mali_clock_critical(mali_cri_deep_resume, (size_t)device);
- mali_pm_statue = 0;
- return ret;
-}
-
-void mali_post_init(void)
-{
-#ifdef CONFIG_GPU_THERMAL
- int err;
- struct gpufreq_cooling_device *gcdev = NULL;
- struct gpucore_cooling_device *gccdev = NULL;
-
- gcdev = gpufreq_cooling_alloc();
- register_gpu_freq_info(get_current_frequency);
- if (IS_ERR(gcdev))
- printk("malloc gpu cooling buffer error!!\n");
- else if (!gcdev)
- printk("system does not enable thermal driver\n");
- else {
- gcdev->get_gpu_freq_level = get_mali_freq_level;
- gcdev->get_gpu_max_level = get_mali_max_level;
- gcdev->set_gpu_freq_idx = set_limit_mali_freq;
- gcdev->get_gpu_current_max_level = get_limit_mali_freq;
- err = gpufreq_cooling_register(gcdev);
- if (err < 0)
- printk("register GPU cooling error\n");
- printk("gpu cooling register okay with err=%d\n",err);
- }
-
- gccdev = gpucore_cooling_alloc();
- if (IS_ERR(gccdev))
- printk("malloc gpu core cooling buffer error!!\n");
- else if (!gccdev)
- printk("system does not enable thermal driver\n");
- else {
- gccdev->max_gpu_core_num=mali_plat_data.cfg_pp;
- gccdev->set_max_pp_num=set_limit_pp_num;
- err = (int)gpucore_cooling_register(gccdev);
- if (err < 0)
- printk("register GPU cooling error\n");
- printk("gpu core cooling register okay with err=%d\n",err);
- }
-#endif
-}
+++ /dev/null
-/*
- * Copyright (C) 2013 ARM Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
- *
- * A copy of the licence is included with the program, and can also be obtained from Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-/**
- * @file arm_core_scaling.c
- * Example core scaling policy.
- */
-
-#include <linux/version.h>
-#include <linux/module.h>
-#include <linux/workqueue.h>
-#include <linux/mali/mali_utgard.h>
-#include <mali_kernel_common.h>
-#include <mali_osk_profiling.h>
-
-#include <meson_main.h>
-
-#define LOG_MALI_SCALING 0
-
-
-static int currentStep;
-#ifndef CONFIG_MALI_DVFS
-static int num_cores_enabled;
-static int lastStep;
-static struct work_struct wq_work;
-static mali_plat_info_t* pmali_plat = NULL;
-#endif
-static int scaling_mode = MALI_PP_FS_SCALING;
-
-
-static unsigned scaling_dbg_level = 0;
-module_param(scaling_dbg_level, uint, 0644);
-MODULE_PARM_DESC(scaling_dbg_level , "scaling debug level");
-
-#define scalingdbg(level, fmt, arg...) \
- do { \
- if (scaling_dbg_level >= (level)) \
- printk(fmt , ## arg); \
- } while (0)
-
-#ifndef CONFIG_MALI_DVFS
-static void do_scaling(struct work_struct *work)
-{
- mali_dvfs_threshold_table * pdvfs = pmali_plat->dvfs_table;
- int err = mali_perf_set_num_pp_cores(num_cores_enabled);
- scalingdbg(1, "set pp cores to %d\n", num_cores_enabled);
- MALI_DEBUG_ASSERT(0 == err);
- MALI_IGNORE(err);
- if (pdvfs[currentStep].freq_index != pdvfs[lastStep].freq_index) {
- mali_dev_pause();
- mali_clock_set(pdvfs[currentStep].freq_index);
- mali_dev_resume();
- lastStep = currentStep;
- }
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- get_current_frequency(),
- 0, 0, 0, 0);
-#endif
-}
-#endif
-
-u32 revise_set_clk(u32 val, u32 flush)
-{
- u32 ret = 0;
-#ifndef CONFIG_MALI_DVFS
- mali_scale_info_t* pinfo;
-
- pinfo = &pmali_plat->scale_info;
-
- if (val < pinfo->minclk)
- val = pinfo->minclk;
- else if (val > pinfo->maxclk)
- val = pinfo->maxclk;
-
- if (val != currentStep) {
- currentStep = val;
- if (flush)
- schedule_work(&wq_work);
- else
- ret = 1;
- }
-#endif
- return ret;
-}
-
-void get_mali_rt_clkpp(u32* clk, u32* pp)
-{
-#ifndef CONFIG_MALI_DVFS
- *clk = currentStep;
- *pp = num_cores_enabled;
-#endif
-}
-
-u32 set_mali_rt_clkpp(u32 clk, u32 pp, u32 flush)
-{
- u32 ret = 0;
-#ifndef CONFIG_MALI_DVFS
- mali_scale_info_t* pinfo;
- u32 flush_work = 0;
-
- pinfo = &pmali_plat->scale_info;
- if (clk < pinfo->minclk)
- clk = pinfo->minclk;
- else if (clk > pinfo->maxclk)
- clk = pinfo->maxclk;
-
- if (clk != currentStep) {
- currentStep = clk;
- if (flush)
- flush_work++;
- else
- ret = 1;
- }
- if (pp < pinfo->minpp)
- pp = pinfo->minpp;
- else if (pp > pinfo->maxpp)
- pp = pinfo->maxpp;
-
- if (pp != num_cores_enabled) {
- num_cores_enabled = pp;
- if (flush)
- flush_work++;
- else
- ret = 1;
- }
-
- if (flush_work)
- schedule_work(&wq_work);
-#endif
- return ret;
-}
-
-void revise_mali_rt(void)
-{
-#ifndef CONFIG_MALI_DVFS
- set_mali_rt_clkpp(currentStep, num_cores_enabled, 1);
-#endif
-}
-
-void flush_scaling_job(void)
-{
-#ifndef CONFIG_MALI_DVFS
- cancel_work_sync(&wq_work);
-#endif
-}
-
-#ifndef CONFIG_MALI_DVFS
-static u32 enable_one_core(void)
-{
- scalingdbg(2, "meson: one more pp, curent has %d pp cores\n", num_cores_enabled + 1);
- return set_mali_rt_clkpp(currentStep, num_cores_enabled + 1, 0);
-}
-
-static u32 disable_one_core(void)
-{
- scalingdbg(2, "meson: disable one pp, current has %d pp cores\n", num_cores_enabled - 1);
- return set_mali_rt_clkpp(currentStep, num_cores_enabled - 1, 0);
-}
-
-static u32 enable_max_num_cores(void)
-{
- return set_mali_rt_clkpp(currentStep, pmali_plat->scale_info.maxpp, 0);
-}
-
-static u32 enable_pp_cores(u32 val)
-{
- scalingdbg(2, "meson: enable %d pp cores\n", val);
- return set_mali_rt_clkpp(currentStep, val, 0);
-}
-#endif
-
-int mali_core_scaling_init(mali_plat_info_t *mali_plat)
-{
-#ifndef CONFIG_MALI_DVFS
- if (mali_plat == NULL) {
- scalingdbg(2, " Mali platform data is NULL!!!\n");
- return -1;
- }
-
- pmali_plat = mali_plat;
- num_cores_enabled = pmali_plat->sc_mpp;
-
- currentStep = pmali_plat->def_clock;
- lastStep = currentStep;
- INIT_WORK(&wq_work, do_scaling);
-#endif
- return 0;
- /* NOTE: Mali is not fully initialized at this point. */
-}
-
-void mali_core_scaling_term(void)
-{
-#ifndef CONFIG_MALI_DVFS
- flush_scheduled_work();
-#endif
-}
-
-#ifndef CONFIG_MALI_DVFS
-static u32 mali_threshold [] = {
- 102, /* 40% */
- 128, /* 50% */
- 230, /* 90% */
-};
-#endif
-
-void mali_pp_scaling_update(struct mali_gpu_utilization_data *data)
-{
-#ifndef CONFIG_MALI_DVFS
- int ret = 0;
-
- if (mali_threshold[2] < data->utilization_pp)
- ret = enable_max_num_cores();
- else if (mali_threshold[1]< data->utilization_pp)
- ret = enable_one_core();
- else if (0 < data->utilization_pp)
- ret = disable_one_core();
- if (ret == 1)
- schedule_work(&wq_work);
-#endif
-}
-
-#if LOG_MALI_SCALING
-void trace_utilization(struct mali_gpu_utilization_data *data, u32 current_idx, u32 next,
- u32 current_pp, u32 next_pp)
-{
- char direction;
- if (next > current_idx)
- direction = '>';
- else if ((current_idx > pmali_plat->scale_info.minpp) && (next < current_idx))
- direction = '<';
- else
- direction = '~';
-
- scalingdbg(2, "[SCALING]%c (%3d-->%3d)@%3d{%3d - %3d}. pp:(%d-->%d)\n",
- direction,
- get_mali_freq(current_idx),
- get_mali_freq(next),
- data->utilization_gpu,
- pmali_plat->dvfs_table[current_idx].downthreshold,
- pmali_plat->dvfs_table[current_idx].upthreshold,
- current_pp, next_pp);
-}
-#endif
-
-#ifndef CONFIG_MALI_DVFS
-static int mali_stay_count = 0;
-static void mali_decide_next_status(struct mali_gpu_utilization_data *data, int* next_fs_idx,
- int* pp_change_flag)
-{
- u32 utilization, mali_up_limit, decided_fs_idx;
- u32 ld_left, ld_right;
- u32 ld_up, ld_down;
- u32 change_mode;
-
- *pp_change_flag = 0;
- change_mode = 0;
- utilization = data->utilization_gpu;
-
- mali_up_limit = (scaling_mode == MALI_TURBO_MODE) ?
- pmali_plat->turbo_clock : pmali_plat->scale_info.maxclk;
- decided_fs_idx = currentStep;
-
- ld_up = pmali_plat->dvfs_table[currentStep].upthreshold;
- ld_down = pmali_plat->dvfs_table[currentStep].downthreshold;
-
- scalingdbg(2, "utilization=%d, ld_up=%d\n ", utilization, ld_up);
- if (utilization >= ld_up) { /* go up */
-
- scalingdbg(2, "currentStep=%d, mali_up_limit=%d\n ", currentStep, mali_up_limit);
- if (currentStep < mali_up_limit) {
- change_mode = 1;
- if ((currentStep < pmali_plat->def_clock) && (utilization > pmali_plat->bst_gpu))
- decided_fs_idx = pmali_plat->def_clock;
- else
- decided_fs_idx++;
- }
- if ((data->utilization_pp >= ld_up) &&
- (num_cores_enabled < pmali_plat->scale_info.maxpp)) {
- if ((num_cores_enabled < pmali_plat->sc_mpp) && (data->utilization_pp >= pmali_plat->bst_pp)) {
- *pp_change_flag = 1;
- change_mode = 1;
- } else if (change_mode == 0) {
- *pp_change_flag = 2;
- change_mode = 1;
- }
- }
-#if LOG_MALI_SCALING
- scalingdbg(2, "[nexting..] [LD:%d]-> FS[CRNT:%d LMT:%d NEXT:%d] PP[NUM:%d LMT:%d MD:%d][F:%d]\n",
- data->utilization_pp, currentStep, mali_up_limit, decided_fs_idx,
- num_cores_enabled, pmali_plat->scale_info.maxpp, *pp_change_flag, change_mode);
-#endif
- } else if (utilization <= ld_down) { /* go down */
- if (mali_stay_count > 0) {
- *next_fs_idx = decided_fs_idx;
- mali_stay_count--;
- return;
- }
-
- if (num_cores_enabled > pmali_plat->sc_mpp) {
- change_mode = 1;
- if (data->utilization_pp <= ld_down) {
- ld_left = data->utilization_pp * num_cores_enabled;
- ld_right = (pmali_plat->dvfs_table[currentStep].upthreshold) *
- (num_cores_enabled - 1);
- if (ld_left < ld_right) {
- change_mode = 2;
- }
- }
- } else if (currentStep > pmali_plat->scale_info.minclk) {
- change_mode = 1;
- } else if (num_cores_enabled > 1) { /* decrease PPS */
- if (data->utilization_pp <= ld_down) {
- ld_left = data->utilization_pp * num_cores_enabled;
- ld_right = (pmali_plat->dvfs_table[currentStep].upthreshold) *
- (num_cores_enabled - 1);
- scalingdbg(2, "ld_left=%d, ld_right=%d\n", ld_left, ld_right);
- if (ld_left < ld_right) {
- change_mode = 2;
- }
- }
- }
-
- if (change_mode == 1) {
- decided_fs_idx--;
- } else if (change_mode == 2) { /* decrease PPS */
- *pp_change_flag = -1;
- }
- }
- if (change_mode)
- mali_stay_count = pmali_plat->dvfs_table[decided_fs_idx].keep_count;
- *next_fs_idx = decided_fs_idx;
-}
-#endif
-
-void mali_pp_fs_scaling_update(struct mali_gpu_utilization_data *data)
-{
-#ifndef CONFIG_MALI_DVFS
- int ret = 0;
- int pp_change_flag = 0;
- u32 next_idx = 0;
-
-#if LOG_MALI_SCALING
- u32 last_pp = num_cores_enabled;
-#endif
- mali_decide_next_status(data, &next_idx, &pp_change_flag);
-
- if (pp_change_flag == 1)
- ret = enable_pp_cores(pmali_plat->sc_mpp);
- else if (pp_change_flag == 2)
- ret = enable_one_core();
- else if (pp_change_flag == -1) {
- ret = disable_one_core();
- }
-
-#if LOG_MALI_SCALING
- if (pp_change_flag || (next_idx != currentStep))
- trace_utilization(data, currentStep, next_idx, last_pp, num_cores_enabled);
-#endif
-
- if (next_idx != currentStep) {
- ret = 1;
- currentStep = next_idx;
- }
-
- if (ret == 1)
- schedule_work(&wq_work);
-#ifdef CONFIG_MALI400_PROFILING
- else
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- get_current_frequency(),
- 0, 0, 0, 0);
-#endif
-#endif
-}
-
-u32 get_mali_schel_mode(void)
-{
- return scaling_mode;
-}
-
-void set_mali_schel_mode(u32 mode)
-{
-#ifndef CONFIG_MALI_DVFS
- MALI_DEBUG_ASSERT(mode < MALI_SCALING_MODE_MAX);
- if (mode >= MALI_SCALING_MODE_MAX)
- return;
- scaling_mode = mode;
-
- /* set default performance range. */
- pmali_plat->scale_info.minclk = pmali_plat->cfg_min_clock;
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- pmali_plat->scale_info.minpp = pmali_plat->cfg_min_pp;
- pmali_plat->scale_info.maxpp = pmali_plat->cfg_pp;
-
- /* set current status and tune max freq */
- if (scaling_mode == MALI_PP_FS_SCALING) {
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- enable_pp_cores(pmali_plat->sc_mpp);
- } else if (scaling_mode == MALI_SCALING_DISABLE) {
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- enable_max_num_cores();
- } else if (scaling_mode == MALI_TURBO_MODE) {
- pmali_plat->scale_info.maxclk = pmali_plat->turbo_clock;
- enable_max_num_cores();
- }
- currentStep = pmali_plat->scale_info.maxclk;
- schedule_work(&wq_work);
-#endif
-}
-
-u32 get_current_frequency(void)
-{
- return get_mali_freq(currentStep);
-}
-
-void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data)
-{
-#ifndef CONFIG_MALI_DVFS
- if (mali_pm_statue)
- return;
-
- switch (scaling_mode) {
- case MALI_PP_FS_SCALING:
- mali_pp_fs_scaling_update(data);
- break;
- case MALI_PP_SCALING:
- mali_pp_scaling_update(data);
- break;
- default:
- break;
- }
-#endif
-}
-
-void mali_dev_restore(void)
-{
-#ifndef CONFIG_MALI_DVFS
- mali_dvfs_threshold_table * pdvfs = pmali_plat->dvfs_table;
-
- //mali_perf_set_num_pp_cores(num_cores_enabled);
- mali_clock_set(pdvfs[currentStep].freq_index);
-#endif
-}
+++ /dev/null
-/*
- * Copyright (C) 2010, 2012-2013 ARM Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
- *
- * A copy of the licence is included with the program, and can also be obtained from Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-#include <linux/version.h>
-#include <linux/dma-mapping.h>
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/ioport.h>
-#include <linux/slab.h>
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#endif
-#include <asm/io.h>
-
-#include "meson_main.h"
-#include <linux/mali/mali_utgard.h>
-#include "mali_kernel_common.h"
-#include "common/mali_pmu.h"
-#include "common/mali_osk_profiling.h"
-
-int mali_pm_statue = 0;
-u32 mali_gp_reset_fail = 0;
-module_param(mali_gp_reset_fail, int, S_IRUSR | S_IWUSR | S_IWGRP | S_IRGRP | S_IROTH); /* rw-rw-r-- */
-MODULE_PARM_DESC(mali_gp_reset_fail, "times of failed to reset GP");
-u32 mali_core_timeout = 0;
-module_param(mali_core_timeout, int, S_IRUSR | S_IWUSR | S_IWGRP | S_IRGRP | S_IROTH); /* rw-rw-r-- */
-MODULE_PARM_DESC(mali_core_timeout, "times of failed to reset GP");
-
-static struct mali_gpu_device_data mali_gpu_data =
-{
- .shared_mem_size = 1024 * 1024 * 1024,
- .max_job_runtime = 60000, /* 60 seconds */
- .pmu_switch_delay = 0xFFFF, /* do not have to be this high on FPGA, but it is good for testing to have a delay */
-#if defined(CONFIG_ARCH_MESON8B)||defined(CONFIG_ARCH_MESONG9BB)
- .pmu_domain_config = {0x1, 0x2, 0x4, 0x0,
- 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x1, 0x2, 0x0},
-#else
- .pmu_domain_config = {0x1, 0x2, 0x4, 0x4,
- 0x0, 0x8, 0x8, 0x8,
- 0x0, 0x1, 0x2, 0x8},
-#endif
-};
-
-static void mali_platform_device_release(struct device *device);
-static struct platform_device mali_gpu_device =
-{
- .name = MALI_GPU_NAME_UTGARD,
- .id = 0,
- .dev.release = mali_platform_device_release,
- .dev.coherent_dma_mask = DMA_BIT_MASK(32),
- .dev.platform_data = &mali_gpu_data,
- .dev.type = &mali_pm_device, /* We should probably use the pm_domain instead of type on newer kernels */
-};
-
-int mali_pdev_pre_init(struct platform_device* ptr_plt_dev)
-{
- MALI_DEBUG_PRINT(4, ("mali_platform_device_register() called\n"));
- if (mali_gpu_data.shared_mem_size < 10) {
- MALI_DEBUG_PRINT(2, ("mali os memory didn't configered, set to default(512M)\n"));
- mali_gpu_data.shared_mem_size = 1024 * 1024 *1024;
- }
- return mali_meson_init_start(ptr_plt_dev);
-}
-
-void mali_pdev_post_init(struct platform_device* pdev)
-{
- mali_gp_reset_fail = 0;
- mali_core_timeout = 0;
-#ifdef CONFIG_PM_RUNTIME
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
- pm_runtime_set_autosuspend_delay(&(pdev->dev), 1000);
- pm_runtime_use_autosuspend(&(pdev->dev));
-#endif
- pm_runtime_enable(&(pdev->dev));
-#endif
- mali_meson_init_finish(pdev);
-}
-
-int mali_pdev_dts_init(struct platform_device* mali_gpu_device)
-{
- struct device_node *cfg_node = mali_gpu_device->dev.of_node;
- struct device_node *child;
- u32 prop_value;
- int err;
-
- for_each_child_of_node(cfg_node, child) {
- err = of_property_read_u32(child, "shared_memory", &prop_value);
- if (err == 0) {
- MALI_DEBUG_PRINT(2, ("shared_memory configurate %d\n", prop_value));
- mali_gpu_data.shared_mem_size = prop_value * 1024 * 1024;
- }
- }
-
- err = mali_pdev_pre_init(mali_gpu_device);
- if (err == 0)
- mali_pdev_post_init(mali_gpu_device);
- return err;
-}
-
-int mali_platform_device_register(void)
-{
- int err = -1;
- err = mali_pdev_pre_init(&mali_gpu_device);
- if (err == 0) {
- err = platform_device_register(&mali_gpu_device);
- if (0 == err)
- mali_pdev_post_init(&mali_gpu_device);
- }
- return err;
-}
-
-void mali_platform_device_unregister(void)
-{
- MALI_DEBUG_PRINT(4, ("mali_platform_device_unregister() called\n"));
- mali_core_scaling_term();
- platform_device_unregister(&mali_gpu_device);
- platform_device_put(&mali_gpu_device);
-}
-
-static void mali_platform_device_release(struct device *device)
-{
- MALI_DEBUG_PRINT(4, ("mali_platform_device_release() called\n"));
-}
-
-
+++ /dev/null
-/*
- * mali_platform.h
- *
- * Created on: Nov 8, 2013
- * Author: amlogic
- */
-
-#ifndef MESON_MAIN_H_
-#define MESON_MAIN_H_
-#include <linux/version.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#ifdef CONFIG_PM_RUNTIME
-#include <linux/pm_runtime.h>
-#endif
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/cpu.h>
-#endif
-
-#include "mali_scaling.h"
-#include "mali_clock.h"
-
-extern struct device_type mali_pm_device;
-extern int mali_pm_statue;
-
-u32 set_max_mali_freq(u32 idx);
-u32 get_max_mali_freq(void);
-
-int mali_meson_init_start(struct platform_device* ptr_plt_dev);
-int mali_meson_init_finish(struct platform_device* ptr_plt_dev);
-int mali_meson_uninit(struct platform_device* ptr_plt_dev);
-int mali_light_suspend(struct device *device);
-int mali_light_resume(struct device *device);
-int mali_deep_suspend(struct device *device);
-int mali_deep_resume(struct device *device);
-
-#endif /* MESON_MAIN_H_ */
+++ /dev/null
-/*******************************************************************
- *
- * Copyright C 2013 by Amlogic, Inc. All Rights Reserved.
- *
- * Description:
- *
- * Author: Amlogic Software
- * Created: 2010/4/1 19:46
- *
- *******************************************************************/
-/* Standard Linux headers */
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/string.h>
-#include <linux/slab.h>
-#include <linux/list.h>
-
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/io.h>
-#include <plat/io.h>
-#include <asm/io.h>
-#endif
-
-#include <linux/mali/mali_utgard.h>
-#include <common/mali_kernel_common.h>
-#include <common/mali_pmu.h>
-#include "mali_pp_scheduler.h"
-#include "meson_main.h"
-
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
-static ssize_t domain_stat_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
-#if 0
- unsigned int val;
-
- val = readl((u32 *)(IO_AOBUS_BASE + 0xf0)) & 0xff;
- return sprintf(buf, "%x\n", val>>4);
-#else
- return 0;
-#endif
-}
-
-#define PREHEAT_CMD "preheat"
-#define PLL2_CMD "mpl2" /* mpl2 [11] or [0xxxxxxx] */
-#define SCMPP_CMD "scmpp" /* scmpp [number of pp your want in most of time]. */
-#define BSTGPU_CMD "bstgpu" /* bstgpu [0-256] */
-#define BSTPP_CMD "bstpp" /* bstpp [0-256] */
-#define LIMIT_CMD "lmt" /* lmt [0 or 1] */
-#define MAX_TOKEN 20
-#define FULL_UTILIZATION 256
-
-static ssize_t mpgpu_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- char *pstart, *cprt = NULL;
- u32 val = 0;
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
-
- cprt = skip_spaces(buf);
- pstart = strsep(&cprt," ");
- if (strlen(pstart) < 1)
- goto quit;
-
- if(!strncmp(pstart, PREHEAT_CMD, MAX_TOKEN)) {
- if (pmali_plat->plat_preheat) {
- pmali_plat->plat_preheat();
- }
- } else if (!strncmp(pstart, PLL2_CMD, MAX_TOKEN)) {
- int base = 10;
- if ((strlen(cprt) > 2) && (cprt[0] == '0') &&
- (cprt[1] == 'x' || cprt[1] == 'X'))
- base = 16;
- if (kstrtouint(cprt, base, &val) <0)
- goto quit;
- if (val < 11)
- pmali_plat->cfg_clock = pmali_plat->cfg_clock_bkup;
- else
- pmali_plat->cfg_clock = pmali_plat->turbo_clock;
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- set_str_src(val);
- } else if (!strncmp(pstart, SCMPP_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
- if ((val > 0) && (val < pmali_plat->cfg_pp)) {
- pmali_plat->sc_mpp = val;
- }
- } else if (!strncmp(pstart, BSTGPU_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
- if ((val > 0) && (val < FULL_UTILIZATION)) {
- pmali_plat->bst_gpu = val;
- }
- } else if (!strncmp(pstart, BSTPP_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
- if ((val > 0) && (val < FULL_UTILIZATION)) {
- pmali_plat->bst_pp = val;
- }
- } else if (!strncmp(pstart, LIMIT_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
-
- if (val < 2) {
- pmali_plat->limit_on = val;
- if (val == 0) {
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- pmali_plat->scale_info.maxpp = pmali_plat->cfg_pp;
- revise_mali_rt();
- }
- }
- }
-quit:
- return count;
-}
-
-static ssize_t scale_mode_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- return sprintf(buf, "%d\n", get_mali_schel_mode());
-}
-
-static ssize_t scale_mode_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
-
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- {
- return -EINVAL;
- }
-
- set_mali_schel_mode(val);
-
- return count;
-}
-
-static ssize_t max_pp_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- printk("maxpp:%d, maxpp_sysfs:%d, total=%d\n",
- pmali_plat->scale_info.maxpp, pmali_plat->maxpp_sysfs,
- mali_pp_scheduler_get_num_cores_total());
- return sprintf(buf, "%d\n", mali_pp_scheduler_get_num_cores_total());
-}
-
-static ssize_t max_pp_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pmali_plat->cfg_pp) || (val < pinfo->minpp))
- return -EINVAL;
-
- pmali_plat->maxpp_sysfs = val;
- pinfo->maxpp = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t min_pp_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- return sprintf(buf, "%d\n", pmali_plat->scale_info.minpp);
-}
-
-static ssize_t min_pp_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pinfo->maxpp) || (val < 1))
- return -EINVAL;
-
- pinfo->minpp = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t max_freq_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- printk("maxclk:%d, maxclk_sys:%d, max gpu level=%d\n",
- pmali_plat->scale_info.maxclk, pmali_plat->maxclk_sysfs, get_gpu_max_clk_level());
- return sprintf(buf, "%d\n", get_gpu_max_clk_level());
-}
-
-static ssize_t max_freq_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pmali_plat->cfg_clock) || (val < pinfo->minclk))
- return -EINVAL;
-
- pmali_plat->maxclk_sysfs = val;
- pinfo->maxclk = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t min_freq_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- return sprintf(buf, "%d\n", pmali_plat->scale_info.minclk);
-}
-
-static ssize_t min_freq_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pinfo->maxclk))
- return -EINVAL;
-
- pinfo->minclk = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t freq_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- return sprintf(buf, "%d\n", get_current_frequency());
-}
-
-static ssize_t freq_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- u32 clk, pp;
- get_mali_rt_clkpp(&clk, &pp);
-
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- return -EINVAL;
-
- set_mali_rt_clkpp(val, pp, 1);
-
- return count;
-}
-
-static ssize_t current_pp_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- u32 clk, pp;
- get_mali_rt_clkpp(&clk, &pp);
- return sprintf(buf, "%d\n", pp);
-}
-
-static ssize_t current_pp_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- u32 clk, pp;
-
- get_mali_rt_clkpp(&clk, &pp);
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- {
- return -EINVAL;
- }
-
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- return -EINVAL;
-
- set_mali_rt_clkpp(clk, val, 1);
-
- return count;
-}
-
-static struct class_attribute mali_class_attrs[] = {
- __ATTR(domain_stat, 0644, domain_stat_read, NULL),
- __ATTR(mpgpucmd, 0644, NULL, mpgpu_write),
- __ATTR(scale_mode, 0644, scale_mode_read, scale_mode_write),
- __ATTR(min_freq, 0644, min_freq_read, min_freq_write),
- __ATTR(max_freq, 0644, max_freq_read, max_freq_write),
- __ATTR(min_pp, 0644, min_pp_read, min_pp_write),
- __ATTR(max_pp, 0644, max_pp_read, max_pp_write),
- __ATTR(cur_freq, 0644, freq_read, freq_write),
- __ATTR(cur_pp, 0644, current_pp_read, current_pp_write),
-};
-
-static struct class mpgpu_class = {
- .name = "mpgpu",
-};
-#endif
-
-int mpgpu_class_init(void)
-{
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
- int ret = 0;
- int i;
- int attr_num = ARRAY_SIZE(mali_class_attrs);
-
- ret = class_register(&mpgpu_class);
- if (ret) {
- printk(KERN_ERR "%s: class_register failed\n", __func__);
- return ret;
- }
- for (i = 0; i< attr_num; i++) {
- ret = class_create_file(&mpgpu_class, &mali_class_attrs[i]);
- if (ret) {
- printk(KERN_ERR "%d ST: class item failed to register\n", i);
- }
- }
- return ret;
-#else
- return 0;
-#endif
-}
-
-void mpgpu_class_exit(void)
-{
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
- class_unregister(&mpgpu_class);
-#endif
-}
-
#
# This file is called by the Linux build system.
-include $(src)/Kbuild.amlogic
-# set up defaults if not defined by the user
-TIMESTAMP ?= default
-ifeq ($(CONFIG_UMP), m)
- USING_UMP ?= 1
-else
- USING_UMP ?= 0
-endif
-ifneq ($(KBUILD_SRC),)
- ifneq ($(wildcard $(KBUILD_SRC)/$(src)),)
- TOP_KBUILD_SRC := $(KBUILD_SRC)/
- endif
-endif
+# set up defaults if not defined by the user
+include $(src)/platform/Kbuild.amlogic
+TIMESTAMP ?= default
OS_MEMORY_KERNEL_BUFFER_SIZE_IN_MB ?= 16
-
-#USING_GPU_UTILIZATION ?= 0
-#PROFILING_SKIP_PP_JOBS ?= 0
-#PROFILING_SKIP_PP_AND_GP_JOBS ?= 0
-ifeq ($(CONFIG_MALI_DVFS),y)
- ccflags-y += -DCONFIG_MALI_DVFS
- USING_GPU_UTILIZATION=0
- USING_DVFS=1
-else
- USING_GPU_UTILIZATION=1
- USING_DVFS=0
-endif
+USING_GPU_UTILIZATION ?= 0
PROFILING_SKIP_PP_JOBS ?= 0
PROFILING_SKIP_PP_AND_GP_JOBS ?= 0
-############## Kasin Added, for platform. ################
-
-ifeq ($(CONFIG_MALI400_DEBUG),y)
- BUILD ?= debug
-else
- BUILD ?= release
- ldflags-y += --strip-debug
-
-endif
-##################### end Kasin Added. ###################
-
MALI_PP_SCHEDULER_FORCE_NO_JOB_OVERLAP ?= 0
MALI_PP_SCHEDULER_KEEP_SUB_JOB_STARTS_ALIGNED ?= 0
MALI_PP_SCHEDULER_FORCE_NO_JOB_OVERLAP_BETWEEN_APPS ?= 0
MALI_UPPER_HALF_SCHEDULING ?= 1
-
-############## Kasin Added, useless now. ################
-# Get path to driver source from Linux build system
-DRIVER_DIR=$(src)
-##################### end Kasin Added. ###################
-
MALI_ENABLE_CPU_CYCLES ?= 0
# For customer releases the Linux Device Drivers will be provided as ARM proprietary and GPL releases:
# The ARM proprietary product will only include the license/proprietary directory
# The GPL product will only include the license/gpl directory
-ifeq ($(wildcard $(TOP_KBUILD_SRC)$(DRIVER_DIR)/linux/license/gpl/*),)
- ccflags-y += -I$(TOP_KBUILD_SRC)$(DRIVER_DIR)/linux/license/proprietary
+ifeq ($(wildcard $(src)/linux/license/gpl/*),)
+ ccflags-y += -I$(src)/linux/license/proprietary
ifeq ($(CONFIG_MALI400_PROFILING),y)
$(error Profiling is incompatible with non-GPL license)
endif
endif
$(error Linux Device integration is incompatible with non-GPL license)
else
- ccflags-y += -I$(TOP_KBUILD_SRC)$(DRIVER_DIR)/linux/license/gpl
+ ccflags-y += -I$(src)/linux/license/gpl
endif
ifeq ($(USING_GPU_UTILIZATION), 1)
linux/mali_pmu_power_up_down.o \
__malidrv_build_info.o
-############## Kasin Added, for platform. ################
-ifeq (true,false)
-mali-y += \
- platform/meson_main.o \
- platform/mali_pm_device.o \
- platform/mali_clock.o \
- platform/mpgpu.o
-else
-mali-y += \
- platform/mali_pm_device.o \
- platform/meson_bu/meson_main2.o \
- platform/meson_bu/mali_clock.o \
- platform/meson_bu/mpgpu.o \
- platform/meson_bu/platform_gx.o
-endif
-ifeq ($(CONFIG_MALI_DVFS),y)
- mali-y += platform/meson_bu/mali_dvfs.o
-else
- mali-y += platform/meson_bu/scaling.o
-endif
-
-ifeq ($(TARGET_PLATFORM),meson_m400)
-MALI_PLATFORM_FILES:= \
- platform/meson_m400/mali_fix.o \
- platform/meson_m400/mali_platform.o \
- platform/meson_m400/platform_mx.o
-endif
-
-ifeq ($(TARGET_PLATFORM),meson_m450)
-ccflags-y += -DCONFIG_MALI450=y
-mali-y += \
- platform/meson_m450/scaling.o
-
-mali-$(CONFIG_ARCH_MESON) += \
- platform/meson_m450/platform_m8.o
-
-mali-$(CONFIG_ARCH_MESON8) += \
- platform/meson_m450/platform_m8.o
-
-mali-$(CONFIG_ARCH_MESON6TVD) += \
- platform/meson_m450/platform_m6tvd.o
-
-mali-$(CONFIG_ARCH_MESON8B) += \
- platform/meson_m450/platform_m8b.o
-
-mali-$(CONFIG_ARCH_MESONG9TV) += \
- platform/meson_m450/platform_m8.o
-
-mali-$(CONFIG_ARCH_MESONG9BB) += \
- platform/meson_m450/platform_m8b.o
-endif
-##################### end Kasin Added. ###################
-
ifneq ($(wildcard $(src)/linux/mali_slp_global_lock.c),)
mali-y += linux/mali_slp_global_lock.o
endif
mali-$(CONFIG_DMA_SHARED_BUFFER) += linux/mali_memory_dma_buf.o
mali-$(CONFIG_DMA_SHARED_BUFFER) += linux/mali_memory_secure.o
mali-$(CONFIG_SYNC) += linux/mali_sync.o
+mali-$(CONFIG_MALI_DMA_BUF_FENCE) += linux/mali_dma_fence.o
ccflags-$(CONFIG_SYNC) += -Idrivers/staging/android
mali-$(CONFIG_MALI400_UMP) += linux/mali_memory_ump.o
ccflags-y += -DMALI_OS_MEMORY_KERNEL_BUFFER_SIZE_IN_MB=$(OS_MEMORY_KERNEL_BUFFER_SIZE_IN_MB)
ccflags-y += -DUSING_GPU_UTILIZATION=$(USING_GPU_UTILIZATION)
ccflags-y += -DMALI_ENABLE_CPU_CYCLES=$(MALI_ENABLE_CPU_CYCLES)
-ccflags-y += -DMALI_FAKE_PLATFORM_DEVICE
ifeq ($(MALI_UPPER_HALF_SCHEDULING),1)
ccflags-y += -DMALI_UPPER_HALF_SCHEDULING
ifeq ($(MALI_PLATFORM_FILES),)
ccflags-$(CONFIG_MALI400_UMP) += -I$(src)/../ump/include/
else
-ccflags-$(CONFIG_MALI400_UMP) += -I$(src)/../ump/include/ump
-ccflags-$(CONFIG_MALI400_DEBUG) += -DDEBUG
+ccflags-$(CONFIG_MALI400_UMP) += -I$(src)/../../ump/include/ump
endif
+ccflags-$(CONFIG_MALI400_DEBUG) += -DDEBUG
# Use our defines when compiling
ccflags-y += -I$(src) -I$(src)/include -I$(src)/common -I$(src)/linux -I$(src)/platform
# Get subversion revision number, fall back to only ${MALI_RELEASE_NAME} if no svn info is available
-MALI_RELEASE_NAME=$(shell cat $(TOP_KBUILD_SRC)$(DRIVER_DIR)/.version 2> /dev/null)
+MALI_RELEASE_NAME=$(shell cat $(src)/.version 2> /dev/null)
-SVN_INFO = (cd $(TOP_KBUILD_SRC)$(DRIVER_DIR); svn info 2>/dev/null)
+SVN_INFO = (cd $(src); svn info 2>/dev/null)
ifneq ($(shell $(SVN_INFO) 2>/dev/null),)
# SVN detected
REPO_URL := $(shell $(SVN_INFO) | grep '^URL: ' | cut -d: -f2- | cut -b2-)
else # SVN
-GIT_REV := $(shell cd $(TOP_KBUILD_SRC)$(DRIVER_DIR); git describe --always 2>/dev/null)
+GIT_REV := $(shell cd $(src); git describe --always 2>/dev/null)
ifneq ($(GIT_REV),)
# Git detected
DRIVER_REV := $(MALI_RELEASE_NAME)-$(GIT_REV)
-CHANGE_DATE := $(shell cd $(TOP_KBUILD_SRC)$(DRIVER_DIR); git log -1 --format="%ci")
+CHANGE_DATE := $(shell cd $(src); git log -1 --format="%ci")
CHANGED_REVISION := $(GIT_REV)
-REPO_URL := $(shell cd $(TOP_KBUILD_SRC)$(DRIVER_DIR); git describe --all --always 2>/dev/null)
+REPO_URL := $(shell cd $(src); git describe --all --always 2>/dev/null)
else # Git
# No Git or SVN detected
ccflags-y += -DSVN_REV_STRING=\"$(DRIVER_REV)\"
VERSION_STRINGS :=
-VERSION_STRINGS += API_VERSION=$(shell cd $(TOP_KBUILD_SRC)$(DRIVER_DIR); grep "\#define _MALI_API_VERSION" $(FILES_PREFIX)include/linux/mali/mali_utgard_uk_types.h | cut -d' ' -f 3 )
+VERSION_STRINGS += API_VERSION=$(shell cd $(src); grep "\#define _MALI_API_VERSION" $(FILES_PREFIX)include/linux/mali/mali_utgard_uk_types.h | cut -d' ' -f 3 )
VERSION_STRINGS += REPO_URL=$(REPO_URL)
VERSION_STRINGS += REVISION=$(DRIVER_REV)
VERSION_STRINGS += CHANGED_REVISION=$(CHANGED_REVISION)
VERSION_STRINGS += USING_INTERNAL_PROFILING=$(CONFIG_MALI400_INTERNAL_PROFILING)
VERSION_STRINGS += USING_GPU_UTILIZATION=$(USING_GPU_UTILIZATION)
VERSION_STRINGS += USING_DVFS=$(CONFIG_MALI_DVFS)
+VERSION_STRINGS += USING_DMA_BUF_FENCE = $(CONFIG_MALI_DMA_BUF_FENCE)
VERSION_STRINGS += MALI_UPPER_HALF_SCHEDULING=$(MALI_UPPER_HALF_SCHEDULING)
# Create file with Mali driver configuration
-$(TOP_KBUILD_SRC)$(DRIVER_DIR)/__malidrv_build_info.c:
- @echo 'const char *__malidrv_build_info(void) { return "malidrv: $(VERSION_STRINGS)";}' > $(TOP_KBUILD_SRC)$(DRIVER_DIR)/__malidrv_build_info.c
+$(src)/__malidrv_build_info.c:
+ @echo 'const char *__malidrv_build_info(void) { return "malidrv: $(VERSION_STRINGS)";}' > $(src)/__malidrv_build_info.c
+++ /dev/null
-############## Kasin Added, for platform. ################
-
-ifndef CONFIG_MALI_DMA_BUF_MAP_ON_ATTACH
- ccflags-y += -DCONFIG_MALI_DMA_BUF_MAP_ON_ATTACH=y
-endif
-
-ccflags-y += -DCONFIG_MALI_DT=y
-ccflags-y += -DMESON_CPU_TYPE=0x80
-ccflags-y += -DMESON_CPU_TYPE_MESON6=0x60
-ccflags-y += -DMESON_CPU_TYPE_MESON6TVD=0x75
-ccflags-y += -DMESON_CPU_TYPE_MESON8=0x80
-ccflags-y += -DMESON_CPU_TYPE_MESON8B=0x8B
-
-USE_GPPLL?=0
-ifdef CONFIG_AM_VIDEO
- USE_GPPLL:=1
-endif
-
-ccflags-y += -DAMLOGIC_GPU_USE_GPPLL=$(USE_GPPLL)
+++ /dev/null
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#include <plat/io.h>
-#endif
-
-#include <linux/io.h>
-
-#include <asm/io.h>
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 29))
-#include <linux/amlogic/iomap.h>
-#endif
-#include "meson_main.h"
-
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6TVD
-
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 29))
-#define HHI_MALI_CLK_CNTL 0x106C
-#define mplt_read(r) aml_read_cbus((r))
-#define mplt_write(v, r) aml_write_cbus((r), (v))
-#define mplt_setbits(r, m) aml_write_cbus((r), (aml_read_cbus(r) | (m)));
-#define mplt_clrbits(r, m) aml_write_cbus((r), (aml_read_cbus(r) & (~(m))));
-#else
-#define mplt_read(r) aml_read_reg32((P_##r))
-#define mplt_write(v, r) aml_write_reg32((P_##r), (v))
-#define mplt_setbits(r, m) aml_write_reg32((P_##r), (aml_read_reg32(P_##r) | (m)));
-#define mplt_clrbits(r, m) aml_write_reg32((P_##r), (aml_read_reg32(P_##r) & (~(m))));
-#endif
-#define FCLK_MPLL2 (2 << 9)
-static DEFINE_SPINLOCK(lock);
-static mali_plat_info_t* pmali_plat = NULL;
-static u32 mali_extr_backup = 0;
-static u32 mali_extr_sample_backup = 0;
-
-int mali_clock_init(mali_plat_info_t* mali_plat)
-{
- u32 def_clk_data;
- if (mali_plat == NULL) {
- printk(" Mali platform data is NULL!!!\n");
- return -1;
- }
-
- pmali_plat = mali_plat;
- if (pmali_plat->have_switch) {
- def_clk_data = pmali_plat->clk[pmali_plat->def_clock];
- mplt_write(def_clk_data | (def_clk_data << 16), HHI_MALI_CLK_CNTL);
- mplt_setbits(HHI_MALI_CLK_CNTL, 1 << 24);
- mplt_setbits(HHI_MALI_CLK_CNTL, 1 << 8);
- } else {
- mali_clock_set(pmali_plat->def_clock);
- }
-
- mali_extr_backup = pmali_plat->clk[pmali_plat->clk_len - 1];
- mali_extr_sample_backup = pmali_plat->clk_sample[pmali_plat->clk_len - 1];
- return 0;
-}
-
-int mali_clock_critical(critical_t critical, size_t param)
-{
- int ret = 0;
- unsigned long flags;
-
- spin_lock_irqsave(&lock, flags);
- ret = critical(param);
- spin_unlock_irqrestore(&lock, flags);
- return ret;
-}
-
-static int critical_clock_set(size_t param)
-{
- unsigned int idx = param;
- if (pmali_plat->have_switch) {
- u32 clk_value;
- mplt_setbits(HHI_MALI_CLK_CNTL, 1 << 31);
- clk_value = mplt_read(HHI_MALI_CLK_CNTL) & 0xffff0000;
- clk_value = clk_value | pmali_plat->clk[idx] | (1 << 8);
- mplt_write(clk_value, HHI_MALI_CLK_CNTL);
- mplt_clrbits(HHI_MALI_CLK_CNTL, 1 << 31);
- } else {
- mplt_clrbits(HHI_MALI_CLK_CNTL, 1 << 8);
- mplt_clrbits(HHI_MALI_CLK_CNTL, (0x7F | (0x7 << 9)));
- mplt_write(pmali_plat->clk[idx], HHI_MALI_CLK_CNTL);
- mplt_setbits(HHI_MALI_CLK_CNTL, 1 << 8);
- }
- return 0;
-}
-
-int mali_clock_set(unsigned int clock)
-{
- return mali_clock_critical(critical_clock_set, (size_t)clock);
-}
-
-void disable_clock(void)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&lock, flags);
- mplt_clrbits(HHI_MALI_CLK_CNTL, 1 << 8);
- spin_unlock_irqrestore(&lock, flags);
-}
-
-void enable_clock(void)
-{
- u32 ret;
- unsigned long flags;
-
- spin_lock_irqsave(&lock, flags);
- mplt_setbits(HHI_MALI_CLK_CNTL, 1 << 8);
- ret = mplt_read(HHI_MALI_CLK_CNTL) & (1 << 8);
- spin_unlock_irqrestore(&lock, flags);
-}
-
-u32 get_mali_freq(u32 idx)
-{
- if (!mali_pm_statue) {
- return pmali_plat->clk_sample[idx];
- } else {
- return 0;
- }
-}
-
-void set_str_src(u32 data)
-{
-#if 0
- if (data == 11) {
- writel(0x0004d000, (u32*)P_HHI_MPLL_CNTL9);
- } else if (data > 11) {
- writel(data, (u32*)P_HHI_MPLL_CNTL9);
- }
-#endif
- if (data == 0) {
- pmali_plat->clk[pmali_plat->clk_len - 1] = mali_extr_backup;
- pmali_plat->clk_sample[pmali_plat->clk_len - 1] = mali_extr_sample_backup;
- } else if (data > 10) {
- pmali_plat->clk_sample[pmali_plat->clk_len - 1] = 600;
- pmali_plat->clk[pmali_plat->clk_len - 1] = FCLK_MPLL2;
- }
-}
-#endif
+++ /dev/null
-#ifndef _MALI_CLOCK_H_
-#define _MALI_CLOCK_H_
-
-typedef int (*critical_t)(size_t param);
-int mali_clock_critical(critical_t critical, size_t param);
-
-int mali_clock_init(mali_plat_info_t*);
-int mali_clock_set(unsigned int index);
-void disable_clock(void);
-void enable_clock(void);
-u32 get_mali_freq(u32 idx);
-void set_str_src(u32 data);
-#endif /* _MALI_CLOCK_H_ */
+++ /dev/null
-/*
- * mali_platform.h
- *
- * Created on: Nov 8, 2013
- * Author: amlogic
- */
-
-#include <linux/kernel.h>
-#ifndef MALI_PLATFORM_H_
-#define MALI_PLATFORM_H_
-
-extern u32 mali_gp_reset_fail;
-extern u32 mali_core_timeout;
-
-#endif /* MALI_PLATFORM_H_ */
+++ /dev/null
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/module.h> /* kernel module definitions */
-#include <linux/ioport.h> /* request_mem_region */
-#include <linux/slab.h>
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#endif
-#include "meson_main.h"
-#include <common/mali_kernel_common.h>
-#include <common/mali_osk_profiling.h>
-#include <common/mali_pmu.h>
-#include <linux/mali/mali_utgard.h>
-
-static int mali_os_suspend(struct device *device)
-{
- int ret = 0;
-
- MALI_DEBUG_PRINT(4, ("mali_os_suspend() called\n"));
- ret = mali_deep_suspend(device);
-
- return ret;
-}
-
-static int mali_os_resume(struct device *device)
-{
- int ret = 0;
-
- MALI_DEBUG_PRINT(4, ("mali_os_resume() called\n"));
-
- ret = mali_deep_resume(device);
-
- return ret;
-}
-
-static int mali_os_freeze(struct device *device)
-{
- int ret = 0;
-
- MALI_DEBUG_PRINT(4, ("mali_os_freeze() called\n"));
-
- mali_dev_freeze();
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->freeze)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->freeze(device);
- }
-
- return ret;
-}
-//copy from r4p1 linux/mali_pmu_power_up_down.c
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
-static int mali_pmu_powerup(void)
-{
- struct mali_pmu_core *pmu = mali_pmu_get_global_pmu_core();
-
- MALI_DEBUG_PRINT(5, ("Mali PMU: Power up\n"));
-
- MALI_DEBUG_ASSERT_POINTER(pmu);
- if (NULL == pmu) {
- return -ENXIO;
- }
-
- mali_pmu_power_up_all(pmu);
-
- return 0;
-}
-#endif
-
-static int mali_os_thaw(struct device *device)
-{
- int ret = 0;
-
- MALI_DEBUG_PRINT(4, ("mali_os_thaw() called\n"));
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
- enable_clock();
- mali_pmu_powerup();
-#endif
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->thaw)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->thaw(device);
- }
-
- return ret;
-}
-
-static int mali_os_restore(struct device *device)
-{
- MALI_DEBUG_PRINT(4, ("mali_os_thaw() called\n"));
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
- mali_dev_restore();
-#endif
- return mali_os_resume(device);
-}
-
-#ifdef CONFIG_PM_RUNTIME
-#if 0
-static int mali_runtime_suspend(struct device *device)
-{
- int ret = 0;
-
- MALI_DEBUG_PRINT(4, ("mali_runtime_suspend() called\n"));
- ret = mali_light_suspend(device);
-
- return ret;
-}
-
-static int mali_runtime_resume(struct device *device)
-{
- int ret = 0;
-
- MALI_DEBUG_PRINT(4, ("mali_run time_resume() called\n"));
- ret = mali_light_resume(device);
-
- return ret;
-}
-
-static int mali_runtime_idle(struct device *device)
-{
- MALI_DEBUG_PRINT(4, ("mali_runtime_idle() called\n"));
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_idle)
- {
- /* Need to notify Mali driver about this event */
- int ret = device->driver->pm->runtime_idle(device);
- if (0 != ret)
- {
- return ret;
- }
- }
-
- pm_runtime_suspend(device);
-
- return 0;
-}
-#endif
-#endif
-
-static struct dev_pm_ops mali_gpu_device_type_pm_ops =
-{
- .suspend = mali_os_suspend,
- .resume = mali_os_resume,
- .freeze = mali_os_freeze,
- .thaw = mali_os_thaw,
- .restore = mali_os_restore,
-#if 0//def CONFIG_PM_RUNTIME
- .runtime_suspend = mali_runtime_suspend,
- .runtime_resume = mali_runtime_resume,
- .runtime_idle = mali_runtime_idle,
-#endif
-};
-
-struct device_type mali_pm_device =
-{
- .pm = &mali_gpu_device_type_pm_ops,
-};
+++ /dev/null
-/*
- * Copyright (C) 2013 ARM Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
- *
- * A copy of the licence is included with the program, and can also be obtained from Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-/**
- * @file arm_core_scaling.h
- * Example core scaling policy.
- */
-
-#ifndef __ARM_CORE_SCALING_H__
-#define __ARM_CORE_SCALING_H__
-
-#include <linux/types.h>
-#include <linux/workqueue.h>
-#include <linux/clk-provider.h>
-#include <linux/clk.h>
-
-enum mali_scale_mode_t {
- MALI_PP_SCALING = 0,
- MALI_PP_FS_SCALING,
- MALI_SCALING_DISABLE,
- MALI_TURBO_MODE,
- MALI_SCALING_MODE_MAX
-};
-
-typedef struct mali_dvfs_threshold_table {
- uint32_t freq_index;
- uint32_t voltage;
- uint32_t keep_count;
- uint32_t downthreshold;
- uint32_t upthreshold;
- uint32_t clk_freq;
- const char *clk_parent;
- struct clk *clkp_handle;
- uint32_t clkp_freq;
-} mali_dvfs_threshold_table;
-
-/**
- * restrictions on frequency and number of pp.
- */
-typedef struct mali_scale_info_t {
- u32 minpp;
- u32 maxpp;
- u32 minclk;
- u32 maxclk;
-} mali_scale_info_t;
-
-/**
- * Platform spesific data for meson chips.
- */
-typedef struct mali_plat_info_t {
- u32 cfg_pp; /* number of pp. */
- u32 cfg_min_pp;
- u32 turbo_clock; /* reserved clock src. */
- u32 def_clock; /* gpu clock used most of time.*/
- u32 cfg_clock; /* max clock could be used.*/
- u32 cfg_clock_bkup; /* same as cfg_clock, for backup. */
- u32 cfg_min_clock;
-
- u32 sc_mpp; /* number of pp used most of time.*/
- u32 bst_gpu; /* threshold for boosting gpu. */
- u32 bst_pp; /* threshold for boosting PP. */
-
- u32 *clk;
- u32 *clk_sample;
- u32 clk_len;
- u32 have_switch; /* have clock gate switch or not. */
-
- mali_dvfs_threshold_table *dvfs_table;
- struct mali_gpu_clk_item *clk_items;
- u32 dvfs_table_size;
-
- mali_scale_info_t scale_info;
- u32 maxclk_sysfs;
- u32 maxpp_sysfs;
-
- /* set upper limit of pp or frequency, for THERMAL thermal or band width saving.*/
- u32 limit_on;
-
- /* for boost up gpu by user. */
- void (*plat_preheat)(void);
-
- struct platform_device *pdev;
- void __iomem *reg_base_hiubus;
- void __iomem *reg_base_aobus;
- struct work_struct wq_work;
- struct clk *clk_mali;
- struct clk *clk_mali_0;
- struct clk *clk_mali_1;
-} mali_plat_info_t;
-mali_plat_info_t* get_mali_plat_data(void);
-
-/**
- * Initialize core scaling policy.
- *
- * @note The core scaling policy will assume that all PP cores are on initially.
- *
- * @param num_pp_cores Total number of PP cores.
- */
-int mali_core_scaling_init(mali_plat_info_t*);
-
-/**
- * Terminate core scaling policy.
- */
-void mali_core_scaling_term(void);
-
-/**
- * cancel and flush scaling job queue.
- */
-void flush_scaling_job(void);
-
-/* get current state(pp, clk). */
-void get_mali_rt_clkpp(u32* clk, u32* pp);
-u32 set_mali_rt_clkpp(u32 clk, u32 pp, u32 flush);
-void revise_mali_rt(void);
-/* get max gpu clk level of this chip*/
-int get_gpu_max_clk_level(void);
-
-/* get or set the scale mode. */
-u32 get_mali_schel_mode(void);
-void set_mali_schel_mode(u32 mode);
-
-/* for frequency reporter in DS-5 streamline. */
-u32 get_current_frequency(void);
-void mali_dev_freeze(void);
-void mali_dev_restore(void);
-
-extern int mali_pm_statue;
-#endif /* __ARM_CORE_SCALING_H__ */
+++ /dev/null
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <linux/clk-provider.h>
-#include <linux/clk.h>
-#include <linux/of_address.h>
-#include <linux/delay.h>
-#include <linux/mali/mali_utgard.h>
-#include <linux/amlogic/cpu_version.h>
-#include "mali_scaling.h"
-#include "mali_clock.h"
-
-#ifndef AML_CLK_LOCK_ERROR
-#define AML_CLK_LOCK_ERROR 1
-#endif
-#define GXBBM_MAX_GPU_FREQ 700000000UL
-struct clk;
-static unsigned gpu_dbg_level = 0;
-module_param(gpu_dbg_level, uint, 0644);
-MODULE_PARM_DESC(gpu_dbg_level, "gpu debug level");
-
-#define gpu_dbg(level, fmt, arg...) \
- do { \
- if (gpu_dbg_level >= (level)) \
- printk("gpu_debug"fmt , ## arg); \
- } while (0)
-
-#define GPU_CLK_DBG(fmt, arg...)
-
-//disable print
-#define _dev_info(...)
-
-//static DEFINE_SPINLOCK(lock);
-static mali_plat_info_t* pmali_plat = NULL;
-//static u32 mali_extr_backup = 0;
-//static u32 mali_extr_sample_backup = 0;
-struct timeval start;
-struct timeval end;
-
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 16))
-int mali_clock_init_clk_tree(struct platform_device* pdev)
-{
- mali_dvfs_threshold_table *dvfs_tbl = &pmali_plat->dvfs_table[pmali_plat->def_clock];
- struct clk *clk_mali_0_parent = dvfs_tbl->clkp_handle;
- struct clk *clk_mali_0 = pmali_plat->clk_mali_0;
-#ifdef AML_CLK_LOCK_ERROR
- struct clk *clk_mali_1 = pmali_plat->clk_mali_1;
-#endif
- struct clk *clk_mali = pmali_plat->clk_mali;
-
- clk_set_parent(clk_mali_0, clk_mali_0_parent);
-
- clk_prepare_enable(clk_mali_0);
-
- clk_set_parent(clk_mali, clk_mali_0);
-
-#ifdef AML_CLK_LOCK_ERROR
- clk_set_parent(clk_mali_1, clk_mali_0_parent);
- clk_prepare_enable(clk_mali_1);
-#endif
-
- GPU_CLK_DBG("%s:enable(%d), %s:enable(%d)\n",
- clk_mali_0->name, clk_mali_0->enable_count,
- clk_mali_0_parent->name, clk_mali_0_parent->enable_count);
-
- return 0;
-}
-
-int mali_clock_init(mali_plat_info_t *pdev)
-{
- *pdev = *pdev;
- return 0;
-}
-
-int mali_clock_critical(critical_t critical, size_t param)
-{
- int ret = 0;
-
- ret = critical(param);
-
- return ret;
-}
-
-static int critical_clock_set(size_t param)
-{
- int ret = 0;
- unsigned int idx = param;
- mali_dvfs_threshold_table *dvfs_tbl = &pmali_plat->dvfs_table[idx];
-
- struct clk *clk_mali_0 = pmali_plat->clk_mali_0;
- struct clk *clk_mali_1 = pmali_plat->clk_mali_1;
- struct clk *clk_mali_x = NULL;
- struct clk *clk_mali_x_parent = NULL;
- struct clk *clk_mali_x_old = NULL;
- struct clk *clk_mali = pmali_plat->clk_mali;
- unsigned long time_use=0;
-
- clk_mali_x_old = clk_get_parent(clk_mali);
-
- if (!clk_mali_x_old) {
- printk("gpu: could not get clk_mali_x_old or clk_mali_x_old\n");
- return 0;
- }
- if (clk_mali_x_old == clk_mali_0) {
- clk_mali_x = clk_mali_1;
- } else if (clk_mali_x_old == clk_mali_1) {
- clk_mali_x = clk_mali_0;
- } else {
- printk("gpu: unmatched clk_mali_x_old\n");
- return 0;
- }
-
- GPU_CLK_DBG("idx=%d, clk_freq=%d\n", idx, dvfs_tbl->clk_freq);
- clk_mali_x_parent = dvfs_tbl->clkp_handle;
- if (!clk_mali_x_parent) {
- printk("gpu: could not get clk_mali_x_parent\n");
- return 0;
- }
-
- GPU_CLK_DBG();
- ret = clk_set_rate(clk_mali_x_parent, dvfs_tbl->clkp_freq);
- GPU_CLK_DBG();
- ret = clk_set_parent(clk_mali_x, clk_mali_x_parent);
- GPU_CLK_DBG();
- ret = clk_set_rate(clk_mali_x, dvfs_tbl->clk_freq);
- GPU_CLK_DBG();
-#ifndef AML_CLK_LOCK_ERROR
- ret = clk_prepare_enable(clk_mali_x);
-#endif
- GPU_CLK_DBG("new %s:enable(%d)\n", clk_mali_x->name, clk_mali_x->enable_count);
- do_gettimeofday(&start);
- udelay(1);// delay 10ns
- do_gettimeofday(&end);
- ret = clk_set_parent(clk_mali, clk_mali_x);
- GPU_CLK_DBG();
-
-#ifndef AML_CLK_LOCK_ERROR
- clk_disable_unprepare(clk_mali_x_old);
-#endif
- GPU_CLK_DBG("old %s:enable(%d)\n", clk_mali_x_old->name, clk_mali_x_old->enable_count);
- time_use = (end.tv_sec - start.tv_sec)*1000000 + end.tv_usec - start.tv_usec;
- GPU_CLK_DBG("step 1, mali_mux use: %ld us\n", time_use);
-
- return 0;
-}
-
-int mali_clock_set(unsigned int clock)
-{
- return mali_clock_critical(critical_clock_set, (size_t)clock);
-}
-
-void disable_clock(void)
-{
- struct clk *clk_mali = pmali_plat->clk_mali;
- struct clk *clk_mali_x = NULL;
-
- clk_mali_x = clk_get_parent(clk_mali);
- GPU_CLK_DBG();
-#ifndef AML_CLK_LOCK_ERROR
- clk_disable_unprepare(clk_mali_x);
-#endif
- GPU_CLK_DBG();
-}
-
-void enable_clock(void)
-{
- struct clk *clk_mali = pmali_plat->clk_mali;
- struct clk *clk_mali_x = NULL;
-
- clk_mali_x = clk_get_parent(clk_mali);
- GPU_CLK_DBG();
-#ifndef AML_CLK_LOCK_ERROR
- clk_prepare_enable(clk_mali_x);
-#endif
- GPU_CLK_DBG();
-}
-
-u32 get_mali_freq(u32 idx)
-{
- if (!mali_pm_statue) {
- return pmali_plat->clk_sample[idx];
- } else {
- return 0;
- }
-}
-
-void set_str_src(u32 data)
-{
- printk("gpu: %s, %s, %d\n", __FILE__, __func__, __LINE__);
-}
-
-int mali_dt_info(struct platform_device *pdev, struct mali_plat_info_t *mpdata)
-{
- struct device_node *gpu_dn = pdev->dev.of_node;
- struct device_node *gpu_clk_dn;
- struct mali_gpu_clk_item *clk_item;
- phandle dvfs_clk_hdl;
- mali_dvfs_threshold_table *dvfs_tbl = NULL;
- uint32_t *clk_sample = NULL;
-
- struct property *prop;
- const __be32 *p;
- int length = 0, i = 0;
- u32 u;
-
- int ret = 0;
- if (!gpu_dn) {
- dev_notice(&pdev->dev, "gpu device node not right\n");
- return -ENODEV;
- }
-
- ret = of_property_read_u32(gpu_dn,"num_of_pp",
- &mpdata->cfg_pp);
- if (ret) {
- dev_notice(&pdev->dev, "set max pp to default 6\n");
- mpdata->cfg_pp = 6;
- }
- mpdata->scale_info.maxpp = mpdata->cfg_pp;
- mpdata->maxpp_sysfs = mpdata->cfg_pp;
- _dev_info(&pdev->dev, "max pp is %d\n", mpdata->scale_info.maxpp);
-
- ret = of_property_read_u32(gpu_dn,"min_pp",
- &mpdata->cfg_min_pp);
- if (ret) {
- dev_notice(&pdev->dev, "set min pp to default 1\n");
- mpdata->cfg_min_pp = 1;
- }
- mpdata->scale_info.minpp = mpdata->cfg_min_pp;
- _dev_info(&pdev->dev, "min pp is %d\n", mpdata->scale_info.minpp);
-
- ret = of_property_read_u32(gpu_dn,"min_clk",
- &mpdata->cfg_min_clock);
- if (ret) {
- dev_notice(&pdev->dev, "set min clk default to 0\n");
- mpdata->cfg_min_clock = 0;
- }
- mpdata->scale_info.minclk = mpdata->cfg_min_clock;
- _dev_info(&pdev->dev, "min clk is %d\n", mpdata->scale_info.minclk);
-
- mpdata->reg_base_hiubus = of_iomap(gpu_dn, 1);
- _dev_info(&pdev->dev, "hiu io source 0x%p\n", mpdata->reg_base_hiubus);
-
- mpdata->reg_base_aobus = of_iomap(gpu_dn, 2);
- _dev_info(&pdev->dev, "hiu io source 0x%p\n", mpdata->reg_base_aobus);
-
- ret = of_property_read_u32(gpu_dn,"sc_mpp",
- &mpdata->sc_mpp);
- if (ret) {
- dev_notice(&pdev->dev, "set pp used most of time default to %d\n", mpdata->cfg_pp);
- mpdata->sc_mpp = mpdata->cfg_pp;
- }
- _dev_info(&pdev->dev, "num of pp used most of time %d\n", mpdata->sc_mpp);
-
- of_get_property(gpu_dn, "tbl", &length);
-
- length = length /sizeof(u32);
- _dev_info(&pdev->dev, "clock dvfs cfg table size is %d\n", length);
-
- mpdata->dvfs_table = devm_kzalloc(&pdev->dev,
- sizeof(struct mali_dvfs_threshold_table)*length,
- GFP_KERNEL);
- dvfs_tbl = mpdata->dvfs_table;
- if (mpdata->dvfs_table == NULL) {
- dev_err(&pdev->dev, "failed to alloc dvfs table\n");
- return -ENOMEM;
- }
- mpdata->clk_sample = devm_kzalloc(&pdev->dev, sizeof(u32)*length, GFP_KERNEL);
- if (mpdata->clk_sample == NULL) {
- dev_err(&pdev->dev, "failed to alloc clk_sample table\n");
- return -ENOMEM;
- }
- clk_sample = mpdata->clk_sample;
-///////////
- mpdata->clk_items = devm_kzalloc(&pdev->dev, sizeof(struct mali_gpu_clk_item) * length, GFP_KERNEL);
- if (mpdata->clk_items == NULL) {
- dev_err(&pdev->dev, "failed to alloc clk_item table\n");
- return -ENOMEM;
- }
- clk_item = mpdata->clk_items;
-//
- of_property_for_each_u32(gpu_dn, "tbl", prop, p, u) {
- dvfs_clk_hdl = (phandle) u;
- gpu_clk_dn = of_find_node_by_phandle(dvfs_clk_hdl);
- ret = of_property_read_u32(gpu_clk_dn,"clk_freq", &dvfs_tbl->clk_freq);
- if (ret) {
- dev_notice(&pdev->dev, "read clk_freq failed\n");
- }
-#if 0
-#ifdef MESON_CPU_VERSION_OPS
- if (is_meson_gxbbm_cpu()) {
- if (dvfs_tbl->clk_freq >= GXBBM_MAX_GPU_FREQ)
- continue;
- }
-#endif
-#endif
- ret = of_property_read_string(gpu_clk_dn,"clk_parent",
- &dvfs_tbl->clk_parent);
- if (ret) {
- dev_notice(&pdev->dev, "read clk_parent failed\n");
- }
- dvfs_tbl->clkp_handle = devm_clk_get(&pdev->dev, dvfs_tbl->clk_parent);
- if (IS_ERR(dvfs_tbl->clkp_handle)) {
- dev_notice(&pdev->dev, "failed to get %s's clock pointer\n", dvfs_tbl->clk_parent);
- }
- ret = of_property_read_u32(gpu_clk_dn,"clkp_freq", &dvfs_tbl->clkp_freq);
- if (ret) {
- dev_notice(&pdev->dev, "read clk_parent freq failed\n");
- }
- ret = of_property_read_u32(gpu_clk_dn,"voltage", &dvfs_tbl->voltage);
- if (ret) {
- dev_notice(&pdev->dev, "read voltage failed\n");
- }
- ret = of_property_read_u32(gpu_clk_dn,"keep_count", &dvfs_tbl->keep_count);
- if (ret) {
- dev_notice(&pdev->dev, "read keep_count failed\n");
- }
- //downthreshold and upthreshold shall be u32
- ret = of_property_read_u32_array(gpu_clk_dn,"threshold",
- &dvfs_tbl->downthreshold, 2);
- if (ret) {
- dev_notice(&pdev->dev, "read threshold failed\n");
- }
- dvfs_tbl->freq_index = i;
- clk_item->clock = dvfs_tbl->clk_freq / 1000000;
- clk_item->vol = dvfs_tbl->voltage;
-
- *clk_sample = dvfs_tbl->clk_freq / 1000000;
-
- dvfs_tbl ++;
- clk_item ++;
- clk_sample ++;
- i++;
- mpdata->dvfs_table_size ++;
- }
-
- ret = of_property_read_u32(gpu_dn,"max_clk",
- &mpdata->cfg_clock);
- if (ret) {
- dev_notice(&pdev->dev, "max clk set %d\n", mpdata->dvfs_table_size-2);
- mpdata->cfg_clock = mpdata->dvfs_table_size-2;
- }
-
- mpdata->cfg_clock_bkup = mpdata->cfg_clock;
- mpdata->maxclk_sysfs = mpdata->cfg_clock;
- mpdata->scale_info.maxclk = mpdata->cfg_clock;
- _dev_info(&pdev->dev, "max clk is %d\n", mpdata->scale_info.maxclk);
-
- ret = of_property_read_u32(gpu_dn,"turbo_clk",
- &mpdata->turbo_clock);
- if (ret) {
- dev_notice(&pdev->dev, "turbo clk set to %d\n", mpdata->dvfs_table_size-1);
- mpdata->turbo_clock = mpdata->dvfs_table_size-1;
- }
- _dev_info(&pdev->dev, "turbo clk is %d\n", mpdata->turbo_clock);
-
- ret = of_property_read_u32(gpu_dn,"def_clk",
- &mpdata->def_clock);
- if (ret) {
- dev_notice(&pdev->dev, "default clk set to %d\n", mpdata->dvfs_table_size/2-1);
- mpdata->def_clock = mpdata->dvfs_table_size/2 - 1;
- }
- _dev_info(&pdev->dev, "default clk is %d\n", mpdata->def_clock);
-
- dvfs_tbl = mpdata->dvfs_table;
- clk_sample = mpdata->clk_sample;
- for (i = 0; i< mpdata->dvfs_table_size; i++) {
- _dev_info(&pdev->dev, "====================%d====================\n"
- "clk_freq=%10d, clk_parent=%9s, voltage=%d, keep_count=%d, threshod=<%d %d>, clk_sample=%d\n",
- i,
- dvfs_tbl->clk_freq, dvfs_tbl->clk_parent,
- dvfs_tbl->voltage, dvfs_tbl->keep_count,
- dvfs_tbl->downthreshold, dvfs_tbl->upthreshold, *clk_sample);
- dvfs_tbl ++;
- clk_sample ++;
- }
- _dev_info(&pdev->dev, "clock dvfs table size is %d\n", mpdata->dvfs_table_size);
-
- mpdata->clk_mali = devm_clk_get(&pdev->dev, "clk_mali");
- mpdata->clk_mali_0 = devm_clk_get(&pdev->dev, "clk_mali_0");
- mpdata->clk_mali_1 = devm_clk_get(&pdev->dev, "clk_mali_1");
- if (IS_ERR(mpdata->clk_mali) || IS_ERR(mpdata->clk_mali_0) || IS_ERR(mpdata->clk_mali_1)) {
- dev_err(&pdev->dev, "failed to get clock pointer\n");
- return -EFAULT;
- }
-
- pmali_plat = mpdata;
- mpdata->pdev = pdev;
- return 0;
-}
-#else
-int mali_clock_init_clk_tree(struct platform_device* pdev)
-{
- //mali_dvfs_threshold_table *dvfs_tbl = &pmali_plat->dvfs_table[pmali_plat->def_clock];
- struct clk *clk_mali = pmali_plat->clk_mali;
-
- clk_prepare_enable(clk_mali);
-
- return 0;
-}
-
-int mali_clock_init(mali_plat_info_t *pdev)
-{
- *pdev = *pdev;
- return 0;
-}
-
-int mali_clock_critical(critical_t critical, size_t param)
-{
- int ret = 0;
-
- ret = critical(param);
-
- return ret;
-}
-
-static int critical_clock_set(size_t param)
-{
- int ret = 0;
- unsigned int idx = param;
- mali_dvfs_threshold_table *dvfs_tbl = &pmali_plat->dvfs_table[idx];
-
- struct clk *clk_mali = pmali_plat->clk_mali;
- unsigned long time_use=0;
-
-
- GPU_CLK_DBG();
- do_gettimeofday(&start);
- ret = clk_set_rate(clk_mali, dvfs_tbl->clk_freq);
- do_gettimeofday(&end);
- GPU_CLK_DBG();
-
-#ifndef AML_CLK_LOCK_ERROR
- clk_disable_unprepare(clk_mali_x_old);
-#endif
- time_use = (end.tv_sec - start.tv_sec)*1000000 + end.tv_usec - start.tv_usec;
- GPU_CLK_DBG("step 1, mali_mux use: %ld us\n", time_use);
-
- return 0;
-}
-
-int mali_clock_set(unsigned int clock)
-{
- return mali_clock_critical(critical_clock_set, (size_t)clock);
-}
-
-void disable_clock(void)
-{
-#ifndef AML_CLK_LOCK_ERROR
- struct clk *clk_mali = pmali_plat->clk_mali;
-
- GPU_CLK_DBG();
- clk_disable_unprepare(clk_mali);
-#endif
- GPU_CLK_DBG();
-}
-
-void enable_clock(void)
-{
-#ifndef AML_CLK_LOCK_ERROR
- struct clk *clk_mali = pmali_plat->clk_mali;
-
- clk_prepare_enable(clk_mali);
-#endif
- GPU_CLK_DBG();
-}
-
-u32 get_mali_freq(u32 idx)
-{
- if (!mali_pm_statue) {
- return pmali_plat->clk_sample[idx];
- } else {
- return 0;
- }
-}
-
-void set_str_src(u32 data)
-{
- printk("gpu: %s, %s, %d\n", __FILE__, __func__, __LINE__);
-}
-
-int mali_dt_info(struct platform_device *pdev, struct mali_plat_info_t *mpdata)
-{
- struct device_node *gpu_dn = pdev->dev.of_node;
- struct device_node *gpu_clk_dn;
- struct mali_gpu_clk_item *clk_item;
- phandle dvfs_clk_hdl;
- mali_dvfs_threshold_table *dvfs_tbl = NULL;
- uint32_t *clk_sample = NULL;
-
- struct property *prop;
- const __be32 *p;
- int length = 0, i = 0;
- u32 u;
-
- int ret = 0;
- if (!gpu_dn) {
- dev_notice(&pdev->dev, "gpu device node not right\n");
- return -ENODEV;
- }
-
- ret = of_property_read_u32(gpu_dn,"num_of_pp",
- &mpdata->cfg_pp);
- if (ret) {
- dev_notice(&pdev->dev, "set max pp to default 6\n");
- mpdata->cfg_pp = 6;
- }
- mpdata->scale_info.maxpp = mpdata->cfg_pp;
- mpdata->maxpp_sysfs = mpdata->cfg_pp;
- _dev_info(&pdev->dev, "max pp is %d\n", mpdata->scale_info.maxpp);
-
- ret = of_property_read_u32(gpu_dn,"min_pp",
- &mpdata->cfg_min_pp);
- if (ret) {
- dev_notice(&pdev->dev, "set min pp to default 1\n");
- mpdata->cfg_min_pp = 1;
- }
- mpdata->scale_info.minpp = mpdata->cfg_min_pp;
- _dev_info(&pdev->dev, "min pp is %d\n", mpdata->scale_info.minpp);
-
- ret = of_property_read_u32(gpu_dn,"min_clk",
- &mpdata->cfg_min_clock);
- if (ret) {
- dev_notice(&pdev->dev, "set min clk default to 0\n");
- mpdata->cfg_min_clock = 0;
- }
- mpdata->scale_info.minclk = mpdata->cfg_min_clock;
- _dev_info(&pdev->dev, "min clk is %d\n", mpdata->scale_info.minclk);
-
- mpdata->reg_base_hiubus = of_iomap(gpu_dn, 1);
- _dev_info(&pdev->dev, "hiu io source 0x%p\n", mpdata->reg_base_hiubus);
-
- mpdata->reg_base_aobus = of_iomap(gpu_dn, 2);
- _dev_info(&pdev->dev, "hiu io source 0x%p\n", mpdata->reg_base_aobus);
-
- ret = of_property_read_u32(gpu_dn,"sc_mpp",
- &mpdata->sc_mpp);
- if (ret) {
- dev_notice(&pdev->dev, "set pp used most of time default to %d\n", mpdata->cfg_pp);
- mpdata->sc_mpp = mpdata->cfg_pp;
- }
- _dev_info(&pdev->dev, "num of pp used most of time %d\n", mpdata->sc_mpp);
-
- of_get_property(gpu_dn, "tbl", &length);
-
- length = length /sizeof(u32);
- _dev_info(&pdev->dev, "clock dvfs cfg table size is %d\n", length);
-
- mpdata->dvfs_table = devm_kzalloc(&pdev->dev,
- sizeof(struct mali_dvfs_threshold_table)*length,
- GFP_KERNEL);
- dvfs_tbl = mpdata->dvfs_table;
- if (mpdata->dvfs_table == NULL) {
- dev_err(&pdev->dev, "failed to alloc dvfs table\n");
- return -ENOMEM;
- }
- mpdata->clk_sample = devm_kzalloc(&pdev->dev, sizeof(u32)*length, GFP_KERNEL);
- if (mpdata->clk_sample == NULL) {
- dev_err(&pdev->dev, "failed to alloc clk_sample table\n");
- return -ENOMEM;
- }
- clk_sample = mpdata->clk_sample;
-///////////
- mpdata->clk_items = devm_kzalloc(&pdev->dev, sizeof(struct mali_gpu_clk_item) * length, GFP_KERNEL);
- if (mpdata->clk_items == NULL) {
- dev_err(&pdev->dev, "failed to alloc clk_item table\n");
- return -ENOMEM;
- }
- clk_item = mpdata->clk_items;
-//
- of_property_for_each_u32(gpu_dn, "tbl", prop, p, u) {
- dvfs_clk_hdl = (phandle) u;
- gpu_clk_dn = of_find_node_by_phandle(dvfs_clk_hdl);
- ret = of_property_read_u32(gpu_clk_dn,"clk_freq", &dvfs_tbl->clk_freq);
- if (ret) {
- dev_notice(&pdev->dev, "read clk_freq failed\n");
- }
-#if 0
-#ifdef MESON_CPU_VERSION_OPS
- if (is_meson_gxbbm_cpu()) {
- if (dvfs_tbl->clk_freq >= GXBBM_MAX_GPU_FREQ)
- continue;
- }
-#endif
-#endif
-#if 0
- ret = of_property_read_string(gpu_clk_dn,"clk_parent",
- &dvfs_tbl->clk_parent);
- if (ret) {
- dev_notice(&pdev->dev, "read clk_parent failed\n");
- }
- dvfs_tbl->clkp_handle = devm_clk_get(&pdev->dev, dvfs_tbl->clk_parent);
- if (IS_ERR(dvfs_tbl->clkp_handle)) {
- dev_notice(&pdev->dev, "failed to get %s's clock pointer\n", dvfs_tbl->clk_parent);
- }
- ret = of_property_read_u32(gpu_clk_dn,"clkp_freq", &dvfs_tbl->clkp_freq);
- if (ret) {
- dev_notice(&pdev->dev, "read clk_parent freq failed\n");
- }
-#endif
- ret = of_property_read_u32(gpu_clk_dn,"voltage", &dvfs_tbl->voltage);
- if (ret) {
- dev_notice(&pdev->dev, "read voltage failed\n");
- }
- ret = of_property_read_u32(gpu_clk_dn,"keep_count", &dvfs_tbl->keep_count);
- if (ret) {
- dev_notice(&pdev->dev, "read keep_count failed\n");
- }
- //downthreshold and upthreshold shall be u32
- ret = of_property_read_u32_array(gpu_clk_dn,"threshold",
- &dvfs_tbl->downthreshold, 2);
- if (ret) {
- dev_notice(&pdev->dev, "read threshold failed\n");
- }
- dvfs_tbl->freq_index = i;
- clk_item->clock = dvfs_tbl->clk_freq / 1000000;
- clk_item->vol = dvfs_tbl->voltage;
-
- *clk_sample = dvfs_tbl->clk_freq / 1000000;
-
- dvfs_tbl ++;
- clk_item ++;
- clk_sample ++;
- i++;
- mpdata->dvfs_table_size ++;
- }
-
- ret = of_property_read_u32(gpu_dn,"max_clk",
- &mpdata->cfg_clock);
- if (ret) {
- dev_notice(&pdev->dev, "max clk set %d\n", mpdata->dvfs_table_size-2);
- mpdata->cfg_clock = mpdata->dvfs_table_size-2;
- }
-
- mpdata->cfg_clock_bkup = mpdata->cfg_clock;
- mpdata->maxclk_sysfs = mpdata->cfg_clock;
- mpdata->scale_info.maxclk = mpdata->cfg_clock;
- _dev_info(&pdev->dev, "max clk is %d\n", mpdata->scale_info.maxclk);
-
- ret = of_property_read_u32(gpu_dn,"turbo_clk",
- &mpdata->turbo_clock);
- if (ret) {
- dev_notice(&pdev->dev, "turbo clk set to %d\n", mpdata->dvfs_table_size-1);
- mpdata->turbo_clock = mpdata->dvfs_table_size-1;
- }
- _dev_info(&pdev->dev, "turbo clk is %d\n", mpdata->turbo_clock);
-
- ret = of_property_read_u32(gpu_dn,"def_clk",
- &mpdata->def_clock);
- if (ret) {
- dev_notice(&pdev->dev, "default clk set to %d\n", mpdata->dvfs_table_size/2-1);
- mpdata->def_clock = mpdata->dvfs_table_size/2 - 1;
- }
- _dev_info(&pdev->dev, "default clk is %d\n", mpdata->def_clock);
-
- dvfs_tbl = mpdata->dvfs_table;
- clk_sample = mpdata->clk_sample;
- for (i = 0; i< mpdata->dvfs_table_size; i++) {
- _dev_info(&pdev->dev, "====================%d====================\n"
- "clk_freq=%10d, clk_parent=%9s, voltage=%d, keep_count=%d, threshod=<%d %d>, clk_sample=%d\n",
- i,
- dvfs_tbl->clk_freq, dvfs_tbl->clk_parent,
- dvfs_tbl->voltage, dvfs_tbl->keep_count,
- dvfs_tbl->downthreshold, dvfs_tbl->upthreshold, *clk_sample);
- dvfs_tbl ++;
- clk_sample ++;
- }
- _dev_info(&pdev->dev, "clock dvfs table size is %d\n", mpdata->dvfs_table_size);
-
- mpdata->clk_mali = devm_clk_get(&pdev->dev, "gpu_mux");
-#if 0
- mpdata->clk_mali_0 = devm_clk_get(&pdev->dev, "clk_mali_0");
- mpdata->clk_mali_1 = devm_clk_get(&pdev->dev, "clk_mali_1");
-#endif
- if (IS_ERR(mpdata->clk_mali)) {
- dev_err(&pdev->dev, "failed to get clock pointer\n");
- return -EFAULT;
- }
-
- pmali_plat = mpdata;
- mpdata->pdev = pdev;
- return 0;
-}
-
-#endif
+++ /dev/null
-#ifndef __MALI_CLOCK_H__
-#define __MALI_CLOCK_H__
-#include <linux/version.h>
-#include <linux/pm.h>
-#include <linux/io.h>
-#include <linux/types.h>
-#include <linux/of.h>
-
-#include <asm/io.h>
-#include <linux/clk.h>
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 29))
-#include <linux/amlogic/iomap.h>
-#endif
-
-#ifndef HHI_MALI_CLK_CNTL
-#define HHI_MALI_CLK_CNTL 0x6C
-#define mplt_read(r) readl((pmali_plat->reg_base_hiubus) + ((r)<<2))
-#define mplt_write(r, v) writel((v), ((pmali_plat->reg_base_hiubus) + ((r)<<2)))
-#define mplt_setbits(r, m) mplt_write((r), (mplt_read(r) | (m)));
-#define mplt_clrbits(r, m) mplt_write((r), (mplt_read(r) & (~(m))));
-#endif
-
-//extern int mali_clock_init(struct platform_device *dev);
-int mali_clock_init_clk_tree(struct platform_device *pdev);
-
-typedef int (*critical_t)(size_t param);
-int mali_clock_critical(critical_t critical, size_t param);
-
-int mali_clock_init(mali_plat_info_t*);
-int mali_clock_set(unsigned int index);
-void disable_clock(void);
-void enable_clock(void);
-u32 get_mali_freq(u32 idx);
-void set_str_src(u32 data);
-int mali_dt_info(struct platform_device *pdev,
- struct mali_plat_info_t *mpdata);
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2013 ARM Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
- *
- * A copy of the licence is included with the program, and can also be obtained from Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-/**
- * @file arm_core_scaling.c
- * Example core scaling policy.
- */
-
-#include <linux/version.h>
-#include <linux/module.h>
-#include <linux/workqueue.h>
-#include <linux/mali/mali_utgard.h>
-#include <mali_kernel_common.h>
-#include <mali_osk_profiling.h>
-#include <linux/time.h>
-
-//#include <linux/amlogic/amports/gp_pll.h>
-#include "meson_main2.h"
-
-
-static int currentStep;
-static int scaling_mode = MALI_PP_FS_SCALING;
-//static int scaling_mode = MALI_SCALING_DISABLE;
-//static int scaling_mode = MALI_PP_SCALING;
-
-//static struct gp_pll_user_handle_s *gp_pll_user_gpu;
-//static int is_gp_pll_get;
-//static int is_gp_pll_put;
-
-static unsigned scaling_dbg_level = 0;
-module_param(scaling_dbg_level, uint, 0644);
-MODULE_PARM_DESC(scaling_dbg_level , "scaling debug level");
-
-static mali_plat_info_t* pmali_plat = NULL;
-static struct workqueue_struct *mali_scaling_wq = NULL;
-//static DEFINE_SPINLOCK(lock);
-
-static int cur_gpu_clk_index = 0;
-static int exec_gpu_clk_index = 0;
-#define scalingdbg(level, fmt, arg...) \
- do { \
- if (scaling_dbg_level >= (level)) \
- printk(fmt , ## arg); \
- } while (0)
-
-struct mali_gpu_clock meson_gpu_clk_info = {
- .item = NULL,
- .num_of_steps = 0,
-};
-
-u32 revise_set_clk(u32 val, u32 flush)
-{
- u32 ret = 0;
- return ret;
-}
-
-void get_mali_rt_clkpp(u32* clk, u32* pp)
-{
-}
-
-u32 set_mali_rt_clkpp(u32 clk, u32 pp, u32 flush)
-{
- u32 ret = 0;
- return ret;
-}
-
-void revise_mali_rt(void)
-{
-}
-
-static void do_scaling(struct work_struct *work)
-{
- //unsigned long flags;
- mali_plat_info_t *pinfo = container_of(work, struct mali_plat_info_t, wq_work);
-
- *pinfo = *pinfo;
- //mali_dev_pause();
- //spin_lock_irqsave(&lock, flags);
- mali_clock_set(exec_gpu_clk_index);
- cur_gpu_clk_index = exec_gpu_clk_index;
- //spin_unlock_irqrestore(&lock, flags);
- //mali_dev_resume();
-}
-void flush_scaling_job(void)
-{
- if (mali_scaling_wq == NULL) return;
-
- flush_workqueue(mali_scaling_wq);
- printk("%s, %d\n", __func__, __LINE__);
-}
-
-
-int mali_core_scaling_init(mali_plat_info_t *mali_plat)
-{
- pmali_plat = mali_plat;
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)
- mali_scaling_wq = alloc_workqueue("gpu_scaling_wq", WQ_HIGHPRI | WQ_UNBOUND, 0);
-#else
- mali_scaling_wq = create_workqueue("gpu_scaling_wq");
-#endif
- INIT_WORK(&pmali_plat->wq_work, do_scaling);
- if (mali_scaling_wq == NULL) printk("Unable to create gpu scaling workqueue\n");
-
- meson_gpu_clk_info.num_of_steps = pmali_plat->scale_info.maxclk;
-
- return 0;
-}
-
-void mali_core_scaling_term(void)
-{
- flush_scaling_job();
- destroy_workqueue(mali_scaling_wq);
- mali_scaling_wq = NULL;
-}
-
-void mali_pp_scaling_update(struct mali_gpu_utilization_data *data)
-{
-}
-
-void mali_pp_fs_scaling_update(struct mali_gpu_utilization_data *data)
-{
-}
-
-u32 get_mali_schel_mode(void)
-{
- return scaling_mode;
-}
-
-void set_mali_schel_mode(u32 mode)
-{
- scaling_mode = mode;
- if (scaling_mode == MALI_TURBO_MODE) {
- printk ("turbo mode\n");
- pmali_plat->limit_on = 0;
- meson_gpu_clk_info.num_of_steps = pmali_plat->turbo_clock;
- } else {
- printk ("not turbo mode\n");
- pmali_plat->limit_on = 1;
- meson_gpu_clk_info.num_of_steps = pmali_plat->scale_info.maxclk;
- }
-
- printk("total_enable_steps = %d\n", meson_gpu_clk_info.num_of_steps);
-}
-
-u32 get_current_frequency(void)
-{
- return get_mali_freq(currentStep);
-}
-
-void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data)
-{
-}
-
-void mali_dev_restore(void)
-{
- //TO add this
- //mali_perf_set_num_pp_cores(num_cores_enabled);
- if (pmali_plat && pmali_plat->pdev) {
- mali_clock_init_clk_tree(pmali_plat->pdev);
- } else {
- printk("error: init clock failed, pmali_plat=%p, pmali_plat->pdev=%p\n",
- pmali_plat, pmali_plat == NULL ? NULL: pmali_plat->pdev);
- }
-}
-
-/* Function that platfrom report it's clock info which driver can set, needed when CONFIG_MALI_DVFS enabled */
-static void meson_platform_get_clock_info(struct mali_gpu_clock **data) {
- if (pmali_plat) {
- meson_gpu_clk_info.item = pmali_plat->clk_items;
- meson_gpu_clk_info.num_of_steps = pmali_plat->scale_info.maxclk;
- printk("get clock info\n");
- } else {
- printk("error pmali_plat is null");
- }
- *data = &meson_gpu_clk_info;
-}
-
-/* Function that get the current clock info, needed when CONFIG_MALI_DVFS enabled */
-static int meson_platform_get_freq(void) {
- scalingdbg(1, "cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
- //dynamically changed the num of steps;
- return cur_gpu_clk_index;
-}
-
-/* Fuction that platform callback for freq setting, needed when CONFIG_MALI_DVFS enabled */
-static int meson_platform_set_freq(int setting_clock_step) {
-
- if (exec_gpu_clk_index == setting_clock_step) {
- return 0;
- }
-
- queue_work(mali_scaling_wq, &pmali_plat->wq_work);
- exec_gpu_clk_index = setting_clock_step;
- scalingdbg(1, "set cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
- return 0;
-}
-
-int mali_meson_get_gpu_data(struct mali_gpu_device_data *mgpu_data)
-{
- mgpu_data->get_clock_info = meson_platform_get_clock_info,
- mgpu_data->get_freq = meson_platform_get_freq,
- mgpu_data->set_freq = meson_platform_set_freq,
- mgpu_data->utilization_callback = NULL;
- return 0;
-}
+++ /dev/null
-/*
- * mali_platform.h
- *
- * Created on: Nov 8, 2013
- * Author: amlogic
- */
-
-#include <linux/kernel.h>
-#ifndef MALI_PLATFORM_H_
-#define MALI_PLATFORM_H_
-
-extern u32 mali_gp_reset_fail;
-extern u32 mali_core_timeout;
-
-#endif /* MALI_PLATFORM_H_ */
+++ /dev/null
-../mali_scaling.h
\ No newline at end of file
+++ /dev/null
-/*
- * Copyright (C) 2010, 2012-2014 Amlogic Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
- *
- */
-
-/**
- * @file mali_platform.c
- * Platform specific Mali driver functions for:
- * meson8m2 and the newer chip
- */
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#ifdef CONFIG_PM_RUNTIME
-#include <linux/pm_runtime.h>
-#endif
-#include <asm/io.h>
-#include <linux/mali/mali_utgard.h>
-#include "mali_kernel_common.h"
-#include <linux/dma-mapping.h>
-#include <linux/moduleparam.h>
-
-#include "mali_executor.h"
-#include "mali_scaling.h"
-#include "mali_clock.h"
-#include "meson_main2.h"
-
-int mali_pm_statue = 0;
-extern void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data);
-
-u32 mali_gp_reset_fail = 0;
-module_param(mali_gp_reset_fail, int, S_IRUSR | S_IWUSR | S_IWGRP | S_IRGRP | S_IROTH); /* rw-rw-r-- */
-MODULE_PARM_DESC(mali_gp_reset_fail, "times of failed to reset GP");
-u32 mali_core_timeout = 0;
-module_param(mali_core_timeout, int, S_IRUSR | S_IWUSR | S_IWGRP | S_IRGRP | S_IROTH); /* rw-rw-r-- */
-MODULE_PARM_DESC(mali_core_timeout, "timeout of failed to reset GP");
-
-static struct mali_gpu_device_data mali_gpu_data = {
-
-#if defined(CONFIG_ARCH_REALVIEW)
- .dedicated_mem_start = 0x80000000, /* Physical start address (use 0xD0000000 for old indirect setup) */
- .dedicated_mem_size = 0x10000000, /* 256MB */
-#endif
-#if defined(CONFIG_ARM64)
- .fb_start = 0x5f000000,
- .fb_size = 0x91000000,
-#else
- .fb_start = 0xe0000000,
- .fb_size = 0x01000000,
-#endif
- .control_interval = 200, /* 1000ms */
-};
-
-int mali_platform_device_init(struct platform_device *device)
-{
- int err = -1;
-
- err = mali_meson_init_start(device);
- if (0 != err) printk("mali init failed\n");
- err = mali_meson_get_gpu_data(&mali_gpu_data);
- if (0 != err) printk("mali get gpu data failed\n");
-
- err = platform_device_add_data(device, &mali_gpu_data, sizeof(mali_gpu_data));
-
- if (0 == err) {
- device->dev.type = &mali_pm_device; /* We should probably use the pm_domain instead of type on newer kernels */
-#ifdef CONFIG_PM_RUNTIME
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
- pm_runtime_set_autosuspend_delay(&device->dev, 1000);
- pm_runtime_use_autosuspend(&device->dev);
-#endif
- pm_runtime_enable(&device->dev);
-#endif
- mali_meson_init_finish(device);
- }
-
- mali_gp_reset_fail = 0;
- mali_core_timeout = 0;
-
- return err;
-}
-
-int mali_platform_device_deinit(struct platform_device *device)
-{
- MALI_IGNORE(device);
-
- printk("%s, %d\n", __FILE__, __LINE__);
- MALI_DEBUG_PRINT(4, ("mali_platform_device_deinit() called\n"));
-
-
- mali_meson_uninit(device);
-
- return 0;
-}
-
-#if 0
-static int param_set_core_scaling(const char *val, const struct kernel_param *kp)
-{
- int ret = param_set_int(val, kp);
- printk("%s, %d\n", __FILE__, __LINE__);
-
- if (1 == mali_core_scaling_enable) {
- mali_core_scaling_sync(mali_executor_get_num_cores_enabled());
- }
- return ret;
-}
-
-static struct kernel_param_ops param_ops_core_scaling = {
- .set = param_set_core_scaling,
- .get = param_get_int,
-};
-
-module_param_cb(mali_core_scaling_enable, ¶m_ops_core_scaling, &mali_core_scaling_enable, 0644);
-MODULE_PARM_DESC(mali_core_scaling_enable, "1 means to enable core scaling policy, 0 means to disable core scaling policy");
-#endif
+++ /dev/null
-/*
- * mali_platform.h
- *
- * Created on: Nov 8, 2013
- * Author: amlogic
- */
-
-#ifndef MESON_MAIN_H_
-#define MESON_MAIN_H_
-#include <linux/version.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#ifdef CONFIG_PM_RUNTIME
-#include <linux/pm_runtime.h>
-#endif
-#include <linux/mali/mali_utgard.h>
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/cpu.h>
-#endif
-
-#include "mali_scaling.h"
-#include "mali_clock.h"
-
-extern struct device_type mali_pm_device;
-extern int mali_pm_statue;
-
-u32 set_max_mali_freq(u32 idx);
-u32 get_max_mali_freq(void);
-
-int mali_meson_init_start(struct platform_device* ptr_plt_dev);
-int mali_meson_get_gpu_data(struct mali_gpu_device_data *mgpu_data);
-int mali_meson_init_finish(struct platform_device* ptr_plt_dev);
-int mali_meson_uninit(struct platform_device* ptr_plt_dev);
-int mali_light_suspend(struct device *device);
-int mali_light_resume(struct device *device);
-int mali_deep_suspend(struct device *device);
-int mali_deep_resume(struct device *device);
-
-#endif /* MESON_MAIN_H_ */
+++ /dev/null
-/*******************************************************************
- *
- * Copyright C 2013 by Amlogic, Inc. All Rights Reserved.
- *
- * Description:
- *
- * Author: Amlogic Software
- * Created: 2010/4/1 19:46
- *
- *******************************************************************/
-/* Standard Linux headers */
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/string.h>
-#include <linux/slab.h>
-#include <linux/list.h>
-
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/io.h>
-#include <plat/io.h>
-#include <asm/io.h>
-#endif
-
-#include <linux/mali/mali_utgard.h>
-#include <common/mali_kernel_common.h>
-#include <common/mali_pmu.h>
-//#include "mali_pp_scheduler.h"
-#include "meson_main.h"
-
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
-static ssize_t domain_stat_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- unsigned int val;
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
-
- val = readl(pmali_plat->reg_base_aobus + 0xf0) & 0xff;
- return sprintf(buf, "%x\n", val>>4);
- return 0;
-}
-
-#define PREHEAT_CMD "preheat"
-#define PLL2_CMD "mpl2" /* mpl2 [11] or [0xxxxxxx] */
-#define SCMPP_CMD "scmpp" /* scmpp [number of pp your want in most of time]. */
-#define BSTGPU_CMD "bstgpu" /* bstgpu [0-256] */
-#define BSTPP_CMD "bstpp" /* bstpp [0-256] */
-#define LIMIT_CMD "lmt" /* lmt [0 or 1] */
-#define MAX_TOKEN 20
-#define FULL_UTILIZATION 256
-
-static ssize_t mpgpu_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- char *pstart, *cprt = NULL;
- u32 val = 0;
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
-
- cprt = skip_spaces(buf);
- pstart = strsep(&cprt," ");
- if (strlen(pstart) < 1)
- goto quit;
-
- if (!strncmp(pstart, PREHEAT_CMD, MAX_TOKEN)) {
- if (pmali_plat->plat_preheat) {
- pmali_plat->plat_preheat();
- }
- } else if (!strncmp(pstart, PLL2_CMD, MAX_TOKEN)) {
- int base = 10;
- if ((strlen(cprt) > 2) && (cprt[0] == '0') &&
- (cprt[1] == 'x' || cprt[1] == 'X'))
- base = 16;
- if (kstrtouint(cprt, base, &val) <0)
- goto quit;
- if (val < 11)
- pmali_plat->cfg_clock = pmali_plat->cfg_clock_bkup;
- else
- pmali_plat->cfg_clock = pmali_plat->turbo_clock;
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- set_str_src(val);
- } else if (!strncmp(pstart, SCMPP_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
- if ((val > 0) && (val < pmali_plat->cfg_pp)) {
- pmali_plat->sc_mpp = val;
- }
- } else if (!strncmp(pstart, BSTGPU_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
- if ((val > 0) && (val < FULL_UTILIZATION)) {
- pmali_plat->bst_gpu = val;
- }
- } else if (!strncmp(pstart, BSTPP_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
- if ((val > 0) && (val < FULL_UTILIZATION)) {
- pmali_plat->bst_pp = val;
- }
- } else if (!strncmp(pstart, LIMIT_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
-
- if (val < 2) {
- pmali_plat->limit_on = val;
- if (val == 0) {
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- pmali_plat->scale_info.maxpp = pmali_plat->cfg_pp;
- revise_mali_rt();
- }
- }
- }
-quit:
- return count;
-}
-
-static ssize_t scale_mode_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- return sprintf(buf, "%d\n", get_mali_schel_mode());
-}
-
-static ssize_t scale_mode_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
-
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- {
- return -EINVAL;
- }
-
- set_mali_schel_mode(val);
-
- return count;
-}
-
-static ssize_t max_pp_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- printk("maxpp:%d, maxpp_sysfs:%d, total=%d\n",
- pmali_plat->scale_info.maxpp, pmali_plat->maxpp_sysfs,
- pmali_plat->cfg_pp);
- return sprintf(buf, "%d\n", pmali_plat->cfg_pp);
-}
-
-static ssize_t max_pp_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pmali_plat->cfg_pp) || (val < pinfo->minpp))
- return -EINVAL;
-
- pmali_plat->maxpp_sysfs = val;
- pinfo->maxpp = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t min_pp_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- return sprintf(buf, "%d\n", pmali_plat->scale_info.minpp);
-}
-
-static ssize_t min_pp_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pinfo->maxpp) || (val < 1))
- return -EINVAL;
-
- pinfo->minpp = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t max_freq_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- printk("maxclk:%d, maxclk_sys:%d, max gpu level=%d\n",
- pmali_plat->scale_info.maxclk, pmali_plat->maxclk_sysfs, get_gpu_max_clk_level());
- return sprintf(buf, "%d\n", get_gpu_max_clk_level());
-}
-
-static ssize_t max_freq_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pmali_plat->cfg_clock) || (val < pinfo->minclk))
- return -EINVAL;
-
- pmali_plat->maxclk_sysfs = val;
- pinfo->maxclk = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t min_freq_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- return sprintf(buf, "%d\n", pmali_plat->scale_info.minclk);
-}
-
-static ssize_t min_freq_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pinfo->maxclk))
- return -EINVAL;
-
- pinfo->minclk = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t freq_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- return sprintf(buf, "%d\n", get_current_frequency());
-}
-
-static ssize_t freq_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- u32 clk, pp;
- get_mali_rt_clkpp(&clk, &pp);
-
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- return -EINVAL;
-
- set_mali_rt_clkpp(val, pp, 1);
-
- return count;
-}
-
-static ssize_t current_pp_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- u32 clk, pp;
- get_mali_rt_clkpp(&clk, &pp);
- return sprintf(buf, "%d\n", pp);
-}
-
-static ssize_t current_pp_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- u32 clk, pp;
-
- get_mali_rt_clkpp(&clk, &pp);
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- {
- return -EINVAL;
- }
-
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- return -EINVAL;
-
- set_mali_rt_clkpp(clk, val, 1);
-
- return count;
-}
-
-static struct class_attribute mali_class_attrs[] = {
- __ATTR(domain_stat, 0644, domain_stat_read, NULL),
- __ATTR(mpgpucmd, 0644, NULL, mpgpu_write),
- __ATTR(scale_mode, 0644, scale_mode_read, scale_mode_write),
- __ATTR(min_freq, 0644, min_freq_read, min_freq_write),
- __ATTR(max_freq, 0644, max_freq_read, max_freq_write),
- __ATTR(min_pp, 0644, min_pp_read, min_pp_write),
- __ATTR(max_pp, 0644, max_pp_read, max_pp_write),
- __ATTR(cur_freq, 0644, freq_read, freq_write),
- __ATTR(cur_pp, 0644, current_pp_read, current_pp_write),
-};
-
-static struct class mpgpu_class = {
- .name = "mpgpu",
-};
-#endif
-
-int mpgpu_class_init(void)
-{
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
- int ret = 0;
- int i;
- int attr_num = ARRAY_SIZE(mali_class_attrs);
-
- ret = class_register(&mpgpu_class);
- if (ret) {
- printk(KERN_ERR "%s: class_register failed\n", __func__);
- return ret;
- }
- for (i = 0; i< attr_num; i++) {
- ret = class_create_file(&mpgpu_class, &mali_class_attrs[i]);
- if (ret) {
- printk(KERN_ERR "%d ST: class item failed to register\n", i);
- }
- }
- return ret;
-#else
- return 0;
-#endif
-}
-
-void mpgpu_class_exit(void)
-{
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
- class_unregister(&mpgpu_class);
-#endif
-}
-
+++ /dev/null
-/*
- * platform.c
- *
- * clock source setting and resource config
- *
- * Created on: Dec 4, 2013
- * Author: amlogic
- */
-
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/module.h> /* kernel module definitions */
-#include <linux/ioport.h> /* request_mem_region */
-#include <linux/slab.h>
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#endif
-#include <asm/io.h>
-#include <linux/mali/mali_utgard.h>
-#ifdef CONFIG_GPU_THERMAL
-#include <linux/gpu_cooling.h>
-#include <linux/gpucore_cooling.h>
-#ifdef CONFIG_DEVFREQ_THERMAL
-#include <linux/amlogic/aml_thermal_hw.h>
-#include <common/mali_ukk.h>
-#endif
-#endif
-#include <common/mali_kernel_common.h>
-#include <common/mali_osk_profiling.h>
-#include <common/mali_pmu.h>
-
-#include "mali_scaling.h"
-#include "mali_clock.h"
-#include "meson_main.h"
-#include "mali_executor.h"
-
-/*
- * For Meson 8 M2.
- *
- */
-static void mali_plat_preheat(void);
-static mali_plat_info_t mali_plat_data = {
- .bst_gpu = 210, /* threshold for boosting gpu. */
- .bst_pp = 160, /* threshold for boosting PP. */
- .have_switch = 1,
- .limit_on = 1,
- .plat_preheat = mali_plat_preheat,
-};
-
-static void mali_plat_preheat(void)
-{
-#ifndef CONFIG_MALI_DVFS
- u32 pre_fs;
- u32 clk, pp;
-
- if (get_mali_schel_mode() != MALI_PP_FS_SCALING)
- return;
-
- get_mali_rt_clkpp(&clk, &pp);
- pre_fs = mali_plat_data.def_clock + 1;
- if (clk < pre_fs)
- clk = pre_fs;
- if (pp < mali_plat_data.sc_mpp)
- pp = mali_plat_data.sc_mpp;
- set_mali_rt_clkpp(clk, pp, 1);
-#endif
-}
-
-mali_plat_info_t* get_mali_plat_data(void) {
- return &mali_plat_data;
-}
-
-int get_mali_freq_level(int freq)
-{
- int i = 0, level = -1;
- int mali_freq_num;
-
- if (freq < 0)
- return level;
-
- mali_freq_num = mali_plat_data.dvfs_table_size - 1;
- if (freq < mali_plat_data.clk_sample[0])
- level = mali_freq_num-1;
- else if (freq >= mali_plat_data.clk_sample[mali_freq_num - 1])
- level = 0;
- else {
- for (i=0; i<mali_freq_num - 1 ;i++) {
- if (freq >= mali_plat_data.clk_sample[i] && freq < mali_plat_data.clk_sample[i + 1]) {
- level = i;
- level = mali_freq_num-level - 1;
- break;
- }
- }
- }
- return level;
-}
-
-unsigned int get_mali_max_level(void)
-{
- return mali_plat_data.dvfs_table_size - 1;
-}
-
-int get_gpu_max_clk_level(void)
-{
- return mali_plat_data.cfg_clock;
-}
-
-#ifdef CONFIG_GPU_THERMAL
-static void set_limit_mali_freq(u32 idx)
-{
- if (mali_plat_data.limit_on == 0)
- return;
- if (idx > mali_plat_data.turbo_clock || idx < mali_plat_data.scale_info.minclk)
- return;
- if (idx > mali_plat_data.maxclk_sysfs) {
- printk("idx > max freq\n");
- return;
- }
- mali_plat_data.scale_info.maxclk= idx;
- revise_mali_rt();
-}
-
-static u32 get_limit_mali_freq(void)
-{
- return mali_plat_data.scale_info.maxclk;
-}
-
-#ifdef CONFIG_DEVFREQ_THERMAL
-static u32 get_mali_utilization(void)
-{
- return (_mali_ukk_utilization_pp() * 100) / 256;
-}
-#endif
-#endif
-
-#ifdef CONFIG_GPU_THERMAL
-static u32 set_limit_pp_num(u32 num)
-{
- u32 ret = -1;
- if (mali_plat_data.limit_on == 0)
- goto quit;
- if (num > mali_plat_data.cfg_pp ||
- num < mali_plat_data.scale_info.minpp)
- goto quit;
-
- if (num > mali_plat_data.maxpp_sysfs) {
- printk("pp > sysfs set pp\n");
- goto quit;
- }
-
- mali_plat_data.scale_info.maxpp = num;
- revise_mali_rt();
- ret = 0;
-quit:
- return ret;
-}
-#ifdef CONFIG_DEVFREQ_THERMAL
-static u32 mali_get_online_pp(void)
-{
- unsigned int val;
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
-
- val = readl(pmali_plat->reg_base_aobus + 0xf0) & 0xff;
- if (val == 0x07) /* No pp is working */
- return 0;
-
- return mali_executor_get_num_cores_enabled();
-}
-#endif
-#endif
-
-void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data);
-int mali_meson_init_start(struct platform_device* ptr_plt_dev)
-{
- dev_set_drvdata(&ptr_plt_dev->dev, &mali_plat_data);
- mali_dt_info(ptr_plt_dev, &mali_plat_data);
- mali_clock_init_clk_tree(ptr_plt_dev);
- return 0;
-}
-
-int mali_meson_init_finish(struct platform_device* ptr_plt_dev)
-{
- if (mali_core_scaling_init(&mali_plat_data) < 0)
- return -1;
- return 0;
-}
-
-int mali_meson_uninit(struct platform_device* ptr_plt_dev)
-{
- mali_core_scaling_term();
- return 0;
-}
-
-static int mali_cri_light_suspend(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- mali_pm_statue = 1;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_suspend(device);
- }
- mali_pmu_power_down_all(pmu);
- return ret;
-}
-
-static int mali_cri_light_resume(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- mali_pmu_power_up_all(pmu);
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_resume(device);
- }
- mali_pm_statue = 0;
- return ret;
-}
-
-static int mali_cri_deep_suspend(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->suspend(device);
- }
- mali_pmu_power_down_all(pmu);
- return ret;
-}
-
-static int mali_cri_deep_resume(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- mali_pmu_power_up_all(pmu);
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->resume(device);
- }
- return ret;
-
-}
-
-int mali_light_suspend(struct device *device)
-{
- int ret = 0;
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- 0, 0, 0, 0, 0);
-#endif
-
- flush_scaling_job();
- /* clock scaling. Kasin..*/
- ret = mali_clock_critical(mali_cri_light_suspend, (size_t)device);
- disable_clock();
- return ret;
-}
-
-int mali_light_resume(struct device *device)
-{
- int ret = 0;
- enable_clock();
- ret = mali_clock_critical(mali_cri_light_resume, (size_t)device);
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- get_current_frequency(), 0, 0, 0, 0);
-#endif
- return ret;
-}
-
-int mali_deep_suspend(struct device *device)
-{
- int ret = 0;
-
- mali_pm_statue = 1;
- flush_scaling_job();
-
-
- /* clock scaling off. Kasin... */
- ret = mali_clock_critical(mali_cri_deep_suspend, (size_t)device);
- disable_clock();
- return ret;
-}
-
-int mali_deep_resume(struct device *device)
-{
- int ret = 0;
-
- /* clock scaling up. Kasin.. */
- enable_clock();
- ret = mali_clock_critical(mali_cri_deep_resume, (size_t)device);
- mali_pm_statue = 0;
- return ret;
-
-}
-
-void mali_post_init(void)
-{
-#ifdef CONFIG_GPU_THERMAL
- int err;
- struct gpufreq_cooling_device *gcdev = NULL;
- struct gpucore_cooling_device *gccdev = NULL;
-
- gcdev = gpufreq_cooling_alloc();
- register_gpu_freq_info(get_current_frequency);
- if (IS_ERR(gcdev))
- printk("malloc gpu cooling buffer error!!\n");
- else if (!gcdev)
- printk("system does not enable thermal driver\n");
- else {
- gcdev->get_gpu_freq_level = get_mali_freq_level;
- gcdev->get_gpu_max_level = get_mali_max_level;
- gcdev->set_gpu_freq_idx = set_limit_mali_freq;
- gcdev->get_gpu_current_max_level = get_limit_mali_freq;
-#ifdef CONFIG_DEVFREQ_THERMAL
- gcdev->get_gpu_freq = get_mali_freq;
- gcdev->get_gpu_loading = get_mali_utilization;
- gcdev->get_online_pp = mali_get_online_pp;
-#endif
- err = gpufreq_cooling_register(gcdev);
-#ifdef CONFIG_DEVFREQ_THERMAL
- aml_thermal_min_update(gcdev->cool_dev);
-#endif
- if (err < 0)
- printk("register GPU cooling error\n");
- printk("gpu cooling register okay with err=%d\n",err);
- }
-
- gccdev = gpucore_cooling_alloc();
- if (IS_ERR(gccdev))
- printk("malloc gpu core cooling buffer error!!\n");
- else if (!gccdev)
- printk("system does not enable thermal driver\n");
- else {
- gccdev->max_gpu_core_num=mali_plat_data.cfg_pp;
- gccdev->set_max_pp_num=set_limit_pp_num;
- err = (int)gpucore_cooling_register(gccdev);
-#ifdef CONFIG_DEVFREQ_THERMAL
- aml_thermal_min_update(gccdev->cool_dev);
-#endif
- if (err < 0)
- printk("register GPU cooling error\n");
- printk("gpu core cooling register okay with err=%d\n",err);
- }
-#endif
-}
+++ /dev/null
-/*
- * Copyright (C) 2013 ARM Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
- *
- * A copy of the licence is included with the program, and can also be obtained from Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-/**
- * @file arm_core_scaling.c
- * Example core scaling policy.
- */
-
-#include <linux/version.h>
-#include <linux/module.h>
-#include <linux/workqueue.h>
-#include <linux/mali/mali_utgard.h>
-#include <mali_kernel_common.h>
-#include <mali_osk_profiling.h>
-
-#if AMLOGIC_GPU_USE_GPPLL
-#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 16)
-#include <linux/amlogic/amports/gp_pll.h>
-#else
-#include <linux/amlogic/media/clk/gp_pll.h>
-#endif
-#endif
-#define LOG_MALI_SCALING 1
-#include "meson_main2.h"
-#include "mali_clock.h"
-
-static int currentStep;
-#ifndef CONFIG_MALI_DVFS
-static int num_cores_enabled;
-static int lastStep;
-static struct work_struct wq_work;
-static mali_plat_info_t* pmali_plat = NULL;
-#endif
-static int scaling_mode = MALI_PP_FS_SCALING;
-//static int scaling_mode = MALI_SCALING_DISABLE;
-//static int scaling_mode = MALI_PP_SCALING;
-
-#if AMLOGIC_GPU_USE_GPPLL
-static struct gp_pll_user_handle_s *gp_pll_user_gpu;
-static int is_gp_pll_get;
-static int is_gp_pll_put;
-#endif
-
-static unsigned scaling_dbg_level = 0;
-module_param(scaling_dbg_level, uint, 0644);
-MODULE_PARM_DESC(scaling_dbg_level , "scaling debug level");
-
-#define scalingdbg(level, fmt, arg...) \
- do { \
- if (scaling_dbg_level >= (level)) \
- printk(fmt , ## arg); \
- } while (0)
-
-#ifndef CONFIG_MALI_DVFS
-static inline void mali_clk_exected(void)
-{
- mali_dvfs_threshold_table * pdvfs = pmali_plat->dvfs_table;
- uint32_t execStep = currentStep;
-#if AMLOGIC_GPU_USE_GPPLL
- mali_dvfs_threshold_table *dvfs_tbl = &pmali_plat->dvfs_table[currentStep];
-#endif
-
- //if (pdvfs[currentStep].freq_index == pdvfs[lastStep].freq_index) return;
- if ((pdvfs[execStep].freq_index == pdvfs[lastStep].freq_index) ||
- (pdvfs[execStep].clk_freq == pdvfs[lastStep].clk_freq)){
- return;
- }
-
-#if AMLOGIC_GPU_USE_GPPLL
- if (0 == strcmp(dvfs_tbl->clk_parent, "gp0_pll")) {
- gp_pll_request(gp_pll_user_gpu);
- if (!is_gp_pll_get) {
- //printk("not get pll\n");
- execStep = currentStep - 1;
- }
- } else {
- //not get the gp pll, do need put
- is_gp_pll_get = 0;
- is_gp_pll_put = 0;
- gp_pll_release(gp_pll_user_gpu);
- }
-#endif
-
- //mali_dev_pause();
- mali_clock_set(pdvfs[execStep].freq_index);
- //mali_dev_resume();
- lastStep = execStep;
-#if AMLOGIC_GPU_USE_GPPLL
- if (is_gp_pll_put) {
- //printk("release gp0 pll\n");
- gp_pll_release(gp_pll_user_gpu);
- gp_pll_request(gp_pll_user_gpu);
- is_gp_pll_get = 0;
- is_gp_pll_put = 0;
- }
-#endif
-
-}
-#if AMLOGIC_GPU_USE_GPPLL
-static int gp_pll_user_cb_gpu(struct gp_pll_user_handle_s *user,
- int event)
-{
- if (event == GP_PLL_USER_EVENT_GRANT) {
- //printk("granted\n");
- is_gp_pll_get = 1;
- is_gp_pll_put = 0;
- schedule_work(&wq_work);
- } else if (event == GP_PLL_USER_EVENT_YIELD) {
- //printk("ask for yield\n");
- is_gp_pll_get = 0;
- is_gp_pll_put = 1;
- schedule_work(&wq_work);
- }
-
- return 0;
-}
-#endif
-
-static void do_scaling(struct work_struct *work)
-{
- mali_dvfs_threshold_table * pdvfs = pmali_plat->dvfs_table;
- int err = mali_perf_set_num_pp_cores(num_cores_enabled);
- scalingdbg(1, "set pp cores to %d\n", num_cores_enabled);
- MALI_DEBUG_ASSERT(0 == err);
- MALI_IGNORE(err);
- scalingdbg(1, "pdvfs[%d].freq_index=%d, pdvfs[%d].freq_index=%d\n",
- currentStep, pdvfs[currentStep].freq_index,
- lastStep, pdvfs[lastStep].freq_index);
- mali_clk_exected();
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- get_current_frequency(),
- 0, 0, 0, 0);
-#endif
-}
-#endif
-
-u32 revise_set_clk(u32 val, u32 flush)
-{
- u32 ret = 0;
-#ifndef CONFIG_MALI_DVFS
- mali_scale_info_t* pinfo;
-
- pinfo = &pmali_plat->scale_info;
-
- if (val < pinfo->minclk)
- val = pinfo->minclk;
- else if (val > pinfo->maxclk)
- val = pinfo->maxclk;
-
- if (val != currentStep) {
- currentStep = val;
- if (flush)
- schedule_work(&wq_work);
- else
- ret = 1;
- }
-#endif
- return ret;
-}
-
-void get_mali_rt_clkpp(u32* clk, u32* pp)
-{
-#ifndef CONFIG_MALI_DVFS
- *clk = currentStep;
- *pp = num_cores_enabled;
-#endif
-}
-
-u32 set_mali_rt_clkpp(u32 clk, u32 pp, u32 flush)
-{
- u32 ret = 0;
-#ifndef CONFIG_MALI_DVFS
- mali_scale_info_t* pinfo;
- u32 flush_work = 0;
-
- pinfo = &pmali_plat->scale_info;
- if (clk < pinfo->minclk)
- clk = pinfo->minclk;
- else if (clk > pinfo->maxclk)
- clk = pinfo->maxclk;
-
- if (clk != currentStep) {
- currentStep = clk;
- if (flush)
- flush_work++;
- else
- ret = 1;
- }
- if (pp < pinfo->minpp)
- pp = pinfo->minpp;
- else if (pp > pinfo->maxpp)
- pp = pinfo->maxpp;
-
- if (pp != num_cores_enabled) {
- num_cores_enabled = pp;
- if (flush)
- flush_work++;
- else
- ret = 1;
- }
-
- if (flush_work)
- schedule_work(&wq_work);
-#endif
- return ret;
-}
-
-void revise_mali_rt(void)
-{
-#ifndef CONFIG_MALI_DVFS
- set_mali_rt_clkpp(currentStep, num_cores_enabled, 1);
-#endif
-}
-
-void flush_scaling_job(void)
-{
-#ifndef CONFIG_MALI_DVFS
- cancel_work_sync(&wq_work);
-#endif
-}
-
-#ifndef CONFIG_MALI_DVFS
-static u32 enable_one_core(void)
-{
- scalingdbg(2, "meson: one more pp, curent has %d pp cores\n", num_cores_enabled + 1);
- return set_mali_rt_clkpp(currentStep, num_cores_enabled + 1, 0);
-}
-
-static u32 disable_one_core(void)
-{
- scalingdbg(2, "meson: disable one pp, current has %d pp cores\n", num_cores_enabled - 1);
- return set_mali_rt_clkpp(currentStep, num_cores_enabled - 1, 0);
-}
-
-static u32 enable_max_num_cores(void)
-{
- return set_mali_rt_clkpp(currentStep, pmali_plat->scale_info.maxpp, 0);
-}
-
-static u32 enable_pp_cores(u32 val)
-{
- scalingdbg(2, "meson: enable %d pp cores\n", val);
- return set_mali_rt_clkpp(currentStep, val, 0);
-}
-#endif
-
-int mali_core_scaling_init(mali_plat_info_t *mali_plat)
-{
-#ifndef CONFIG_MALI_DVFS
- if (mali_plat == NULL) {
- scalingdbg(2, " Mali platform data is NULL!!!\n");
- return -1;
- }
-
- pmali_plat = mali_plat;
- num_cores_enabled = pmali_plat->sc_mpp;
-#if AMLOGIC_GPU_USE_GPPLL
- gp_pll_user_gpu = gp_pll_user_register("gpu", 1,
- gp_pll_user_cb_gpu);
- //not get the gp pll, do need put
- is_gp_pll_get = 0;
- is_gp_pll_put = 0;
- if (gp_pll_user_gpu == NULL) printk("register gp pll user for gpu failed\n");
-#endif
-
- currentStep = pmali_plat->def_clock;
- lastStep = currentStep;
- INIT_WORK(&wq_work, do_scaling);
-#endif
- return 0;
- /* NOTE: Mali is not fully initialized at this point. */
-}
-
-void mali_core_scaling_term(void)
-{
-#ifndef CONFIG_MALI_DVFS
- flush_scheduled_work();
-#if AMLOGIC_GPU_USE_GPPLL
- gp_pll_user_unregister(gp_pll_user_gpu);
-#endif
-#endif
-}
-
-#ifndef CONFIG_MALI_DVFS
-static u32 mali_threshold [] = {
- 102, /* 40% */
- 128, /* 50% */
- 230, /* 90% */
-};
-#endif
-
-void mali_pp_scaling_update(struct mali_gpu_utilization_data *data)
-{
-#ifndef CONFIG_MALI_DVFS
- int ret = 0;
-
- if (mali_threshold[2] < data->utilization_pp)
- ret = enable_max_num_cores();
- else if (mali_threshold[1]< data->utilization_pp)
- ret = enable_one_core();
- else if (0 < data->utilization_pp)
- ret = disable_one_core();
- if (ret == 1)
- schedule_work(&wq_work);
-#endif
-}
-
-#if LOG_MALI_SCALING
-void trace_utilization(struct mali_gpu_utilization_data *data, u32 current_idx, u32 next,
- u32 current_pp, u32 next_pp)
-{
- char direction;
- if (next > current_idx)
- direction = '>';
- else if ((current_idx > pmali_plat->scale_info.minpp) && (next < current_idx))
- direction = '<';
- else
- direction = '~';
-
- scalingdbg(2, "[SCALING]%c (%3d-->%3d)@%3d{%3d - %3d}. pp:(%d-->%d)\n",
- direction,
- get_mali_freq(current_idx),
- get_mali_freq(next),
- data->utilization_gpu,
- pmali_plat->dvfs_table[current_idx].downthreshold,
- pmali_plat->dvfs_table[current_idx].upthreshold,
- current_pp, next_pp);
-}
-#endif
-
-#ifndef CONFIG_MALI_DVFS
-static int mali_stay_count = 0;
-static void mali_decide_next_status(struct mali_gpu_utilization_data *data, int* next_fs_idx,
- int* pp_change_flag)
-{
- u32 utilization, mali_up_limit, decided_fs_idx;
- u32 ld_left, ld_right;
- u32 ld_up, ld_down;
- u32 change_mode;
-
- *pp_change_flag = 0;
- change_mode = 0;
- utilization = data->utilization_gpu;
-
- scalingdbg(5, "line(%d), scaling_mode=%d, MALI_TURBO_MODE=%d, turbo=%d, maxclk=%d\n",
- __LINE__, scaling_mode, MALI_TURBO_MODE,
- pmali_plat->turbo_clock, pmali_plat->scale_info.maxclk);
-
- mali_up_limit = (scaling_mode == MALI_TURBO_MODE) ?
- pmali_plat->turbo_clock : pmali_plat->scale_info.maxclk;
- decided_fs_idx = currentStep;
-
- ld_up = pmali_plat->dvfs_table[currentStep].upthreshold;
- ld_down = pmali_plat->dvfs_table[currentStep].downthreshold;
-
- scalingdbg(2, "utilization=%d, ld_up=%d\n ", utilization, ld_up);
- if (utilization >= ld_up) { /* go up */
-
- scalingdbg(2, "currentStep=%d, mali_up_limit=%d\n ", currentStep, mali_up_limit);
- if (currentStep < mali_up_limit) {
- change_mode = 1;
- if ((currentStep < pmali_plat->def_clock) && (utilization > pmali_plat->bst_gpu))
- decided_fs_idx = pmali_plat->def_clock;
- else
- decided_fs_idx++;
- }
- if ((data->utilization_pp >= ld_up) &&
- (num_cores_enabled < pmali_plat->scale_info.maxpp)) {
- if ((num_cores_enabled < pmali_plat->sc_mpp) && (data->utilization_pp >= pmali_plat->bst_pp)) {
- *pp_change_flag = 1;
- change_mode = 1;
- } else if (change_mode == 0) {
- *pp_change_flag = 2;
- change_mode = 1;
- }
- }
-#if LOG_MALI_SCALING
- scalingdbg(2, "[nexting..] [LD:%d]-> FS[CRNT:%d LMT:%d NEXT:%d] PP[NUM:%d LMT:%d MD:%d][F:%d]\n",
- data->utilization_pp, currentStep, mali_up_limit, decided_fs_idx,
- num_cores_enabled, pmali_plat->scale_info.maxpp, *pp_change_flag, change_mode);
-#endif
- } else if (utilization <= ld_down) { /* go down */
- if (mali_stay_count > 0) {
- *next_fs_idx = decided_fs_idx;
- mali_stay_count--;
- return;
- }
-
- if (num_cores_enabled > pmali_plat->sc_mpp) {
- change_mode = 1;
- if (data->utilization_pp <= ld_down) {
- ld_left = data->utilization_pp * num_cores_enabled;
- ld_right = (pmali_plat->dvfs_table[currentStep].upthreshold) *
- (num_cores_enabled - 1);
- if (ld_left < ld_right) {
- change_mode = 2;
- }
- }
- } else if (currentStep > pmali_plat->scale_info.minclk) {
- change_mode = 1;
- } else if (num_cores_enabled > 1) { /* decrease PPS */
- if (data->utilization_pp <= ld_down) {
- ld_left = data->utilization_pp * num_cores_enabled;
- ld_right = (pmali_plat->dvfs_table[currentStep].upthreshold) *
- (num_cores_enabled - 1);
- scalingdbg(2, "ld_left=%d, ld_right=%d\n", ld_left, ld_right);
- if (ld_left < ld_right) {
- change_mode = 2;
- }
- }
- }
-
- if (change_mode == 1) {
- decided_fs_idx--;
- } else if (change_mode == 2) { /* decrease PPS */
- *pp_change_flag = -1;
- }
- }
-
- if (decided_fs_idx < 0 ) {
- printk("gpu debug, next index below 0\n");
- decided_fs_idx = 0;
- }
- if (decided_fs_idx > pmali_plat->scale_info.maxclk) {
- decided_fs_idx = pmali_plat->scale_info.maxclk;
- printk("gpu debug, next index above max, set to %d\n", decided_fs_idx);
- }
-
- if (change_mode)
- mali_stay_count = pmali_plat->dvfs_table[decided_fs_idx].keep_count;
- *next_fs_idx = decided_fs_idx;
-}
-#endif
-
-void mali_pp_fs_scaling_update(struct mali_gpu_utilization_data *data)
-{
-#ifndef CONFIG_MALI_DVFS
- int ret = 0;
- int pp_change_flag = 0;
- u32 next_idx = 0;
-
-#if LOG_MALI_SCALING
- u32 last_pp = num_cores_enabled;
-#endif
- mali_decide_next_status(data, &next_idx, &pp_change_flag);
-
- if (pp_change_flag == 1)
- ret = enable_pp_cores(pmali_plat->sc_mpp);
- else if (pp_change_flag == 2)
- ret = enable_one_core();
- else if (pp_change_flag == -1) {
- ret = disable_one_core();
- }
-
-#if LOG_MALI_SCALING
- if (pp_change_flag || (next_idx != currentStep))
- trace_utilization(data, currentStep, next_idx, last_pp, num_cores_enabled);
-#endif
-
- if (next_idx != currentStep) {
- ret = 1;
- currentStep = next_idx;
- }
-
- if (ret == 1)
- schedule_work(&wq_work);
-#ifdef CONFIG_MALI400_PROFILING
- else
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- get_current_frequency(),
- 0, 0, 0, 0);
-#endif
-#endif
-}
-
-u32 get_mali_schel_mode(void)
-{
- return scaling_mode;
-}
-
-void set_mali_schel_mode(u32 mode)
-{
-#ifndef CONFIG_MALI_DVFS
- MALI_DEBUG_ASSERT(mode < MALI_SCALING_MODE_MAX);
- if (mode >= MALI_SCALING_MODE_MAX)
- return;
- scaling_mode = mode;
-
- //disable thermal in turbo mode
- if (scaling_mode == MALI_TURBO_MODE) {
- pmali_plat->limit_on = 0;
- } else {
- pmali_plat->limit_on = 1;
- }
- /* set default performance range. */
- pmali_plat->scale_info.minclk = pmali_plat->cfg_min_clock;
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- pmali_plat->scale_info.minpp = pmali_plat->cfg_min_pp;
- pmali_plat->scale_info.maxpp = pmali_plat->cfg_pp;
-
- /* set current status and tune max freq */
- if (scaling_mode == MALI_PP_FS_SCALING) {
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- enable_pp_cores(pmali_plat->sc_mpp);
- } else if (scaling_mode == MALI_SCALING_DISABLE) {
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- enable_max_num_cores();
- } else if (scaling_mode == MALI_TURBO_MODE) {
- pmali_plat->scale_info.maxclk = pmali_plat->turbo_clock;
- enable_max_num_cores();
- }
- currentStep = pmali_plat->scale_info.maxclk;
- schedule_work(&wq_work);
-#endif
-}
-
-u32 get_current_frequency(void)
-{
- return get_mali_freq(currentStep);
-}
-
-void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data)
-{
-#ifndef CONFIG_MALI_DVFS
- if (mali_pm_statue)
- return;
-
- switch (scaling_mode) {
- case MALI_PP_FS_SCALING:
- mali_pp_fs_scaling_update(data);
- break;
- case MALI_PP_SCALING:
- mali_pp_scaling_update(data);
- break;
- default:
- break;
- }
-#endif
-}
-static u32 clk_cntl_save = 0;
-void mali_dev_freeze(void)
-{
- clk_cntl_save = mplt_read(HHI_MALI_CLK_CNTL);
-}
-
-void mali_dev_restore(void)
-{
-
- mplt_write(HHI_MALI_CLK_CNTL, clk_cntl_save);
- if (pmali_plat && pmali_plat->pdev) {
- mali_clock_init_clk_tree(pmali_plat->pdev);
- } else {
- printk("error: init clock failed, pmali_plat=%p, pmali_plat->pdev=%p\n",
- pmali_plat, pmali_plat == NULL ? NULL: pmali_plat->pdev);
- }
-}
-
-int mali_meson_get_gpu_data(struct mali_gpu_device_data *mgpu_data)
-{
- mgpu_data->get_clock_info = NULL;
- mgpu_data->get_freq = NULL;
- mgpu_data->set_freq = NULL;
- mgpu_data->utilization_callback = mali_gpu_utilization_callback;
- return 0;
-}
+++ /dev/null
-/*
- * AMLOGIC Mali fix driver.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the named License,
- * or any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
- *
- * Author: Tim Yao <timyao@amlogic.com>
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/timer.h>
-#include <asm/io.h>
-#include <linux/ioport.h>
-#include <linux/dma-mapping.h>
-
-#include <linux/module.h>
-
-#include <mach/am_regs.h>
-#include <mach/clock.h>
-#include <linux/io.h>
-#include <mach/io.h>
-#include <plat/io.h>
-#include <asm/io.h>
-
-#include "mali_kernel_common.h"
-#include "mali_osk.h"
-#include "mali_platform.h"
-#include "mali_fix.h"
-
-#define MALI_MM1_REG_ADDR 0xd0064000
-#define MALI_MMU_REGISTER_INT_STATUS 0x0008
-#define MALI_MM2_REG_ADDR 0xd0065000
-#define MALI_MMU_REGISTER_INT_STATUS 0x0008
-#define MALI_MM_REG_SIZE 0x1000
-
-#define READ_MALI_MMU1_REG(r) (ioread32(((u8*)mali_mm1_regs) + r))
-#define READ_MALI_MMU2_REG(r) (ioread32(((u8*)mali_mm2_regs) + r))
-
-extern int mali_PP0_int_cnt(void);
-extern int mali_PP1_int_cnt(void);
-
-#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
-static ulong * mali_mm1_regs = NULL;
-static ulong * mali_mm2_regs = NULL;
-static struct timer_list timer;
-
-static u32 mali_pp1_int_count = 0;
-static u32 mali_pp2_int_count = 0;
-static u32 mali_pp1_mmu_int_count = 0;
-static u32 mali_pp2_mmu_int_count = 0;
-static u32 mali_mmu_int_process_state[2];
-
-static void timer_callback(ulong data)
-{
- unsigned long mali_flags;
-
- mali_pp1_int_count = mali_PP0_int_cnt();
- mali_pp2_int_count = mali_PP1_int_cnt();
-
- /* lock mali_clock_gating when access Mali registers */
- mali_flags = mali_clock_gating_lock();
-
- if (readl((u32 *)P_HHI_MALI_CLK_CNTL) & 0x100) {
- /* polling for PP1 MMU interrupt */
- if (mali_mmu_int_process_state[0] == MMU_INT_NONE) {
- if (READ_MALI_MMU1_REG(MALI_MMU_REGISTER_INT_STATUS) != 0) {
- mali_pp1_mmu_int_count++;
- MALI_DEBUG_PRINT(3, ("Mali MMU: core0 page fault emit \n"));
- mali_mmu_int_process_state[0] = MMU_INT_HIT;
- __raw_writel(1, (volatile void *)P_ISA_TIMERC);
- }
- }
-
- /* polling for PP2 MMU interrupt */
- if (mali_mmu_int_process_state[1] == MMU_INT_NONE) {
- if (READ_MALI_MMU2_REG(MALI_MMU_REGISTER_INT_STATUS) != 0) {
- mali_pp2_mmu_int_count++;
- MALI_DEBUG_PRINT(3, ("Mali MMU: core1 page fault emit \n"));
- mali_mmu_int_process_state[1] = MMU_INT_HIT;
- __raw_writel(1, (volatile void *)P_ISA_TIMERC);
- }
- }
- }
-
- mali_clock_gating_unlock(mali_flags);
-
- timer.expires = jiffies + HZ/100;
-
- add_timer(&timer);
-}
-
-void malifix_set_mmu_int_process_state(int index, int state)
-{
- if (index < 2)
- mali_mmu_int_process_state[index] = state;
-}
-
-int malifix_get_mmu_int_process_state(int index)
-{
- if (index < 2)
- return mali_mmu_int_process_state[index];
- return 0;
-}
-#endif
-
-void malifix_init(void)
-{
-#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
- if (!mali_meson_is_revb())
- return;
-
- if ((mali_mm1_regs) && (mali_mm2_regs)) return;
- mali_mmu_int_process_state[0] = 0;
- mali_mmu_int_process_state[1] = 0;
-
- /* set up Timer C as a 1uS one-shot timer */
- aml_clr_reg32_mask(P_ISA_TIMER_MUX, (1<<18)|(1<<14)|(3<<4));
- aml_set_reg32_mask(P_ISA_TIMER_MUX, (1<<18)|(0<<14)|(0<<4));
-
- setup_timer(&timer, timer_callback, 0);
-
- mali_mm1_regs = (ulong *)ioremap_nocache(MALI_MM1_REG_ADDR, MALI_MM_REG_SIZE);
- if (mali_mm1_regs)
- printk("Mali pp1 MMU register mapped at %p...\n", mali_mm1_regs);
-
- mali_mm2_regs = (ulong *)ioremap_nocache(MALI_MM2_REG_ADDR, MALI_MM_REG_SIZE);
- if (mali_mm2_regs)
- printk("Mali pp2 MMU register mapped at %p...\n", mali_mm2_regs);
-
- if ((mali_mm1_regs != NULL) && (mali_mm2_regs != NULL))
- mod_timer(&timer, jiffies + HZ/100);
-#endif
-}
-
-void malifix_exit(void)
-{
-#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
- if (!mali_meson_is_revb())
- return;
-
- del_timer(&timer);
-
- if (mali_mm1_regs != NULL)
- iounmap(mali_mm1_regs);
- mali_mm1_regs = NULL;
-
- if (mali_mm2_regs != NULL)
- iounmap(mali_mm2_regs);
- mali_mm2_regs = NULL;
-
-#endif
- return;
-}
-
-#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
-module_param(mali_pp1_int_count, uint, 0664);
-MODULE_PARM_DESC(mali_pp1_int_count, "Mali PP1 interrupt count\n");
-
-module_param(mali_pp2_int_count, uint, 0664);
-MODULE_PARM_DESC(mali_pp2_int_count, "Mali PP1 interrupt count\n");
-
-module_param(mali_pp1_mmu_int_count, uint, 0664);
-MODULE_PARM_DESC(mali_pp1_mmu_int_count, "Mali PP1 mmu interrupt count\n");
-
-module_param(mali_pp2_mmu_int_count, uint, 0664);
-MODULE_PARM_DESC(mali_pp2_mmu_int_count, "Mali PP2 mmu interrupt count\n");
-#endif
-
-MODULE_DESCRIPTION("AMLOGIC mali fix driver");
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Tim Yao <timyao@amlogic.com>");
+++ /dev/null
-#ifndef MALI_FIX_H
-#define MALI_FIX_H
-
-#define MMU_INT_NONE 0
-#define MMU_INT_HIT 1
-#define MMU_INT_TOP 2
-#define MMU_INT_BOT 3
-
-extern void malifix_init(void);
-extern void malifix_exit(void);
-extern void malifix_set_mmu_int_process_state(int, int);
-extern int malifix_get_mmu_int_process_state(int);
-extern int mali_meson_is_revb(void);
-#endif /* MALI_FIX_H */
+++ /dev/null
-/*
- * This confidential and proprietary software may be used only as
- * authorised by a licensing agreement from AMLOGIC, INC.
- * (C) COPYRIGHT 2011 AMLOGIC, INC.
- * ALL RIGHTS RESERVED
- * The entire notice above must be reproduced on all authorised
- * copies and copies may only be made to the extent permitted
- * by a licensing agreement from AMLOGIC, INC.
- */
-
-/**
- * @file mali_platform.c
- * Platform specific Mali driver functions for meson platform
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/dma-mapping.h>
-#include <linux/spinlock.h>
-#include <linux/spinlock_types.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <mach/am_regs.h>
-#include <mach/clock.h>
-
-#include "mali_kernel_common.h"
-#include "mali_osk.h"
-#include "mali_platform.h"
-#include "mali_poweron_reg.h"
-#include "mali_fix.h"
-#include "mali_platform.h"
-
-static int last_power_mode = -1;
-static int mali_init_flag = 0;
-static const u32 poweron_data[] =
-{
-/* commands */
-/* 000 */ 0x00000040, 0x20400000, 0x00000300, 0x30040000,
-/* 010 */ 0x00000400, 0x400a0000, 0x0f000033, 0x10000042,
-/* 020 */ 0x00300c00, 0x10000040, 0x4c000001, 0x00000000,
-/* 030 */ 0x00000000, 0x60000000, 0x00000000, 0x00000000,
-/* 040 */ 0x00004000, 0x00002000, 0x00000210, 0x0000203f,
-/* 050 */ 0x00000220, 0x0000203f, 0x00000230, 0x0000203f,
-/* 060 */ 0x00000240, 0x0000203f, 0x00000250, 0x0000203f,
-/* 070 */ 0x00000260, 0x0000203f, 0x00000270, 0x0000203f,
-/* 080 */ 0x00000280, 0x0000203f, 0x00000290, 0x0000203f,
-/* 090 */ 0x000002a0, 0x0000203f, 0x000002b0, 0x0000203f,
-/* 0a0 */ 0x000002c0, 0x0000203f, 0x000002d0, 0x0000203f,
-/* 0b0 */ 0x000002e0, 0x0000203f, 0x000002f0, 0x0000203f,
-/* 0c0 */ 0x00002000, 0x00002000, 0x00002010, 0x0000203f,
-/* 0d0 */ 0x00002020, 0x0000203f, 0x00002030, 0x0000203f,
-/* 0e0 */ 0x00002040, 0x0000203f, 0x00002050, 0x0000203f,
-/* 0f0 */ 0x00002060, 0x0000203f, 0x00002070, 0x0000203f,
-/* 100 */ 0x00002080, 0x0000203f, 0x00002090, 0x0000203f,
-/* 110 */ 0x000020a0, 0x0000203f, 0x000020b0, 0x0000203f,
-/* 120 */ 0x000020c0, 0x0000203f, 0x000020d0, 0x0000203f,
-/* 130 */ 0x000020e0, 0x0000203f, 0x000020f0, 0x0000203f,
-/* 140 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 150 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 160 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 170 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 180 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 190 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 1a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 1b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 1c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 1d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 1e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 1f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 200 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 210 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 220 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 230 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 240 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 250 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 260 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 270 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 280 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 290 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 2a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 2b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 2c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 2d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 2e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 2f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* const */
-/* 300 */ 0x3f2a6400, 0xbf317600, 0x3e8d8e00, 0x00000000,
-/* 310 */ 0x3f2f7000, 0x3f36e200, 0x3e10c500, 0x00000000,
-/* 320 */ 0xbe974e00, 0x3dc35300, 0x3f735800, 0x00000000,
-/* 330 */ 0x00000000, 0x00000000, 0x00000000, 0x3f800000,
-/* 340 */ 0x42b00000, 0x42dc0000, 0x3f800000, 0x3f800000,
-/* 350 */ 0x42b00000, 0x42dc0000, 0x00000000, 0x00000000,
-/* 360 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 370 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 380 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 390 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 3a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 3b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 3c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 3d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 3e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 3f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* inst */
-/* 400 */ 0xad4ad6b5, 0x438002b5, 0x0007ffe0, 0x00001e00,
-/* 410 */ 0xad4ad694, 0x038002b5, 0x0087ffe0, 0x00005030,
-/* 420 */ 0xad4bda56, 0x038002b5, 0x0007ffe0, 0x00001c10,
-/* 430 */ 0xad4ad6b5, 0x038002b5, 0x4007fee0, 0x00001c00
-};
-
-static struct clk *mali_clk = NULL;
-
-#if MESON_CPU_TYPE <= MESON_CPU_TYPE_MESON6
-
-#define OFFSET_MMU_DTE 0
-#define OFFSET_MMU_PTE 4096
-#define OFFSET_MMU_VIRTUAL_ZERO 8192
-
-#define INT_MALI_GP_BITS (1<<16)
-#define INT_MALI_PP_BITS (1<<18)
-#define INT_MALI_PP_MMU_BITS (1<<19)
-#define INT_ALL (0xffffffff)
-
-#define INT_MALI_PP_MMU_PAGE_FAULT (1<<0)
-
-#define MMU_FLAG_DTE_PRESENT 0x01
-#define MMU_FLAG_PTE_PAGE_PRESENT 0x01
-#define MMU_FLAG_PTE_RD_PERMISSION 0x02
-#define MMU_FLAG_PTE_WR_PERMISSION 0x04
-
-//static int mali_revb_flag = -1;
-static DEFINE_SPINLOCK(lock);
-extern int mali_revb_flag;
-int mali_meson_is_revb(void)
-{
- printk("mail version=%d\n",mali_revb_flag);
- if (mali_revb_flag == -1)
- mali_revb_flag = 1;
- else if (mali_revb_flag == 0)
- panic("rev-a! you should neet earlier version of mali_driver.!\n");
-
- return mali_revb_flag;
-}
-
-static void mali_meson_poweron(int first_poweron)
-{
- unsigned long flags;
- u32 p, p_aligned;
- dma_addr_t p_phy;
- int i;
- unsigned int_mask;
-
- if(!first_poweron) {
- if ((last_power_mode != -1) && (last_power_mode != MALI_POWER_MODE_DEEP_SLEEP)) {
- MALI_DEBUG_PRINT(3, ("Maybe your system not deep sleep now.......\n"));
- //printk("Maybe your system not deep sleep now.......\n");
- return;
- }
- }
-
- MALI_DEBUG_PRINT(2, ("mali_meson_poweron: Mali APB bus accessing\n"));
- if (READ_MALI_REG(MALI_PP_PP_VERSION) != MALI_PP_PP_VERSION_MAGIC) {
- MALI_DEBUG_PRINT(3, ("mali_meson_poweron: Mali APB bus access failed\n"));
- //printk("mali_meson_poweron: Mali APB bus access failed.");
- return;
- }
- MALI_DEBUG_PRINT(2, ("..........accessing done.\n"));
- if (READ_MALI_REG(MALI_MMU_DTE_ADDR) != 0) {
- MALI_DEBUG_PRINT(3, ("mali_meson_poweron: Mali is not really powered off\n"));
- //printk("mali_meson_poweron: Mali is not really powered off.");
- return;
- }
-
- p = (u32)kcalloc(4096 * 4, 1, GFP_KERNEL);
- if (!p) {
- printk("mali_meson_poweron: NOMEM in meson_poweron\n");
- return;
- }
-
- p_aligned = __ALIGN_MASK(p, 4096);
-
- /* DTE */
- *(u32 *)(p_aligned) = (virt_to_phys((void *)p_aligned) + OFFSET_MMU_PTE) | MMU_FLAG_DTE_PRESENT;
- /* PTE */
- for (i=0; i<1024; i++) {
- *(u32 *)(p_aligned + OFFSET_MMU_PTE + i*4) =
- (virt_to_phys((void *)p_aligned) + OFFSET_MMU_VIRTUAL_ZERO + 4096 * i) |
- MMU_FLAG_PTE_PAGE_PRESENT |
- MMU_FLAG_PTE_RD_PERMISSION;
- }
-
- /* command & data */
- memcpy((void *)(p_aligned + OFFSET_MMU_VIRTUAL_ZERO), poweron_data, 4096);
-
- p_phy = dma_map_single(NULL, (void *)p_aligned, 4096 * 3, DMA_TO_DEVICE);
-
- /* Set up Mali GP MMU */
- WRITE_MALI_REG(MALI_MMU_DTE_ADDR, p_phy);
- WRITE_MALI_REG(MALI_MMU_CMD, 0);
-
- if ((READ_MALI_REG(MALI_MMU_STATUS) & 1) != 1)
- printk("mali_meson_poweron: MMU enabling failed.\n");
-
- /* Set up Mali command registers */
- WRITE_MALI_REG(MALI_APB_GP_VSCL_START, 0);
- WRITE_MALI_REG(MALI_APB_GP_VSCL_END, 0x38);
-
- spin_lock_irqsave(&lock, flags);
-
- int_mask = READ_MALI_REG(MALI_APB_GP_INT_MASK);
- WRITE_MALI_REG(MALI_APB_GP_INT_CLEAR, 0x707bff);
- WRITE_MALI_REG(MALI_APB_GP_INT_MASK, 0);
-
- /* Start GP */
- WRITE_MALI_REG(MALI_APB_GP_CMD, 1);
-
- for (i = 0; i<100; i++)
- udelay(500);
-
- /* check Mali GP interrupt */
- if (READ_MALI_REG(MALI_APB_GP_INT_RAWSTAT) & 0x707bff)
- printk("mali_meson_poweron: Interrupt received.\n");
- else
- printk("mali_meson_poweron: No interrupt received.\n");
-
- /* force reset GP */
- WRITE_MALI_REG(MALI_APB_GP_CMD, 1 << 5);
-
- /* stop MMU paging and reset */
- WRITE_MALI_REG(MALI_MMU_CMD, 1);
- WRITE_MALI_REG(MALI_MMU_CMD, 6);
-
- for (i = 0; i<100; i++)
- udelay(500);
-
- WRITE_MALI_REG(MALI_APB_GP_INT_CLEAR, 0x3ff);
- WRITE_MALI_REG(MALI_MMU_INT_CLEAR, INT_ALL);
- WRITE_MALI_REG(MALI_MMU_INT_MASK, 0);
-
- WRITE_MALI_REG(MALI_APB_GP_INT_CLEAR, 0x707bff);
- WRITE_MALI_REG(MALI_APB_GP_INT_MASK, int_mask);
-
- spin_unlock_irqrestore(&lock, flags);
-
- dma_unmap_single(NULL, p_phy, 4096 * 3, DMA_TO_DEVICE);
-
- kfree((void *)p);
-
- /* Mali revision detection */
- if (last_power_mode == -1)
- mali_revb_flag = mali_meson_is_revb();
-}
-#else
-static void mali_meson_poweron(int first_poweron) {
- return;
-}
-#endif /*MESON_CPU_TYPE <= MESON_CPU_TYPE_MESON6 */
-
-_mali_osk_errcode_t mali_platform_init(void)
-{
- mali_clk = clk_get_sys("mali", "pll_fixed");
-
- if (mali_clk ) {
- if (!mali_init_flag) {
- clk_set_rate(mali_clk, 333000000);
- mali_clk->enable(mali_clk);
- malifix_init();
- mali_meson_poweron(1);
- mali_init_flag = 1;
- }
- MALI_SUCCESS;
- } else
- panic("linux kernel should > 3.0\n");
-
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6
- MALI_PRINT_ERROR(("Failed to lookup mali clock"));
- MALI_ERROR(_MALI_OSK_ERR_FAULT);
-#else
- MALI_SUCCESS;
-#endif /* CONFIG_ARCH_MESON6 */
-}
-
-_mali_osk_errcode_t mali_platform_deinit(void)
-{
- mali_init_flag =0;
- printk("MALI:mali_platform_deinit\n");
- malifix_exit();
-
- MALI_SUCCESS;
-}
-
-_mali_osk_errcode_t mali_platform_power_mode_change(mali_power_mode power_mode)
-{
- MALI_DEBUG_PRINT(3, ( "mali_platform_power_mode_change power_mode=%d\n", power_mode));
-
- switch (power_mode) {
- case MALI_POWER_MODE_LIGHT_SLEEP:
- case MALI_POWER_MODE_DEEP_SLEEP:
- /* Turn off mali clock gating */
- mali_clk->disable(mali_clk);
- break;
-
- case MALI_POWER_MODE_ON:
- /* Turn on MALI clock gating */
- mali_clk->enable(mali_clk);
- mali_meson_poweron(0);
- break;
- }
- last_power_mode = power_mode;
- MALI_SUCCESS;
-}
-
+++ /dev/null
-/*
- * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
- *
- * A copy of the licence is included with the program, and can also be obtained from Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-/**
- * @file mali_platform.h
- * Platform specific Mali driver functions
- */
-
-#ifndef __MALI_PLATFORM_H__
-#define __MALI_PLATFORM_H__
-
-#include "mali_osk.h"
-
-/** @brief description of power change reasons
- */
-typedef enum mali_power_mode_tag
-{
- MALI_POWER_MODE_ON, /**< Power Mali on */
- MALI_POWER_MODE_LIGHT_SLEEP, /**< Mali has been idle for a short time, or runtime PM suspend */
- MALI_POWER_MODE_DEEP_SLEEP, /**< Mali has been idle for a long time, or OS suspend */
-} mali_power_mode;
-
-/** @brief Platform specific setup and initialisation of MALI
- *
- * This is called from the entrypoint of the driver to initialize the platform
- *
- * @return _MALI_OSK_ERR_OK on success otherwise, a suitable _mali_osk_errcode_t error.
- */
-_mali_osk_errcode_t mali_platform_init(void);
-
-/** @brief Platform specific deinitialisation of MALI
- *
- * This is called on the exit of the driver to terminate the platform
- *
- * @return _MALI_OSK_ERR_OK on success otherwise, a suitable _mali_osk_errcode_t error.
- */
-_mali_osk_errcode_t mali_platform_deinit(void);
-
-/** @brief Platform specific powerdown sequence of MALI
- *
- * Notification from the Mali device driver stating the new desired power mode.
- * MALI_POWER_MODE_ON must be obeyed, while the other modes are optional.
- * @param power_mode defines the power modes
- * @return _MALI_OSK_ERR_OK on success otherwise, a suitable _mali_osk_errcode_t error.
- */
-_mali_osk_errcode_t mali_platform_power_mode_change(mali_power_mode power_mode);
-
-
-/** @brief Platform specific handling of GPU utilization data
- *
- * When GPU utilization data is enabled, this function will be
- * periodically called.
- *
- * @param utilization The workload utilization of the Mali GPU. 0 = no utilization, 256 = full utilization.
- */
-void mali_gpu_utilization_handler(u32 utilization);
-
-/** @brief Setting the power domain of MALI
- *
- * This function sets the power domain of MALI if Linux run time power management is enabled
- *
- * @param dev Reference to struct platform_device (defined in linux) used by MALI GPU
- */
-void set_mali_parent_power_domain(void* dev);
-
-#endif
+++ /dev/null
-/*
- * This confidential and proprietary software may be used only as
- * authorised by a licensing agreement from AMLOGIC, INC.
- * (C) COPYRIGHT 2011 AMLOGIC, INC.
- * ALL RIGHTS RESERVED
- * The entire notice above must be reproduced on all authorised
- * copies and copies may only be made to the extent permitted
- * by a licensing agreement from AMLOGIC, INC.
- */
-
-#ifndef MALI_POWERON_REG_H
-#define MALI_POWERON_REG_H
-
-#define MALI_PP_PP_VERSION_MAGIC 0xCD070100UL
-
-#if defined(IO_APB2_BUS_PHY_BASE)
-#define WRITE_MALI_REG(reg, val) \
- __raw_writel(val, (volatile void *)(reg - IO_APB2_BUS_PHY_BASE + IO_APB2_BUS_BASE))
-#define READ_MALI_REG(reg) \
- __raw_readl((volatile void *)(reg - IO_APB2_BUS_PHY_BASE + IO_APB2_BUS_BASE))
-#else
-#define WRITE_MALI_REG(reg, val) \
- __raw_writel(val, (volatile void *)(reg - IO_APB_BUS_PHY_BASE + IO_APB_BUS_BASE))
-#define READ_MALI_REG(reg) \
- __raw_readl((volatile void *)(reg - IO_APB_BUS_PHY_BASE + IO_APB_BUS_BASE))
-#endif
-
-#define MALI_APB_GP_VSCL_START 0xd0060000
-#define MALI_APB_GP_VSCL_END 0xd0060004
-#define MALI_APB_GP_CMD 0xd0060020
-#define MALI_APB_GP_INT_RAWSTAT 0xd0060024
-#define MALI_APB_GP_INT_CLEAR 0xd0060028
-#define MALI_APB_GP_INT_MASK 0xd006002c
-#define MALI_APB_GP_INT_STAT 0xd0060030
-
-#define MALI_MMU_DTE_ADDR 0xd0063000
-#define MALI_MMU_STATUS 0xd0063004
-#define MALI_MMU_CMD 0xd0063008
-#define MALI_MMU_RAW_STATUS 0xd0064014
-#define MALI_MMU_INT_CLEAR 0xd0064018
-#define MALI_MMU_INT_MASK 0xd006401c
-#define MALI_MMU_INT_STATUS 0xd0064020
-
-#define MALI_PP_MMU_DTE_ADDR 0xd0064000
-#define MALI_PP_MMU_STATUS 0xd0064004
-#define MALI_PP_MMU_CMD 0xd0064008
-#define MALI_PP_MMU_RAW_STATUS 0xd0064014
-#define MALI_PP_MMU_INT_CLEAR 0xd0064018
-#define MALI_PP_MMU_INT_MASK 0xd006401c
-#define MALI_PP_MMU_INT_STATUS 0xd0064020
-
-#define MALI_APB_PP_REND_LIST_ADDR 0xd0068000
-#define MALI_APB_PP_REND_RSW_BASE 0xd0068004
-#define MALI_APB_PP_REND_VERTEX_BASE 0xd0068008
-#define MALI_APB_PPSUBPIXEL_SPECIFIER 0xd0068048
-#define MALI_APB_WB0_SOURCE_SELECT 0xd0068100
-#define MALI_APB_WB0_TARGET_ADDR 0xd0068104
-#define MALI_APB_WB0_TARGET_SCANLINE_LENGTH 0xd0068114
-
-#define MALI_PP_PP_VERSION 0xd0069000
-#define MALI_PP_STATUS 0xd0069008
-#define MALI_PP_CTRL_MGMT 0xd006900C
-#define MALI_PP_INT_RAWSTAT 0xd0069020
-#define MALI_PP_INT_CLEAR 0xd0069024
-#define MALI_PP_INT_MASK 0xd0069028
-#define MALI_PP_INT_STAT 0xd006902C
-
-#endif /* MALI_POWERON_REG_H */
+++ /dev/null
-/*
- * platform.c
- *
- * clock source setting and resource config
- *
- * Created on: Dec 4, 2013
- * Author: amlogic
- */
-
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/module.h>
-#include <linux/ioport.h>
-#include <linux/slab.h>
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#include <asm/io.h>
-#include <linux/mali/mali_utgard.h>
-
-#include <common/mali_kernel_common.h>
-#include <common/mali_osk_profiling.h>
-#include <common/mali_pmu.h>
-
-#include "meson_main.h"
-#include "mali_fix.h"
-#include "mali_platform.h"
-
-/**
- * For Meson 6tvd.
- *
- */
-
-#if MESON_CPU_TYPE <= MESON_CPU_TYPE_MESON6TV
-
-u32 mali_dvfs_clk[1];
-u32 mali_dvfs_clk_sample[1];
-
-#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6TV
-#undef INT_MALI_GP
-#undef INT_MALI_GP_MMU
-#undef INT_MALI_PP
-#undef INT_MALI_PP2
-#undef INT_MALI_PP3
-#undef INT_MALI_PP4
-#undef INT_MALI_PP_MMU
-#undef INT_MALI_PP2_MMU
-#undef INT_MALI_PP3_MMU
-#undef INT_MALI_PP4_MMU
-
-#define INT_MALI_GP (48+32)
-#define INT_MALI_GP_MMU (49+32)
-#define INT_MALI_PP (50+32)
-#define INT_MALI_PP2 (58+32)
-#define INT_MALI_PP3 (60+32)
-#define INT_MALI_PP4 (62+32)
-#define INT_MALI_PP_MMU (51+32)
-#define INT_MALI_PP2_MMU (59+32)
-#define INT_MALI_PP3_MMU (61+32)
-#define INT_MALI_PP4_MMU (63+32)
-
-#ifndef CONFIG_MALI400_4_PP
-static struct resource meson_mali_resources[] =
-{
- MALI_GPU_RESOURCES_MALI400_MP2(0xd0060000,
- INT_MALI_GP, INT_MALI_GP_MMU,
- INT_MALI_PP, INT_MALI_PP_MMU,
- INT_MALI_PP2, INT_MALI_PP2_MMU)
-};
-#else
-static struct resource meson_mali_resources[] =
-{
- MALI_GPU_RESOURCES_MALI400_MP4(0xd0060000,
- INT_MALI_GP, INT_MALI_GP_MMU,
- INT_MALI_PP, INT_MALI_PP_MMU,
- INT_MALI_PP2, INT_MALI_PP2_MMU,
- INT_MALI_PP3, INT_MALI_PP3_MMU,
- INT_MALI_PP4, INT_MALI_PP4_MMU
- )
-};
-#endif
-
-#elif MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
-
-#undef INT_MALI_GP
-#undef INT_MALI_GP_MMU
-#undef INT_MALI_PP
-#undef INT_MALI_PP2
-#undef INT_MALI_PP_MMU
-#undef INT_MALI_PP2_MMU
-
-#define INT_MALI_GP (48+32)
-#define INT_MALI_GP_MMU (49+32)
-#define INT_MALI_PP (50+32)
-#define INT_MALI_PP_MMU (51+32)
-#define INT_MALI_PP2_MMU ( 6+32)
-
-static struct resource meson_mali_resources[] =
-{
- MALI_GPU_RESOURCES_MALI400_MP2(0xd0060000,
- INT_MALI_GP, INT_MALI_GP_MMU,
- INT_MALI_PP, INT_MALI_PP2_MMU,
- INT_MALI_PP_MMU, INT_MALI_PP2_MMU)
-};
-
-#else /* MESON_CPU_TYPE == MESON_CPU_TYPE_MESON3 */
-
-#undef INT_MALI_GP
-#undef INT_MALI_GP_MMU
-#undef INT_MALI_PP
-#undef INT_MALI_PP_MMU
-
-#define INT_MALI_GP 48
-#define INT_MALI_GP_MMU 49
-#define INT_MALI_PP 50
-#define INT_MALI_PP_MMU 51
-
-static struct resource meson_mali_resources[] =
-{
- MALI_GPU_RESOURCES_MALI400_MP1(0xd0060000,
- INT_MALI_GP, INT_MALI_GP_MMU, INT_MALI_PP, INT_MALI_PP_MMU)
-};
-#endif /* MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6TV */
-
-void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data)
-{
-
-}
-
-mali_plat_info_t mali_plat_data = {
-
-};
-
-int mali_meson_init_start(struct platform_device* ptr_plt_dev)
-{
- /* for mali platform data. */
- struct mali_gpu_device_data* pdev = ptr_plt_dev->dev.platform_data;
-
- pdev->control_interval = 1000;
- pdev->utilization_callback = mali_gpu_utilization_callback;
-
- /* for resource data. */
- ptr_plt_dev->num_resources = ARRAY_SIZE(meson_mali_resources);
- ptr_plt_dev->resource = meson_mali_resources;
- return 0;
-}
-
-int mali_meson_init_finish(struct platform_device* ptr_plt_dev)
-{
- mali_platform_init();
- return 0;
-}
-
-int mali_meson_uninit(struct platform_device* ptr_plt_dev)
-{
- mali_platform_deinit();
- return 0;
-}
-
-int mali_light_suspend(struct device *device)
-{
- int ret = 0;
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_suspend(device);
- }
-
- mali_platform_power_mode_change(MALI_POWER_MODE_LIGHT_SLEEP);
- return ret;
-}
-
-int mali_light_resume(struct device *device)
-{
- int ret = 0;
-
- mali_platform_power_mode_change(MALI_POWER_MODE_ON);
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_resume(device);
- }
- return ret;
-}
-
-int mali_deep_suspend(struct device *device)
-{
- int ret = 0;
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->suspend(device);
- }
-
- mali_platform_power_mode_change(MALI_POWER_MODE_DEEP_SLEEP);
- return ret;
-}
-
-int mali_deep_resume(struct device *device)
-{
- int ret = 0;
-
- mali_platform_power_mode_change(MALI_POWER_MODE_ON);
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->resume(device);
- }
- return ret;
-
-}
-
-void mali_core_scaling_term(void)
-{
-
-}
-
-int get_gpu_max_clk_level(void)
-{
- return 0;
-}
-
-void mali_post_init(void)
-{
-}
-#endif /* MESON_CPU_TYPE <= MESON_CPU_TYPE_MESON6 */
+++ /dev/null
-/*
- * platform.c
- *
- * clock source setting and resource config
- *
- * Created on: Dec 4, 2013
- * Author: amlogic
- */
-
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/module.h> /* kernel module definitions */
-#include <linux/ioport.h> /* request_mem_region */
-#include <linux/slab.h>
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#include <asm/io.h>
-#include <linux/mali/mali_utgard.h>
-
-#include <common/mali_kernel_common.h>
-#include <common/mali_osk_profiling.h>
-#include <common/mali_pmu.h>
-
-#include "meson_main.h"
-
-/*
- * For Meson 8TVD.
- *
- */
-
-#define CFG_PP 2
-#define CFG_CLOCK 3
-#define CFG_MIN_PP 1
-#define CFG_MIN_CLOCK 0
-
-/* fclk is 2Ghz. */
-#define FCLK_DEV5 (7 << 9) /* 400 Mhz */
-#define FCLK_DEV3 (6 << 9) /* 666 Mhz */
-#define FCLK_DEV2 (5 << 9) /* 1000 Mhz */
-#define FCLK_DEV7 (4 << 9) /* 285 Mhz */
-
-u32 mali_dvfs_clk[] = {
- FCLK_DEV7 | 9, /* 100 Mhz */
- FCLK_DEV2 | 4, /* 200 Mhz */
- FCLK_DEV3 | 1, /* 333 Mhz */
- FCLK_DEV5 | 0, /* 400 Mhz */
-};
-
-u32 mali_dvfs_clk_sample[] = {
- 100, /* 182.1 Mhz */
- 200, /* 318.7 Mhz */
- 333, /* 425 Mhz */
- 400, /* 510 Mhz */
-};
-
-static mali_plat_info_t mali_plat_data = {
- .cfg_pp = CFG_PP, /* number of pp. */
- .cfg_min_pp = CFG_MIN_PP,
- .def_clock = CFG_CLOCK, /* gpu clock used most of time.*/
- .cfg_clock = CFG_CLOCK, /* max gpu clock. */
- .cfg_min_clock = CFG_MIN_CLOCK,
-
- .clk = mali_dvfs_clk, /* clock source table. */
- .clk_sample = mali_dvfs_clk_sample, /* freqency table for show. */
- .clk_len = sizeof(mali_dvfs_clk) / sizeof(mali_dvfs_clk[0]),
- .have_switch = 0,
-};
-
-#define MALI_USER_PP0 AM_IRQ4(31)
-
-static struct resource mali_gpu_resources[] =
-{
-MALI_GPU_RESOURCES_MALI450_MP2_PMU(0xC9140000, INT_MALI_GP, INT_MALI_GP_MMU,
- MALI_USER_PP0, INT_MALI_PP_MMU,
- INT_MALI_PP1, INT_MALI_PP_MMU1,
- INT_MALI_PP)
-};
-
-int mali_meson_init_start(struct platform_device* ptr_plt_dev)
-{
- ptr_plt_dev->num_resources = ARRAY_SIZE(mali_gpu_resources);
- ptr_plt_dev->resource = mali_gpu_resources;
- return mali_clock_init(&mali_plat_data);
-}
-
-int mali_meson_init_finish(struct platform_device* ptr_plt_dev)
-{
- return 0;
-}
-
-int mali_meson_uninit(struct platform_device* ptr_plt_dev)
-{
- return 0;
-}
-
-static int mali_cri_pmu_on_off(size_t param)
-{
- struct mali_pmu_core *pmu;
-
- MALI_DEBUG_PRINT(4, ("mali_os_suspend() called\n"));
- pmu = mali_pmu_get_global_pmu_core();
- if (param == 0)
- mali_pmu_power_down_all(pmu);
- else
- mali_pmu_power_up_all(pmu);
- return 0;
-}
-
-int mali_light_suspend(struct device *device)
-{
- int ret = 0;
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- 0, 0, 0, 0, 0);
-#endif
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_suspend(device);
- }
-
- /* clock scaling. Kasin..*/
- mali_clock_critical(mali_cri_pmu_on_off, 0);
- disable_clock();
- return ret;
-}
-
-int mali_light_resume(struct device *device)
-{
- int ret = 0;
- /* clock scaling. Kasin..*/
- enable_clock();
-
- mali_clock_critical(mali_cri_pmu_on_off, 1);
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- 0, 0, 0, 0, 0);
-#endif
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_resume(device);
- }
- return ret;
-}
-
-int mali_deep_suspend(struct device *device)
-{
- int ret = 0;
- //enable_clock();
- //flush_scaling_job();
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->suspend(device);
- }
-
- /* clock scaling off. Kasin... */
- mali_clock_critical(mali_cri_pmu_on_off, 0);
- disable_clock();
- return ret;
-}
-
-int mali_deep_resume(struct device *device)
-{
- int ret = 0;
- /* clock scaling up. Kasin.. */
- enable_clock();
- mali_clock_critical(mali_cri_pmu_on_off, 1);
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->resume(device);
- }
- return ret;
-
-}
-
-void mali_post_init(void)
-{
-}
+++ /dev/null
-/*
- * platform.c
- *
- * clock source setting and resource config
- *
- * Created on: Dec 4, 2013
- * Author: amlogic
- */
-
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/module.h> /* kernel module definitions */
-#include <linux/ioport.h> /* request_mem_region */
-#include <linux/slab.h>
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#endif
-#include <asm/io.h>
-#include <linux/mali/mali_utgard.h>
-#ifdef CONFIG_GPU_THERMAL
-#include <linux/gpu_cooling.h>
-#include <linux/gpucore_cooling.h>
-#endif
-#include <common/mali_kernel_common.h>
-#include <common/mali_osk_profiling.h>
-#include <common/mali_pmu.h>
-
-#include "meson_main.h"
-
-/*
- * For Meson 8 M2.
- *
- */
-
-#define CFG_PP 6
-#define CFG_CLOCK 3
-#define CFG_MIN_PP 1
-#define CFG_MIN_CLOCK 0
-
-/* fclk is 2550Mhz. */
-#define FCLK_DEV3 (6 << 9) /* 850 Mhz */
-#define FCLK_DEV4 (5 << 9) /* 637.5 Mhz */
-#define FCLK_DEV5 (7 << 9) /* 510 Mhz */
-#define FCLK_DEV7 (4 << 9) /* 364.3 Mhz */
-
-static u32 mali_dvfs_clk[] = {
- FCLK_DEV7 | 1, /* 182.1 Mhz */
- FCLK_DEV4 | 1, /* 318.7 Mhz */
- FCLK_DEV3 | 1, /* 425 Mhz */
- FCLK_DEV5 | 0, /* 510 Mhz */
- FCLK_DEV4 | 0, /* 637.5 Mhz */
-};
-
-static u32 mali_dvfs_clk_sample[] = {
- 182, /* 182.1 Mhz */
- 319, /* 318.7 Mhz */
- 425, /* 425 Mhz */
- 510, /* 510 Mhz */
- 637, /* 637.5 Mhz */
-};
-//////////////////////////////////////
-//for dvfs
-struct mali_gpu_clk_item meson_gpu_clk[] = {
- {182, 1150}, /* 182.1 Mhz, 1150mV */
- {319, 1150}, /* 318.7 Mhz */
- {425, 1150}, /* 425 Mhz */
- {510, 1150}, /* 510 Mhz */
- {637, 1150}, /* 637.5 Mhz */
-};
-struct mali_gpu_clock meson_gpu_clk_info = {
- .item = meson_gpu_clk,
- .num_of_steps = ARRAY_SIZE(meson_gpu_clk),
-};
-static int cur_gpu_clk_index = 0;
-//////////////////////////////////////
-static mali_dvfs_threshold_table mali_dvfs_table[]={
- { 0, 0, 3, 30, 80}, /* for 182.1 */
- { 1, 1, 3, 40, 205}, /* for 318.7 */
- { 2, 2, 3, 150, 215}, /* for 425.0 */
- { 3, 3, 3, 170, 253}, /* for 510.0 */
- { 4, 4, 3, 230, 255}, /* for 637.5 */
- { 0, 0, 3, 0, 0}
-};
-
-static void mali_plat_preheat(void);
-static mali_plat_info_t mali_plat_data = {
- .cfg_pp = CFG_PP, /* number of pp. */
- .cfg_min_pp = CFG_MIN_PP,
- .turbo_clock = 4, /* reserved clock src. */
- .def_clock = 2, /* gpu clock used most of time.*/
- .cfg_clock = CFG_CLOCK, /* max gpu clock. */
- .cfg_clock_bkup = CFG_CLOCK,
- .cfg_min_clock = CFG_MIN_CLOCK,
-
- .sc_mpp = 3, /* number of pp used most of time.*/
- .bst_gpu = 210, /* threshold for boosting gpu. */
- .bst_pp = 160, /* threshold for boosting PP. */
-
- .clk = mali_dvfs_clk, /* clock source table. */
- .clk_sample = mali_dvfs_clk_sample, /* freqency table for show. */
- .clk_len = sizeof(mali_dvfs_clk) / sizeof(mali_dvfs_clk[0]),
- .have_switch = 1,
-
- .dvfs_table = mali_dvfs_table, /* DVFS table. */
- .dvfs_table_size = sizeof(mali_dvfs_table) / sizeof(mali_dvfs_threshold_table),
-
- .scale_info = {
- CFG_MIN_PP, /* minpp */
- CFG_PP, /* maxpp, should be same as cfg_pp */
- CFG_MIN_CLOCK, /* minclk */
- CFG_CLOCK, /* maxclk should be same as cfg_clock */
- },
-
- .limit_on = 1,
- .plat_preheat = mali_plat_preheat,
-};
-
-static void mali_plat_preheat(void)
-{
-#ifndef CONFIG_MALI_DVFS
- u32 pre_fs;
- u32 clk, pp;
-
- if (get_mali_schel_mode() != MALI_PP_FS_SCALING)
- return;
-
- get_mali_rt_clkpp(&clk, &pp);
- pre_fs = mali_plat_data.def_clock + 1;
- if (clk < pre_fs)
- clk = pre_fs;
- if (pp < mali_plat_data.sc_mpp)
- pp = mali_plat_data.sc_mpp;
- set_mali_rt_clkpp(clk, pp, 1);
-#endif
-}
-
-mali_plat_info_t* get_mali_plat_data(void) {
- return &mali_plat_data;
-}
-
-int get_mali_freq_level(int freq)
-{
- int i = 0, level = -1;
- int mali_freq_num;
-
- if (freq < 0)
- return level;
-
- mali_freq_num = mali_plat_data.dvfs_table_size - 1;
- if (freq <= mali_plat_data.clk_sample[0])
- level = mali_freq_num-1;
- if (freq >= mali_plat_data.clk_sample[mali_freq_num - 1])
- level = 0;
- for (i=0; i<mali_freq_num - 1 ;i++) {
- if (freq >= mali_plat_data.clk_sample[i] && freq <= mali_plat_data.clk_sample[i + 1]) {
- level = i;
- level = mali_freq_num-level - 1;
- }
- }
- return level;
-}
-
-unsigned int get_mali_max_level(void)
-{
- return mali_plat_data.dvfs_table_size - 1;
-}
-
-#if 0
-static struct resource mali_gpu_resources[] =
-{
- MALI_GPU_RESOURCES_MALI450_MP6_PMU(IO_MALI_APB_PHY_BASE, INT_MALI_GP, INT_MALI_GP_MMU,
- INT_MALI_PP0, INT_MALI_PP0_MMU,
- INT_MALI_PP1, INT_MALI_PP1_MMU,
- INT_MALI_PP2, INT_MALI_PP2_MMU,
- INT_MALI_PP4, INT_MALI_PP4_MMU,
- INT_MALI_PP5, INT_MALI_PP5_MMU,
- INT_MALI_PP6, INT_MALI_PP6_MMU,
- INT_MALI_PP)
-};
-#else
-static struct resource mali_gpu_resources[] =
-{
- { .name = "Mali_L2", .flags = 0x00000200, .start = 0xd00c0000 + 0x10000, .end = 0xd00c0000 + 0x10000 + 0x200, },
- { .name = "Mali_GP", .flags = 0x00000200, .start = 0xd00c0000 + 0x00000, .end = 0xd00c0000 + 0x00000 + 0x100, },
- { .name = "Mali_GP_IRQ", .flags = 0x00000400, .start = (160 + 32), .end = (160 + 32), },
- { .name = "Mali_GP_MMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x03000, .end = 0xd00c0000 + 0x03000 + 0x100, },
- { .name = "Mali_GP_MMU_IRQ", .flags = 0x00000400, .start = (161 + 32), .end = (161 + 32), },
- { .name = "Mali_L2", .flags = 0x00000200, .start = 0xd00c0000 + 0x01000, .end = 0xd00c0000 + 0x01000 + 0x200, },
- { .name = "Mali_PP" "0", .flags = 0x00000200, .start = 0xd00c0000 + 0x08000, .end = 0xd00c0000 + 0x08000 + 0x1100, },
- { .name = "Mali_PP" "0" "_IRQ", .flags = 0x00000400, .start = (164 + 32), .end = (164 + 32), },
- { .name = "Mali_PP" "0" "_MMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x04000, .end = 0xd00c0000 + 0x04000 + 0x100, },
- { .name = "Mali_PP" "0" "_MMU_IRQ", .flags = 0x00000400, .start = (165 + 32), .end = (165 + 32), },
- { .name = "Mali_PP" "1", .flags = 0x00000200, .start = 0xd00c0000 + 0x0A000, .end = 0xd00c0000 + 0x0A000 + 0x1100, },
- { .name = "Mali_PP" "1" "_IRQ", .flags = 0x00000400, .start = (166 + 32), .end = (166 + 32), },
- { .name = "Mali_PP" "1" "_MMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x05000, .end = 0xd00c0000 + 0x05000 + 0x100, },
- { .name = "Mali_PP" "1" "_MMU_IRQ", .flags = 0x00000400, .start = (167 + 32), .end = (167 + 32), },
- { .name = "Mali_PP" "2", .flags = 0x00000200, .start = 0xd00c0000 + 0x0C000, .end = 0xd00c0000 + 0x0C000 + 0x1100, },
- { .name = "Mali_PP" "2" "_IRQ", .flags = 0x00000400, .start = (168 + 32), .end = (168 + 32), },
- { .name = "Mali_PP" "2" "_MMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x06000, .end = 0xd00c0000 + 0x06000 + 0x100, },
- { .name = "Mali_PP" "2" "_MMU_IRQ", .flags = 0x00000400, .start = (169 + 32), .end = (169 + 32), },
- { .name = "Mali_L2", .flags = 0x00000200, .start = 0xd00c0000 + 0x11000, .end = 0xd00c0000 + 0x11000 + 0x200, },
- { .name = "Mali_PP" "3", .flags = 0x00000200, .start = 0xd00c0000 + 0x28000, .end = 0xd00c0000 + 0x28000 + 0x1100, },
- { .name = "Mali_PP" "3" "_IRQ", .flags = 0x00000400, .start = (172 + 32), .end = (172 + 32), },
- { .name = "Mali_PP" "3" "_MMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x1C000, .end = 0xd00c0000 + 0x1C000 + 0x100, },
- { .name = "Mali_PP" "3" "_MMU_IRQ", .flags = 0x00000400, .start = (173 + 32), .end = (173 + 32), },
- { .name = "Mali_PP" "4", .flags = 0x00000200, .start = 0xd00c0000 + 0x2A000, .end = 0xd00c0000 + 0x2A000 + 0x1100, },
- { .name = "Mali_PP" "4" "_IRQ", .flags = 0x00000400, .start = (174 + 32), .end = (174 + 32), },
- { .name = "Mali_PP" "4" "_MMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x1D000, .end = 0xd00c0000 + 0x1D000 + 0x100, },
- { .name = "Mali_PP" "4" "_MMU_IRQ", .flags = 0x00000400, .start = (175 + 32), .end = (175 + 32), },
- { .name = "Mali_PP" "5", .flags = 0x00000200, .start = 0xd00c0000 + 0x2C000, .end = 0xd00c0000 + 0x2C000 + 0x1100, },
- { .name = "Mali_PP" "5" "_IRQ", .flags = 0x00000400, .start = (176 + 32), .end = (176 + 32), },
- { .name = "Mali_PP" "5" "_MMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x1E000, .end = 0xd00c0000 + 0x1E000 + 0x100, },
- { .name = "Mali_PP" "5" "_MMU_IRQ", .flags = 0x00000400, .start = (177 + 32), .end = (177 + 32), },
- { .name = "Mali_Broadcast", .flags = 0x00000200, .start = 0xd00c0000 + 0x13000, .end = 0xd00c0000 + 0x13000 + 0x100, },
- { .name = "Mali_DLBU", .flags = 0x00000200, .start = 0xd00c0000 + 0x14000, .end = 0xd00c0000 + 0x14000 + 0x100, },
- { .name = "Mali_PP_Broadcast", .flags = 0x00000200, .start = 0xd00c0000 + 0x16000, .end = 0xd00c0000 + 0x16000 + 0x1100, },
- { .name = "Mali_PP_Broadcast_IRQ", .flags = 0x00000400, .start = (162 + 32), .end = (162 + 32), },
- { .name = "Mali_PP_MMU_Broadcast", .flags = 0x00000200, .start = 0xd00c0000 + 0x15000, .end = 0xd00c0000 + 0x15000 + 0x100, },
- { .name = "Mali_DMA", .flags = 0x00000200, .start = 0xd00c0000 + 0x12000, .end = 0xd00c0000 + 0x12000 + 0x100, },
- { .name = "Mali_PMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x02000, .end = 0xd00c0000 + 0x02000 + 0x100, },
-};
-#endif
-#ifdef CONFIG_GPU_THERMAL
-static void set_limit_mali_freq(u32 idx)
-{
- if (mali_plat_data.limit_on == 0)
- return;
- if (idx > mali_plat_data.turbo_clock || idx < mali_plat_data.scale_info.minclk)
- return;
- mali_plat_data.scale_info.maxclk= idx;
- revise_mali_rt();
-}
-
-static u32 get_limit_mali_freq(void)
-{
- return mali_plat_data.scale_info.maxclk;
-}
-#endif
-
-#ifdef CONFIG_GPU_THERMAL
-static u32 set_limit_pp_num(u32 num)
-{
- u32 ret = -1;
- if (mali_plat_data.limit_on == 0)
- goto quit;
- if (num > mali_plat_data.cfg_pp ||
- num < mali_plat_data.scale_info.minpp)
- goto quit;
- mali_plat_data.scale_info.maxpp = num;
- revise_mali_rt();
- ret = 0;
-quit:
- return ret;
-}
-#endif
-
-void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data);
-
-#if 0
-struct mali_gpu_clk_item {
- unsigned int clock; /* unit(MHz) */
- unsigned int vol;
-};
-
-struct mali_gpu_clock {
- struct mali_gpu_clk_item *item;
- unsigned int num_of_steps;
-};
-#endif
-
-/* Function that platfrom report it's clock info which driver can set, needed when CONFIG_MALI_DVFS enabled */
-void meson_platform_get_clock_info(struct mali_gpu_clock **data) {
- *data = &meson_gpu_clk_info;
-}
-
-/* Function that get the current clock info, needed when CONFIG_MALI_DVFS enabled */
-int meson_platform_get_freq(void) {
- printk("get cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
- return cur_gpu_clk_index;
-}
-
-/* Fuction that platform callback for freq setting, needed when CONFIG_MALI_DVFS enabled */
-int meson_platform_set_freq(int setting_clock_step) {
-
- if (cur_gpu_clk_index == setting_clock_step) {
- return 0;
- }
-
- mali_clock_set(setting_clock_step);
-
- cur_gpu_clk_index = setting_clock_step;
- printk("set cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
-
- return 0;
-}
-
-int mali_meson_init_start(struct platform_device* ptr_plt_dev)
-{
- struct mali_gpu_device_data* pdev = ptr_plt_dev->dev.platform_data;
-
- /* chip mark detect. */
-#ifdef IS_MESON_M8_CPU
- if (IS_MESON_M8_CPU) {
- mali_plat_data.have_switch = 0;
- }
-#endif
-
- /* for resource data. */
- ptr_plt_dev->num_resources = ARRAY_SIZE(mali_gpu_resources);
- ptr_plt_dev->resource = mali_gpu_resources;
-
- /*for dvfs*/
-#ifndef CONFIG_MALI_DVFS
- /* for mali platform data. */
- pdev->control_interval = 300;
- pdev->utilization_callback = mali_gpu_utilization_callback;
-#else
- pdev->get_clock_info = meson_platform_get_clock_info;
- pdev->get_freq = meson_platform_get_freq;
- pdev->set_freq = meson_platform_set_freq;
-#endif
-
- return mali_clock_init(&mali_plat_data);
-}
-
-int mali_meson_init_finish(struct platform_device* ptr_plt_dev)
-{
-#ifndef CONFIG_MALI_DVFS
- if (mali_core_scaling_init(&mali_plat_data) < 0)
- return -1;
-#else
- printk("disable meson own dvfs\n");
-#endif
- return 0;
-}
-
-int mali_meson_uninit(struct platform_device* ptr_plt_dev)
-{
- return 0;
-}
-
-static int mali_cri_light_suspend(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- mali_pm_statue = 1;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_suspend(device);
- }
- mali_pmu_power_down_all(pmu);
- return ret;
-}
-
-static int mali_cri_light_resume(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- mali_pmu_power_up_all(pmu);
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_resume(device);
- }
- mali_pm_statue = 0;
- return ret;
-}
-
-static int mali_cri_deep_suspend(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->suspend(device);
- }
- mali_pmu_power_down_all(pmu);
- return ret;
-}
-
-static int mali_cri_deep_resume(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- mali_pmu_power_up_all(pmu);
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->resume(device);
- }
- return ret;
-
-}
-
-int mali_light_suspend(struct device *device)
-{
- int ret = 0;
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- 0, 0, 0, 0, 0);
-#endif
-
- /* clock scaling. Kasin..*/
- ret = mali_clock_critical(mali_cri_light_suspend, (size_t)device);
- disable_clock();
- return ret;
-}
-
-int mali_light_resume(struct device *device)
-{
- int ret = 0;
- enable_clock();
- ret = mali_clock_critical(mali_cri_light_resume, (size_t)device);
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- get_current_frequency(), 0, 0, 0, 0);
-#endif
- return ret;
-}
-
-int mali_deep_suspend(struct device *device)
-{
- int ret = 0;
-
- mali_pm_statue = 1;
- enable_clock();
-#ifndef CONFIG_MALI_DVFS
- flush_scaling_job();
-#endif
-
- /* clock scaling off. Kasin... */
- ret = mali_clock_critical(mali_cri_deep_suspend, (size_t)device);
- disable_clock();
- return ret;
-}
-
-int mali_deep_resume(struct device *device)
-{
- int ret = 0;
-
- /* clock scaling up. Kasin.. */
- enable_clock();
- ret = mali_clock_critical(mali_cri_deep_resume, (size_t)device);
- mali_pm_statue = 0;
- return ret;
-
-}
-
-void mali_post_init(void)
-{
-#ifdef CONFIG_GPU_THERMAL
- int err;
- struct gpufreq_cooling_device *gcdev = NULL;
- struct gpucore_cooling_device *gccdev = NULL;
-
- gcdev = gpufreq_cooling_alloc();
- register_gpu_freq_info(get_current_frequency);
- if (IS_ERR(gcdev))
- printk("malloc gpu cooling buffer error!!\n");
- else if (!gcdev)
- printk("system does not enable thermal driver\n");
- else {
- gcdev->get_gpu_freq_level = get_mali_freq_level;
- gcdev->get_gpu_max_level = get_mali_max_level;
- gcdev->set_gpu_freq_idx = set_limit_mali_freq;
- gcdev->get_gpu_current_max_level = get_limit_mali_freq;
- err = gpufreq_cooling_register(gcdev);
- if (err < 0)
- printk("register GPU cooling error\n");
- printk("gpu cooling register okay with err=%d\n",err);
- }
-
- gccdev = gpucore_cooling_alloc();
- if (IS_ERR(gccdev))
- printk("malloc gpu core cooling buffer error!!\n");
- else if (!gccdev)
- printk("system does not enable thermal driver\n");
- else {
- gccdev->max_gpu_core_num=mali_plat_data.cfg_pp;
- gccdev->set_max_pp_num=set_limit_pp_num;
- err = (int)gpucore_cooling_register(gccdev);
- if (err < 0)
- printk("register GPU cooling error\n");
- printk("gpu core cooling register okay with err=%d\n",err);
- }
-#endif
-}
+++ /dev/null
-/*
- * platform.c
- *
- * clock source setting and resource config
- *
- * Created on: Dec 4, 2013
- * Author: amlogic
- */
-
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/module.h> /* kernel module definitions */
-#include <linux/ioport.h> /* request_mem_region */
-#include <linux/slab.h>
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#include <asm/io.h>
-#include <linux/mali/mali_utgard.h>
-#include <linux/gpu_cooling.h>
-#include <linux/gpucore_cooling.h>
-#include <common/mali_kernel_common.h>
-#include <common/mali_osk_profiling.h>
-#include <common/mali_pmu.h>
-
-#include "meson_main.h"
-
-/*
- * For Meson 8B.
- *
- */
-
-#define CFG_PP 2
-#define CFG_CLOCK 3
-#define CFG_MIN_PP 1
-#define CFG_MIN_CLOCK 0
-
-/* fclk is 2550Mhz. */
-#define FCLK_DEV3 (6 << 9) /* 850 Mhz */
-#define FCLK_DEV4 (5 << 9) /* 637.5 Mhz */
-#define FCLK_DEV5 (7 << 9) /* 510 Mhz */
-#define FCLK_DEV7 (4 << 9) /* 364.3 Mhz */
-
-static u32 mali_dvfs_clk[] = {
- FCLK_DEV5 | 1, /* 255 Mhz */
- FCLK_DEV7 | 0, /* 364 Mhz */
- FCLK_DEV3 | 1, /* 425 Mhz */
- FCLK_DEV5 | 0, /* 510 Mhz */
- FCLK_DEV4 | 0, /* 637.5 Mhz */
-};
-
-static u32 mali_dvfs_clk_sample[] = {
- 255, /* 182.1 Mhz */
- 364, /* 318.7 Mhz */
- 425, /* 425 Mhz */
- 510, /* 510 Mhz */
- 637, /* 637.5 Mhz */
-};
-
-//////////////////////////////////////
-//for dvfs
-struct mali_gpu_clk_item meson_gpu_clk[] = {
- {255, 1150}, /* 182.1 Mhz, 1150mV */
- {364, 1150}, /* 318.7 Mhz */
- {425, 1150}, /* 425 Mhz */
- {510, 1150}, /* 510 Mhz */
- {637, 1150}, /* 637.5 Mhz */
-};
-struct mali_gpu_clock meson_gpu_clk_info = {
- .item = meson_gpu_clk,
- .num_of_steps = ARRAY_SIZE(meson_gpu_clk),
-};
-static int cur_gpu_clk_index = 0;
-//////////////////////////////////////
-
-static mali_dvfs_threshold_table mali_dvfs_table[]={
- { 0, 0, 5, 30 , 180}, /* for 255 */
- { 1, 1, 5, 152, 205}, /* for 364 */
- { 2, 2, 5, 180, 212}, /* for 425 */
- { 3, 3, 5, 205, 236}, /* for 510 */
- { 4, 4, 5, 230, 255}, /* for 637 */
- { 0, 0, 5, 0, 0}
-};
-
-static void mali_plat_preheat(void);
-static mali_plat_info_t mali_plat_data = {
- .cfg_pp = CFG_PP, /* number of pp. */
- .cfg_min_pp = CFG_MIN_PP,
- .turbo_clock = 4, /* reserved clock src. */
- .def_clock = 2, /* gpu clock used most of time.*/
- .cfg_clock = CFG_CLOCK, /* max gpu clock. */
- .cfg_clock_bkup = CFG_CLOCK,
- .cfg_min_clock = CFG_MIN_CLOCK,
-
- .sc_mpp = 2, /* number of pp used most of time.*/
- .bst_gpu = 210, /* threshold for boosting gpu. */
- .bst_pp = 160, /* threshold for boosting PP. */
-
- .clk = mali_dvfs_clk, /* clock source table. */
- .clk_sample = mali_dvfs_clk_sample, /* freqency table for show. */
- .clk_len = sizeof(mali_dvfs_clk) / sizeof(mali_dvfs_clk[0]),
- .have_switch = 1,
-
- .dvfs_table = mali_dvfs_table, /* DVFS table. */
- .dvfs_table_size = sizeof(mali_dvfs_table) / sizeof(mali_dvfs_threshold_table),
-
- .scale_info = {
- CFG_MIN_PP, /* minpp */
- CFG_PP, /* maxpp, should be same as cfg_pp */
- CFG_MIN_CLOCK, /* minclk */
- CFG_CLOCK, /* maxclk should be same as cfg_clock */
- },
-
- .limit_on = 1,
- .plat_preheat = mali_plat_preheat,
-};
-
-static void mali_plat_preheat(void)
-{
-#ifndef CONFIG_MALI_DVFS
- u32 pre_fs;
- u32 clk, pp;
-
- if (get_mali_schel_mode() != MALI_PP_FS_SCALING)
- return;
-
- get_mali_rt_clkpp(&clk, &pp);
- pre_fs = mali_plat_data.def_clock + 1;
- if (clk < pre_fs)
- clk = pre_fs;
- if (pp < mali_plat_data.sc_mpp)
- pp = mali_plat_data.sc_mpp;
- set_mali_rt_clkpp(clk, pp, 1);
-#endif
-}
-
-mali_plat_info_t* get_mali_plat_data(void) {
- return &mali_plat_data;
-}
-
-int get_mali_freq_level(int freq)
-{
- int i = 0, level = -1;
- int mali_freq_num;
-
- if (freq < 0)
- return level;
- mali_freq_num = mali_plat_data.dvfs_table_size - 1;
- if (freq <= mali_plat_data.clk_sample[0])
- level = mali_freq_num-1;
- if (freq >= mali_plat_data.clk_sample[mali_freq_num - 1])
- level = 0;
- for (i=0; i<mali_freq_num - 1 ;i++) {
- if (freq >= mali_plat_data.clk_sample[i] && freq <= mali_plat_data.clk_sample[i + 1]) {
- level = i;
- level = mali_freq_num-level - 1;
- }
- }
- return level;
-}
-
-unsigned int get_mali_max_level(void)
-{
- return mali_plat_data.dvfs_table_size - 1;
-}
-
-static struct resource mali_gpu_resources[] =
-{
- MALI_GPU_RESOURCES_MALI450_MP2_PMU(IO_MALI_APB_PHY_BASE, INT_MALI_GP, INT_MALI_GP_MMU,
- INT_MALI_PP0, INT_MALI_PP0_MMU,
- INT_MALI_PP1, INT_MALI_PP1_MMU,
- INT_MALI_PP)
-};
-
-static void set_limit_mali_freq(u32 idx)
-{
- if (mali_plat_data.limit_on == 0)
- return;
- if (idx > mali_plat_data.turbo_clock || idx < mali_plat_data.scale_info.minclk)
- return;
- mali_plat_data.scale_info.maxclk= idx;
-
- revise_mali_rt();
-}
-
-static u32 get_limit_mali_freq(void)
-{
- return mali_plat_data.scale_info.maxclk;
-}
-
-static u32 set_limit_pp_num(u32 num)
-{
- u32 ret = -1;
- if (mali_plat_data.limit_on == 0)
- goto quit;
- if (num > mali_plat_data.cfg_pp ||
- num < mali_plat_data.scale_info.minpp)
- goto quit;
- mali_plat_data.scale_info.maxpp = num;
- revise_mali_rt();
- ret = 0;
-quit:
- return ret;
-}
-
-void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data);
-
-#if 0
-struct mali_gpu_clk_item {
- unsigned int clock; /* unit(MHz) */
- unsigned int vol;
-};
-
-struct mali_gpu_clock {
- struct mali_gpu_clk_item *item;
- unsigned int num_of_steps;
-};
-#endif
-
-/* Function that platfrom report it's clock info which driver can set, needed when CONFIG_MALI_DVFS enabled */
-void meson_platform_get_clock_info(struct mali_gpu_clock **data) {
- *data = &meson_gpu_clk_info;
-}
-
-/* Function that get the current clock info, needed when CONFIG_MALI_DVFS enabled */
-int meson_platform_get_freq(void) {
- printk("get cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
- return cur_gpu_clk_index;
-}
-
-/* Fuction that platform callback for freq setting, needed when CONFIG_MALI_DVFS enabled */
-int meson_platform_set_freq(int setting_clock_step) {
-
- if (cur_gpu_clk_index == setting_clock_step) {
- return 0;
- }
-
- mali_clock_set(setting_clock_step);
-
- cur_gpu_clk_index = setting_clock_step;
- printk("set cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
-
- return 0;
-}
-int mali_meson_init_start(struct platform_device* ptr_plt_dev)
-{
- struct mali_gpu_device_data* pdev = ptr_plt_dev->dev.platform_data;
-
-
- /* for resource data. */
- ptr_plt_dev->num_resources = ARRAY_SIZE(mali_gpu_resources);
- ptr_plt_dev->resource = mali_gpu_resources;
-
- /*for dvfs*/
-#ifndef CONFIG_MALI_DVFS
- /* for mali platform data. */
- pdev->control_interval = 200;
- pdev->utilization_callback = mali_gpu_utilization_callback;
-#else
- pdev->get_clock_info = meson_platform_get_clock_info;
- pdev->get_freq = meson_platform_get_freq;
- pdev->set_freq = meson_platform_set_freq;
-#endif
-
- return mali_clock_init(&mali_plat_data);
-}
-
-int mali_meson_init_finish(struct platform_device* ptr_plt_dev)
-{
-#ifndef CONFIG_MALI_DVFS
- if (mali_core_scaling_init(&mali_plat_data) < 0)
- return -1;
-#endif
- return 0;
-}
-
-int mali_meson_uninit(struct platform_device* ptr_plt_dev)
-{
- return 0;
-}
-
-static int mali_cri_light_suspend(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- mali_pm_statue = 1;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_suspend(device);
- }
- mali_pmu_power_down_all(pmu);
- return ret;
-}
-
-static int mali_cri_light_resume(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- mali_pmu_power_up_all(pmu);
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_resume(device);
- }
- mali_pm_statue = 0;
- return ret;
-}
-
-static int mali_cri_deep_suspend(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->suspend(device);
- }
- mali_pmu_power_down_all(pmu);
- return ret;
-}
-
-static int mali_cri_deep_resume(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- mali_pmu_power_up_all(pmu);
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->resume(device);
- }
- return ret;
-
-}
-
-int mali_light_suspend(struct device *device)
-{
- int ret = 0;
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- 0, 0, 0, 0, 0);
-#endif
-
- /* clock scaling. Kasin..*/
- ret = mali_clock_critical(mali_cri_light_suspend, (size_t)device);
- disable_clock();
- return ret;
-}
-
-int mali_light_resume(struct device *device)
-{
- int ret = 0;
- enable_clock();
- ret = mali_clock_critical(mali_cri_light_resume, (size_t)device);
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- get_current_frequency(), 0, 0, 0, 0);
-#endif
- return ret;
-}
-
-int mali_deep_suspend(struct device *device)
-{
- int ret = 0;
- struct mali_pmu_core *pmu;
-
- mali_pm_statue = 1;
- pmu = mali_pmu_get_global_pmu_core();
- enable_clock();
-#ifndef CONFIG_MALI_DVFS
- flush_scaling_job();
-#endif
-
- /* clock scaling off. Kasin... */
- ret = mali_clock_critical(mali_cri_deep_suspend, (size_t)device);
- disable_clock();
- return ret;
-}
-
-int mali_deep_resume(struct device *device)
-{
- int ret = 0;
-
- /* clock scaling up. Kasin.. */
- enable_clock();
- ret = mali_clock_critical(mali_cri_deep_resume, (size_t)device);
- mali_pm_statue = 0;
- return ret;
-}
-
-void mali_post_init(void)
-{
-#ifdef CONFIG_GPU_THERMAL
- int err;
- struct gpufreq_cooling_device *gcdev = NULL;
- struct gpucore_cooling_device *gccdev = NULL;
-
- gcdev = gpufreq_cooling_alloc();
- register_gpu_freq_info(get_current_frequency);
- if (IS_ERR(gcdev))
- printk("malloc gpu cooling buffer error!!\n");
- else if (!gcdev)
- printk("system does not enable thermal driver\n");
- else {
- gcdev->get_gpu_freq_level = get_mali_freq_level;
- gcdev->get_gpu_max_level = get_mali_max_level;
- gcdev->set_gpu_freq_idx = set_limit_mali_freq;
- gcdev->get_gpu_current_max_level = get_limit_mali_freq;
- err = gpufreq_cooling_register(gcdev);
- if (err < 0)
- printk("register GPU cooling error\n");
- printk("gpu cooling register okay with err=%d\n",err);
- }
-
- gccdev = gpucore_cooling_alloc();
- if (IS_ERR(gccdev))
- printk("malloc gpu core cooling buffer error!!\n");
- else if (!gccdev)
- printk("system does not enable thermal driver\n");
- else {
- gccdev->max_gpu_core_num=mali_plat_data.cfg_pp;
- gccdev->set_max_pp_num=set_limit_pp_num;
- err = (int)gpucore_cooling_register(gccdev);
- if (err < 0)
- printk("register GPU cooling error\n");
- printk("gpu core cooling register okay with err=%d\n",err);
- }
-#endif
-}
+++ /dev/null
-/*
- * Copyright (C) 2013 ARM Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
- *
- * A copy of the licence is included with the program, and can also be obtained from Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-/**
- * @file arm_core_scaling.c
- * Example core scaling policy.
- */
-
-#include <linux/version.h>
-#include <linux/module.h>
-#include <linux/workqueue.h>
-#include <linux/mali/mali_utgard.h>
-#include <mali_kernel_common.h>
-#include <mali_osk_profiling.h>
-
-#include <meson_main.h>
-
-#define LOG_MALI_SCALING 0
-
-
-static int currentStep;
-#ifndef CONFIG_MALI_DVFS
-static int num_cores_enabled;
-static int lastStep;
-static struct work_struct wq_work;
-static mali_plat_info_t* pmali_plat = NULL;
-#endif
-static int scaling_mode = MALI_PP_FS_SCALING;
-
-
-static unsigned scaling_dbg_level = 0;
-module_param(scaling_dbg_level, uint, 0644);
-MODULE_PARM_DESC(scaling_dbg_level , "scaling debug level");
-
-#define scalingdbg(level, fmt, arg...) \
- do { \
- if (scaling_dbg_level >= (level)) \
- printk(fmt , ## arg); \
- } while (0)
-
-#ifndef CONFIG_MALI_DVFS
-static void do_scaling(struct work_struct *work)
-{
- mali_dvfs_threshold_table * pdvfs = pmali_plat->dvfs_table;
- int err = mali_perf_set_num_pp_cores(num_cores_enabled);
- scalingdbg(1, "set pp cores to %d\n", num_cores_enabled);
- MALI_DEBUG_ASSERT(0 == err);
- MALI_IGNORE(err);
- if (pdvfs[currentStep].freq_index != pdvfs[lastStep].freq_index) {
- mali_dev_pause();
- mali_clock_set(pdvfs[currentStep].freq_index);
- mali_dev_resume();
- lastStep = currentStep;
- }
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- get_current_frequency(),
- 0, 0, 0, 0);
-#endif
-}
-#endif
-
-u32 revise_set_clk(u32 val, u32 flush)
-{
- u32 ret = 0;
-#ifndef CONFIG_MALI_DVFS
- mali_scale_info_t* pinfo;
-
- pinfo = &pmali_plat->scale_info;
-
- if (val < pinfo->minclk)
- val = pinfo->minclk;
- else if (val > pinfo->maxclk)
- val = pinfo->maxclk;
-
- if (val != currentStep) {
- currentStep = val;
- if (flush)
- schedule_work(&wq_work);
- else
- ret = 1;
- }
-#endif
- return ret;
-}
-
-void get_mali_rt_clkpp(u32* clk, u32* pp)
-{
-#ifndef CONFIG_MALI_DVFS
- *clk = currentStep;
- *pp = num_cores_enabled;
-#endif
-}
-
-u32 set_mali_rt_clkpp(u32 clk, u32 pp, u32 flush)
-{
- u32 ret = 0;
-#ifndef CONFIG_MALI_DVFS
- mali_scale_info_t* pinfo;
- u32 flush_work = 0;
-
- pinfo = &pmali_plat->scale_info;
- if (clk < pinfo->minclk)
- clk = pinfo->minclk;
- else if (clk > pinfo->maxclk)
- clk = pinfo->maxclk;
-
- if (clk != currentStep) {
- currentStep = clk;
- if (flush)
- flush_work++;
- else
- ret = 1;
- }
- if (pp < pinfo->minpp)
- pp = pinfo->minpp;
- else if (pp > pinfo->maxpp)
- pp = pinfo->maxpp;
-
- if (pp != num_cores_enabled) {
- num_cores_enabled = pp;
- if (flush)
- flush_work++;
- else
- ret = 1;
- }
-
- if (flush_work)
- schedule_work(&wq_work);
-#endif
- return ret;
-}
-
-void revise_mali_rt(void)
-{
-#ifndef CONFIG_MALI_DVFS
- set_mali_rt_clkpp(currentStep, num_cores_enabled, 1);
-#endif
-}
-
-void flush_scaling_job(void)
-{
-#ifndef CONFIG_MALI_DVFS
- cancel_work_sync(&wq_work);
-#endif
-}
-
-#ifndef CONFIG_MALI_DVFS
-static u32 enable_one_core(void)
-{
- scalingdbg(2, "meson: one more pp, curent has %d pp cores\n", num_cores_enabled + 1);
- return set_mali_rt_clkpp(currentStep, num_cores_enabled + 1, 0);
-}
-
-static u32 disable_one_core(void)
-{
- scalingdbg(2, "meson: disable one pp, current has %d pp cores\n", num_cores_enabled - 1);
- return set_mali_rt_clkpp(currentStep, num_cores_enabled - 1, 0);
-}
-
-static u32 enable_max_num_cores(void)
-{
- return set_mali_rt_clkpp(currentStep, pmali_plat->scale_info.maxpp, 0);
-}
-
-static u32 enable_pp_cores(u32 val)
-{
- scalingdbg(2, "meson: enable %d pp cores\n", val);
- return set_mali_rt_clkpp(currentStep, val, 0);
-}
-#endif
-
-int mali_core_scaling_init(mali_plat_info_t *mali_plat)
-{
-#ifndef CONFIG_MALI_DVFS
- if (mali_plat == NULL) {
- scalingdbg(2, " Mali platform data is NULL!!!\n");
- return -1;
- }
-
- pmali_plat = mali_plat;
- num_cores_enabled = pmali_plat->sc_mpp;
-
- currentStep = pmali_plat->def_clock;
- lastStep = currentStep;
- INIT_WORK(&wq_work, do_scaling);
-#endif
- return 0;
- /* NOTE: Mali is not fully initialized at this point. */
-}
-
-void mali_core_scaling_term(void)
-{
-#ifndef CONFIG_MALI_DVFS
- flush_scheduled_work();
-#endif
-}
-
-#ifndef CONFIG_MALI_DVFS
-static u32 mali_threshold [] = {
- 102, /* 40% */
- 128, /* 50% */
- 230, /* 90% */
-};
-#endif
-
-void mali_pp_scaling_update(struct mali_gpu_utilization_data *data)
-{
-#ifndef CONFIG_MALI_DVFS
- int ret = 0;
-
- if (mali_threshold[2] < data->utilization_pp)
- ret = enable_max_num_cores();
- else if (mali_threshold[1]< data->utilization_pp)
- ret = enable_one_core();
- else if (0 < data->utilization_pp)
- ret = disable_one_core();
- if (ret == 1)
- schedule_work(&wq_work);
-#endif
-}
-
-#if LOG_MALI_SCALING
-void trace_utilization(struct mali_gpu_utilization_data *data, u32 current_idx, u32 next,
- u32 current_pp, u32 next_pp)
-{
- char direction;
- if (next > current_idx)
- direction = '>';
- else if ((current_idx > pmali_plat->scale_info.minpp) && (next < current_idx))
- direction = '<';
- else
- direction = '~';
-
- scalingdbg(2, "[SCALING]%c (%3d-->%3d)@%3d{%3d - %3d}. pp:(%d-->%d)\n",
- direction,
- get_mali_freq(current_idx),
- get_mali_freq(next),
- data->utilization_gpu,
- pmali_plat->dvfs_table[current_idx].downthreshold,
- pmali_plat->dvfs_table[current_idx].upthreshold,
- current_pp, next_pp);
-}
-#endif
-
-#ifndef CONFIG_MALI_DVFS
-static int mali_stay_count = 0;
-static void mali_decide_next_status(struct mali_gpu_utilization_data *data, int* next_fs_idx,
- int* pp_change_flag)
-{
- u32 utilization, mali_up_limit, decided_fs_idx;
- u32 ld_left, ld_right;
- u32 ld_up, ld_down;
- u32 change_mode;
-
- *pp_change_flag = 0;
- change_mode = 0;
- utilization = data->utilization_gpu;
-
- mali_up_limit = (scaling_mode == MALI_TURBO_MODE) ?
- pmali_plat->turbo_clock : pmali_plat->scale_info.maxclk;
- decided_fs_idx = currentStep;
-
- ld_up = pmali_plat->dvfs_table[currentStep].upthreshold;
- ld_down = pmali_plat->dvfs_table[currentStep].downthreshold;
-
- scalingdbg(2, "utilization=%d, ld_up=%d\n ", utilization, ld_up);
- if (utilization >= ld_up) { /* go up */
-
- scalingdbg(2, "currentStep=%d, mali_up_limit=%d\n ", currentStep, mali_up_limit);
- if (currentStep < mali_up_limit) {
- change_mode = 1;
- if ((currentStep < pmali_plat->def_clock) && (utilization > pmali_plat->bst_gpu))
- decided_fs_idx = pmali_plat->def_clock;
- else
- decided_fs_idx++;
- }
- if ((data->utilization_pp >= ld_up) &&
- (num_cores_enabled < pmali_plat->scale_info.maxpp)) {
- if ((num_cores_enabled < pmali_plat->sc_mpp) && (data->utilization_pp >= pmali_plat->bst_pp)) {
- *pp_change_flag = 1;
- change_mode = 1;
- } else if (change_mode == 0) {
- *pp_change_flag = 2;
- change_mode = 1;
- }
- }
-#if LOG_MALI_SCALING
- scalingdbg(2, "[nexting..] [LD:%d]-> FS[CRNT:%d LMT:%d NEXT:%d] PP[NUM:%d LMT:%d MD:%d][F:%d]\n",
- data->utilization_pp, currentStep, mali_up_limit, decided_fs_idx,
- num_cores_enabled, pmali_plat->scale_info.maxpp, *pp_change_flag, change_mode);
-#endif
- } else if (utilization <= ld_down) { /* go down */
- if (mali_stay_count > 0) {
- *next_fs_idx = decided_fs_idx;
- mali_stay_count--;
- return;
- }
-
- if (num_cores_enabled > pmali_plat->sc_mpp) {
- change_mode = 1;
- if (data->utilization_pp <= ld_down) {
- ld_left = data->utilization_pp * num_cores_enabled;
- ld_right = (pmali_plat->dvfs_table[currentStep].upthreshold) *
- (num_cores_enabled - 1);
- if (ld_left < ld_right) {
- change_mode = 2;
- }
- }
- } else if (currentStep > pmali_plat->scale_info.minclk) {
- change_mode = 1;
- } else if (num_cores_enabled > 1) { /* decrease PPS */
- if (data->utilization_pp <= ld_down) {
- ld_left = data->utilization_pp * num_cores_enabled;
- ld_right = (pmali_plat->dvfs_table[currentStep].upthreshold) *
- (num_cores_enabled - 1);
- scalingdbg(2, "ld_left=%d, ld_right=%d\n", ld_left, ld_right);
- if (ld_left < ld_right) {
- change_mode = 2;
- }
- }
- }
-
- if (change_mode == 1) {
- decided_fs_idx--;
- } else if (change_mode == 2) { /* decrease PPS */
- *pp_change_flag = -1;
- }
- }
- if (change_mode)
- mali_stay_count = pmali_plat->dvfs_table[decided_fs_idx].keep_count;
- *next_fs_idx = decided_fs_idx;
-}
-#endif
-
-void mali_pp_fs_scaling_update(struct mali_gpu_utilization_data *data)
-{
-#ifndef CONFIG_MALI_DVFS
- int ret = 0;
- int pp_change_flag = 0;
- u32 next_idx = 0;
-
-#if LOG_MALI_SCALING
- u32 last_pp = num_cores_enabled;
-#endif
- mali_decide_next_status(data, &next_idx, &pp_change_flag);
-
- if (pp_change_flag == 1)
- ret = enable_pp_cores(pmali_plat->sc_mpp);
- else if (pp_change_flag == 2)
- ret = enable_one_core();
- else if (pp_change_flag == -1) {
- ret = disable_one_core();
- }
-
-#if LOG_MALI_SCALING
- if (pp_change_flag || (next_idx != currentStep))
- trace_utilization(data, currentStep, next_idx, last_pp, num_cores_enabled);
-#endif
-
- if (next_idx != currentStep) {
- ret = 1;
- currentStep = next_idx;
- }
-
- if (ret == 1)
- schedule_work(&wq_work);
-#ifdef CONFIG_MALI400_PROFILING
- else
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- get_current_frequency(),
- 0, 0, 0, 0);
-#endif
-#endif
-}
-
-u32 get_mali_schel_mode(void)
-{
- return scaling_mode;
-}
-
-void set_mali_schel_mode(u32 mode)
-{
-#ifndef CONFIG_MALI_DVFS
- MALI_DEBUG_ASSERT(mode < MALI_SCALING_MODE_MAX);
- if (mode >= MALI_SCALING_MODE_MAX)
- return;
- scaling_mode = mode;
-
- /* set default performance range. */
- pmali_plat->scale_info.minclk = pmali_plat->cfg_min_clock;
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- pmali_plat->scale_info.minpp = pmali_plat->cfg_min_pp;
- pmali_plat->scale_info.maxpp = pmali_plat->cfg_pp;
-
- /* set current status and tune max freq */
- if (scaling_mode == MALI_PP_FS_SCALING) {
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- enable_pp_cores(pmali_plat->sc_mpp);
- } else if (scaling_mode == MALI_SCALING_DISABLE) {
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- enable_max_num_cores();
- } else if (scaling_mode == MALI_TURBO_MODE) {
- pmali_plat->scale_info.maxclk = pmali_plat->turbo_clock;
- enable_max_num_cores();
- }
- currentStep = pmali_plat->scale_info.maxclk;
- schedule_work(&wq_work);
-#endif
-}
-
-u32 get_current_frequency(void)
-{
- return get_mali_freq(currentStep);
-}
-
-void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data)
-{
-#ifndef CONFIG_MALI_DVFS
- if (mali_pm_statue)
- return;
-
- switch (scaling_mode) {
- case MALI_PP_FS_SCALING:
- mali_pp_fs_scaling_update(data);
- break;
- case MALI_PP_SCALING:
- mali_pp_scaling_update(data);
- break;
- default:
- break;
- }
-#endif
-}
-
-void mali_dev_restore(void)
-{
-#ifndef CONFIG_MALI_DVFS
- mali_dvfs_threshold_table * pdvfs = pmali_plat->dvfs_table;
-
- //mali_perf_set_num_pp_cores(num_cores_enabled);
- mali_clock_set(pdvfs[currentStep].freq_index);
-#endif
-}
+++ /dev/null
-/*
- * Copyright (C) 2010, 2012-2013 ARM Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
- *
- * A copy of the licence is included with the program, and can also be obtained from Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-#include <linux/version.h>
-#include <linux/dma-mapping.h>
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/ioport.h>
-#include <linux/slab.h>
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#endif
-#include <asm/io.h>
-
-#include "meson_main.h"
-#include <linux/mali/mali_utgard.h>
-#include "mali_kernel_common.h"
-#include "common/mali_pmu.h"
-#include "common/mali_osk_profiling.h"
-
-int mali_pm_statue = 0;
-u32 mali_gp_reset_fail = 0;
-module_param(mali_gp_reset_fail, int, S_IRUSR | S_IWUSR | S_IWGRP | S_IRGRP | S_IROTH); /* rw-rw-r-- */
-MODULE_PARM_DESC(mali_gp_reset_fail, "times of failed to reset GP");
-u32 mali_core_timeout = 0;
-module_param(mali_core_timeout, int, S_IRUSR | S_IWUSR | S_IWGRP | S_IRGRP | S_IROTH); /* rw-rw-r-- */
-MODULE_PARM_DESC(mali_core_timeout, "times of failed to reset GP");
-
-static struct mali_gpu_device_data mali_gpu_data =
-{
- .shared_mem_size = 1024 * 1024 * 1024,
- .max_job_runtime = 60000, /* 60 seconds */
- .pmu_switch_delay = 0xFFFF, /* do not have to be this high on FPGA, but it is good for testing to have a delay */
-#if defined(CONFIG_ARCH_MESON8B)||defined(CONFIG_ARCH_MESONG9BB)
- .pmu_domain_config = {0x1, 0x2, 0x4, 0x0,
- 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x1, 0x2, 0x0},
-#else
- .pmu_domain_config = {0x1, 0x2, 0x4, 0x4,
- 0x0, 0x8, 0x8, 0x8,
- 0x0, 0x1, 0x2, 0x8},
-#endif
-};
-
-static void mali_platform_device_release(struct device *device);
-static struct platform_device mali_gpu_device =
-{
- .name = MALI_GPU_NAME_UTGARD,
- .id = 0,
- .dev.release = mali_platform_device_release,
- .dev.coherent_dma_mask = DMA_BIT_MASK(32),
- .dev.platform_data = &mali_gpu_data,
- .dev.type = &mali_pm_device, /* We should probably use the pm_domain instead of type on newer kernels */
-};
-
-int mali_pdev_pre_init(struct platform_device* ptr_plt_dev)
-{
- MALI_DEBUG_PRINT(4, ("mali_platform_device_register() called\n"));
- if (mali_gpu_data.shared_mem_size < 10) {
- MALI_DEBUG_PRINT(2, ("mali os memory didn't configered, set to default(512M)\n"));
- mali_gpu_data.shared_mem_size = 1024 * 1024 *1024;
- }
- return mali_meson_init_start(ptr_plt_dev);
-}
-
-void mali_pdev_post_init(struct platform_device* pdev)
-{
- mali_gp_reset_fail = 0;
- mali_core_timeout = 0;
-#ifdef CONFIG_PM_RUNTIME
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
- pm_runtime_set_autosuspend_delay(&(pdev->dev), 1000);
- pm_runtime_use_autosuspend(&(pdev->dev));
-#endif
- pm_runtime_enable(&(pdev->dev));
-#endif
- mali_meson_init_finish(pdev);
-}
-
-int mali_pdev_dts_init(struct platform_device* mali_gpu_device)
-{
- struct device_node *cfg_node = mali_gpu_device->dev.of_node;
- struct device_node *child;
- u32 prop_value;
- int err;
-
- for_each_child_of_node(cfg_node, child) {
- err = of_property_read_u32(child, "shared_memory", &prop_value);
- if (err == 0) {
- MALI_DEBUG_PRINT(2, ("shared_memory configurate %d\n", prop_value));
- mali_gpu_data.shared_mem_size = prop_value * 1024 * 1024;
- }
- }
-
- err = mali_pdev_pre_init(mali_gpu_device);
- if (err == 0)
- mali_pdev_post_init(mali_gpu_device);
- return err;
-}
-
-int mali_platform_device_register(void)
-{
- int err = -1;
- err = mali_pdev_pre_init(&mali_gpu_device);
- if (err == 0) {
- err = platform_device_register(&mali_gpu_device);
- if (0 == err)
- mali_pdev_post_init(&mali_gpu_device);
- }
- return err;
-}
-
-void mali_platform_device_unregister(void)
-{
- MALI_DEBUG_PRINT(4, ("mali_platform_device_unregister() called\n"));
- mali_core_scaling_term();
- platform_device_unregister(&mali_gpu_device);
- platform_device_put(&mali_gpu_device);
-}
-
-static void mali_platform_device_release(struct device *device)
-{
- MALI_DEBUG_PRINT(4, ("mali_platform_device_release() called\n"));
-}
-
-
+++ /dev/null
-/*
- * mali_platform.h
- *
- * Created on: Nov 8, 2013
- * Author: amlogic
- */
-
-#ifndef MESON_MAIN_H_
-#define MESON_MAIN_H_
-#include <linux/version.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#ifdef CONFIG_PM_RUNTIME
-#include <linux/pm_runtime.h>
-#endif
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/cpu.h>
-#endif
-
-#include "mali_scaling.h"
-#include "mali_clock.h"
-
-extern struct device_type mali_pm_device;
-extern int mali_pm_statue;
-
-u32 set_max_mali_freq(u32 idx);
-u32 get_max_mali_freq(void);
-
-int mali_meson_init_start(struct platform_device* ptr_plt_dev);
-int mali_meson_init_finish(struct platform_device* ptr_plt_dev);
-int mali_meson_uninit(struct platform_device* ptr_plt_dev);
-int mali_light_suspend(struct device *device);
-int mali_light_resume(struct device *device);
-int mali_deep_suspend(struct device *device);
-int mali_deep_resume(struct device *device);
-
-#endif /* MESON_MAIN_H_ */
+++ /dev/null
-/*******************************************************************
- *
- * Copyright C 2013 by Amlogic, Inc. All Rights Reserved.
- *
- * Description:
- *
- * Author: Amlogic Software
- * Created: 2010/4/1 19:46
- *
- *******************************************************************/
-/* Standard Linux headers */
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/string.h>
-#include <linux/slab.h>
-#include <linux/list.h>
-
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/io.h>
-#include <plat/io.h>
-#include <asm/io.h>
-#endif
-
-#include <linux/mali/mali_utgard.h>
-#include <common/mali_kernel_common.h>
-#include <common/mali_pmu.h>
-#include "mali_pp_scheduler.h"
-#include "meson_main.h"
-
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
-static ssize_t domain_stat_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
-#if 0
- unsigned int val;
-
- val = readl((u32 *)(IO_AOBUS_BASE + 0xf0)) & 0xff;
- return sprintf(buf, "%x\n", val>>4);
-#else
- return 0;
-#endif
-}
-
-#define PREHEAT_CMD "preheat"
-#define PLL2_CMD "mpl2" /* mpl2 [11] or [0xxxxxxx] */
-#define SCMPP_CMD "scmpp" /* scmpp [number of pp your want in most of time]. */
-#define BSTGPU_CMD "bstgpu" /* bstgpu [0-256] */
-#define BSTPP_CMD "bstpp" /* bstpp [0-256] */
-#define LIMIT_CMD "lmt" /* lmt [0 or 1] */
-#define MAX_TOKEN 20
-#define FULL_UTILIZATION 256
-
-static ssize_t mpgpu_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- char *pstart, *cprt = NULL;
- u32 val = 0;
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
-
- cprt = skip_spaces(buf);
- pstart = strsep(&cprt," ");
- if (strlen(pstart) < 1)
- goto quit;
-
- if(!strncmp(pstart, PREHEAT_CMD, MAX_TOKEN)) {
- if (pmali_plat->plat_preheat) {
- pmali_plat->plat_preheat();
- }
- } else if (!strncmp(pstart, PLL2_CMD, MAX_TOKEN)) {
- int base = 10;
- if ((strlen(cprt) > 2) && (cprt[0] == '0') &&
- (cprt[1] == 'x' || cprt[1] == 'X'))
- base = 16;
- if (kstrtouint(cprt, base, &val) <0)
- goto quit;
- if (val < 11)
- pmali_plat->cfg_clock = pmali_plat->cfg_clock_bkup;
- else
- pmali_plat->cfg_clock = pmali_plat->turbo_clock;
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- set_str_src(val);
- } else if (!strncmp(pstart, SCMPP_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
- if ((val > 0) && (val < pmali_plat->cfg_pp)) {
- pmali_plat->sc_mpp = val;
- }
- } else if (!strncmp(pstart, BSTGPU_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
- if ((val > 0) && (val < FULL_UTILIZATION)) {
- pmali_plat->bst_gpu = val;
- }
- } else if (!strncmp(pstart, BSTPP_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
- if ((val > 0) && (val < FULL_UTILIZATION)) {
- pmali_plat->bst_pp = val;
- }
- } else if (!strncmp(pstart, LIMIT_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
-
- if (val < 2) {
- pmali_plat->limit_on = val;
- if (val == 0) {
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- pmali_plat->scale_info.maxpp = pmali_plat->cfg_pp;
- revise_mali_rt();
- }
- }
- }
-quit:
- return count;
-}
-
-static ssize_t scale_mode_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- return sprintf(buf, "%d\n", get_mali_schel_mode());
-}
-
-static ssize_t scale_mode_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
-
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- {
- return -EINVAL;
- }
-
- set_mali_schel_mode(val);
-
- return count;
-}
-
-static ssize_t max_pp_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- printk("maxpp:%d, maxpp_sysfs:%d, total=%d\n",
- pmali_plat->scale_info.maxpp, pmali_plat->maxpp_sysfs,
- mali_pp_scheduler_get_num_cores_total());
- return sprintf(buf, "%d\n", mali_pp_scheduler_get_num_cores_total());
-}
-
-static ssize_t max_pp_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pmali_plat->cfg_pp) || (val < pinfo->minpp))
- return -EINVAL;
-
- pmali_plat->maxpp_sysfs = val;
- pinfo->maxpp = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t min_pp_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- return sprintf(buf, "%d\n", pmali_plat->scale_info.minpp);
-}
-
-static ssize_t min_pp_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pinfo->maxpp) || (val < 1))
- return -EINVAL;
-
- pinfo->minpp = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t max_freq_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- printk("maxclk:%d, maxclk_sys:%d, max gpu level=%d\n",
- pmali_plat->scale_info.maxclk, pmali_plat->maxclk_sysfs, get_gpu_max_clk_level());
- return sprintf(buf, "%d\n", get_gpu_max_clk_level());
-}
-
-static ssize_t max_freq_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pmali_plat->cfg_clock) || (val < pinfo->minclk))
- return -EINVAL;
-
- pmali_plat->maxclk_sysfs = val;
- pinfo->maxclk = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t min_freq_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- return sprintf(buf, "%d\n", pmali_plat->scale_info.minclk);
-}
-
-static ssize_t min_freq_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pinfo->maxclk))
- return -EINVAL;
-
- pinfo->minclk = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t freq_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- return sprintf(buf, "%d\n", get_current_frequency());
-}
-
-static ssize_t freq_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- u32 clk, pp;
- get_mali_rt_clkpp(&clk, &pp);
-
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- return -EINVAL;
-
- set_mali_rt_clkpp(val, pp, 1);
-
- return count;
-}
-
-static ssize_t current_pp_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- u32 clk, pp;
- get_mali_rt_clkpp(&clk, &pp);
- return sprintf(buf, "%d\n", pp);
-}
-
-static ssize_t current_pp_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- u32 clk, pp;
-
- get_mali_rt_clkpp(&clk, &pp);
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- {
- return -EINVAL;
- }
-
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- return -EINVAL;
-
- set_mali_rt_clkpp(clk, val, 1);
-
- return count;
-}
-
-static struct class_attribute mali_class_attrs[] = {
- __ATTR(domain_stat, 0644, domain_stat_read, NULL),
- __ATTR(mpgpucmd, 0644, NULL, mpgpu_write),
- __ATTR(scale_mode, 0644, scale_mode_read, scale_mode_write),
- __ATTR(min_freq, 0644, min_freq_read, min_freq_write),
- __ATTR(max_freq, 0644, max_freq_read, max_freq_write),
- __ATTR(min_pp, 0644, min_pp_read, min_pp_write),
- __ATTR(max_pp, 0644, max_pp_read, max_pp_write),
- __ATTR(cur_freq, 0644, freq_read, freq_write),
- __ATTR(cur_pp, 0644, current_pp_read, current_pp_write),
-};
-
-static struct class mpgpu_class = {
- .name = "mpgpu",
-};
-#endif
-
-int mpgpu_class_init(void)
-{
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
- int ret = 0;
- int i;
- int attr_num = ARRAY_SIZE(mali_class_attrs);
-
- ret = class_register(&mpgpu_class);
- if (ret) {
- printk(KERN_ERR "%s: class_register failed\n", __func__);
- return ret;
- }
- for (i = 0; i< attr_num; i++) {
- ret = class_create_file(&mpgpu_class, &mali_class_attrs[i]);
- if (ret) {
- printk(KERN_ERR "%d ST: class item failed to register\n", i);
- }
- }
- return ret;
-#else
- return 0;
-#endif
-}
-
-void mpgpu_class_exit(void)
-{
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
- class_unregister(&mpgpu_class);
-#endif
-}
-
#
# This file is called by the Linux build system.
-include $(src)/Kbuild.amlogic
-# set up defaults if not defined by the user
-TIMESTAMP ?= default
-ifeq ($(CONFIG_UMP), m)
- USING_UMP ?= 1
-else
- USING_UMP ?= 0
-endif
-ifneq ($(KBUILD_SRC),)
- ifneq ($(wildcard $(KBUILD_SRC)/$(src)),)
- TOP_KBUILD_SRC := $(KBUILD_SRC)/
- endif
-endif
+# set up defaults if not defined by the user
+include $(src)/platform/Kbuild.amlogic
+TIMESTAMP ?= default
OS_MEMORY_KERNEL_BUFFER_SIZE_IN_MB ?= 16
-
-#USING_GPU_UTILIZATION ?= 0
-#PROFILING_SKIP_PP_JOBS ?= 0
-#PROFILING_SKIP_PP_AND_GP_JOBS ?= 0
-ifeq ($(CONFIG_MALI_DVFS),y)
- ccflags-y += -DCONFIG_MALI_DVFS
- USING_GPU_UTILIZATION=0
- USING_DVFS=1
-else
- USING_GPU_UTILIZATION=1
- USING_DVFS=0
-endif
+USING_GPU_UTILIZATION ?= 0
PROFILING_SKIP_PP_JOBS ?= 0
PROFILING_SKIP_PP_AND_GP_JOBS ?= 0
-############## Kasin Added, for platform. ################
-
-ifeq ($(CONFIG_MALI400_DEBUG),y)
- BUILD ?= debug
-else
- BUILD ?= release
- #ldflags-y += --strip-debug
-
-endif
-##################### end Kasin Added. ###################
-
MALI_PP_SCHEDULER_FORCE_NO_JOB_OVERLAP ?= 0
MALI_PP_SCHEDULER_KEEP_SUB_JOB_STARTS_ALIGNED ?= 0
MALI_PP_SCHEDULER_FORCE_NO_JOB_OVERLAP_BETWEEN_APPS ?= 0
MALI_UPPER_HALF_SCHEDULING ?= 1
-
-############## Kasin Added, useless now. ################
-# Get path to driver source from Linux build system
-DRIVER_DIR=$(src)
-##################### end Kasin Added. ###################
-
MALI_ENABLE_CPU_CYCLES ?= 0
# For customer releases the Linux Device Drivers will be provided as ARM proprietary and GPL releases:
# The ARM proprietary product will only include the license/proprietary directory
# The GPL product will only include the license/gpl directory
-ifeq ($(wildcard $(TOP_KBUILD_SRC)$(DRIVER_DIR)/linux/license/gpl/*),)
- ccflags-y += -I$(TOP_KBUILD_SRC)$(DRIVER_DIR)/linux/license/proprietary
+ifeq ($(wildcard $(src)/linux/license/gpl/*),)
+ ccflags-y += -I$(src)/linux/license/proprietary
ifeq ($(CONFIG_MALI400_PROFILING),y)
$(error Profiling is incompatible with non-GPL license)
endif
endif
$(error Linux Device integration is incompatible with non-GPL license)
else
- ccflags-y += -I$(TOP_KBUILD_SRC)$(DRIVER_DIR)/linux/license/gpl
+ ccflags-y += -I$(src)/linux/license/gpl
endif
ifeq ($(USING_GPU_UTILIZATION), 1)
linux/mali_pmu_power_up_down.o \
__malidrv_build_info.o
-############## Kasin Added, for platform. ################
-ifeq (true,false)
-mali-y += \
- platform/meson_main.o \
- platform/mali_pm_device.o \
- platform/mali_clock.o \
- platform/mpgpu.o
-else
-mali-y += \
- platform/mali_pm_device.o \
- platform/meson_bu/meson_main2.o \
- platform/meson_bu/mali_clock.o \
- platform/meson_bu/mpgpu.o \
- platform/meson_bu/platform_gx.o
-endif
-ifeq ($(CONFIG_MALI_DVFS),y)
- mali-y += platform/meson_bu/mali_dvfs.o
-else
- mali-y += platform/meson_bu/scaling.o
-endif
-
-ifeq ($(TARGET_PLATFORM),meson_m400)
-MALI_PLATFORM_FILES:= \
- platform/meson_m400/mali_fix.o \
- platform/meson_m400/mali_platform.o \
- platform/meson_m400/platform_mx.o
-endif
-
-ifeq ($(TARGET_PLATFORM),meson_m450)
-ccflags-y += -DCONFIG_MALI450=y
-mali-y += \
- platform/meson_m450/scaling.o
-
-mali-$(CONFIG_ARCH_MESON) += \
- platform/meson_m450/platform_m8.o
-
-mali-$(CONFIG_ARCH_MESON8) += \
- platform/meson_m450/platform_m8.o
-
-mali-$(CONFIG_ARCH_MESON6TVD) += \
- platform/meson_m450/platform_m6tvd.o
-
-mali-$(CONFIG_ARCH_MESON8B) += \
- platform/meson_m450/platform_m8b.o
-
-mali-$(CONFIG_ARCH_MESONG9TV) += \
- platform/meson_m450/platform_m8.o
-
-mali-$(CONFIG_ARCH_MESONG9BB) += \
- platform/meson_m450/platform_m8b.o
-endif
-##################### end Kasin Added. ###################
-
ifneq ($(wildcard $(src)/linux/mali_slp_global_lock.c),)
mali-y += linux/mali_slp_global_lock.o
endif
ccflags-y += -DMALI_OS_MEMORY_KERNEL_BUFFER_SIZE_IN_MB=$(OS_MEMORY_KERNEL_BUFFER_SIZE_IN_MB)
ccflags-y += -DUSING_GPU_UTILIZATION=$(USING_GPU_UTILIZATION)
ccflags-y += -DMALI_ENABLE_CPU_CYCLES=$(MALI_ENABLE_CPU_CYCLES)
-ccflags-y += -DMALI_FAKE_PLATFORM_DEVICE
ifeq ($(MALI_UPPER_HALF_SCHEDULING),1)
ccflags-y += -DMALI_UPPER_HALF_SCHEDULING
ifeq ($(MALI_PLATFORM_FILES),)
ccflags-$(CONFIG_MALI400_UMP) += -I$(src)/../ump/include/
else
-ccflags-$(CONFIG_MALI400_UMP) += -I$(src)/../ump/include/ump
-ccflags-$(CONFIG_MALI400_DEBUG) += -DDEBUG
+ccflags-$(CONFIG_MALI400_UMP) += -I$(src)/../../ump/include/ump
endif
+ccflags-$(CONFIG_MALI400_DEBUG) += -DDEBUG
# Use our defines when compiling
ccflags-y += -I$(src) -I$(src)/include -I$(src)/common -I$(src)/linux -I$(src)/platform
# Get subversion revision number, fall back to only ${MALI_RELEASE_NAME} if no svn info is available
-MALI_RELEASE_NAME=$(shell cat $(TOP_KBUILD_SRC)$(DRIVER_DIR)/.version 2> /dev/null)
+MALI_RELEASE_NAME=$(shell cat $(src)/.version 2> /dev/null)
-SVN_INFO = (cd $(TOP_KBUILD_SRC)$(DRIVER_DIR); svn info 2>/dev/null)
+SVN_INFO = (cd $(src); svn info 2>/dev/null)
ifneq ($(shell $(SVN_INFO) 2>/dev/null),)
# SVN detected
REPO_URL := $(shell $(SVN_INFO) | grep '^URL: ' | cut -d: -f2- | cut -b2-)
else # SVN
-GIT_REV := $(shell cd $(TOP_KBUILD_SRC)$(DRIVER_DIR); git describe --always 2>/dev/null)
+GIT_REV := $(shell cd $(src); git describe --always 2>/dev/null)
ifneq ($(GIT_REV),)
# Git detected
DRIVER_REV := $(MALI_RELEASE_NAME)-$(GIT_REV)
-CHANGE_DATE := $(shell cd $(TOP_KBUILD_SRC)$(DRIVER_DIR); git log -1 --format="%ci")
+CHANGE_DATE := $(shell cd $(src); git log -1 --format="%ci")
CHANGED_REVISION := $(GIT_REV)
-REPO_URL := $(shell cd $(TOP_KBUILD_SRC)$(DRIVER_DIR); git describe --all --always 2>/dev/null)
+REPO_URL := $(shell cd $(src); git describe --all --always 2>/dev/null)
else # Git
# No Git or SVN detected
ccflags-y += -DSVN_REV_STRING=\"$(DRIVER_REV)\"
VERSION_STRINGS :=
-VERSION_STRINGS += API_VERSION=$(shell cd $(TOP_KBUILD_SRC)$(DRIVER_DIR); grep "\#define _MALI_API_VERSION" $(FILES_PREFIX)include/linux/mali/mali_utgard_uk_types.h | cut -d' ' -f 3 )
+VERSION_STRINGS += API_VERSION=$(shell cd $(src); grep "\#define _MALI_API_VERSION" $(FILES_PREFIX)include/linux/mali/mali_utgard_uk_types.h | cut -d' ' -f 3 )
VERSION_STRINGS += REPO_URL=$(REPO_URL)
VERSION_STRINGS += REVISION=$(DRIVER_REV)
VERSION_STRINGS += CHANGED_REVISION=$(CHANGED_REVISION)
VERSION_STRINGS += MALI_UPPER_HALF_SCHEDULING=$(MALI_UPPER_HALF_SCHEDULING)
# Create file with Mali driver configuration
-$(TOP_KBUILD_SRC)$(DRIVER_DIR)/__malidrv_build_info.c:
- @echo 'const char *__malidrv_build_info(void) { return "malidrv: $(VERSION_STRINGS)";}' > $(TOP_KBUILD_SRC)$(DRIVER_DIR)/__malidrv_build_info.c
+$(src)/__malidrv_build_info.c:
+ @echo 'const char *__malidrv_build_info(void) { return "malidrv: $(VERSION_STRINGS)";}' > $(src)/__malidrv_build_info.c
+++ /dev/null
-############## Kasin Added, for platform. ################
-
-ifndef CONFIG_MALI_DMA_BUF_MAP_ON_ATTACH
- ccflags-y += -DCONFIG_MALI_DMA_BUF_MAP_ON_ATTACH=y
-endif
-
-ccflags-y += -DCONFIG_MALI_DT=y
-ccflags-y += -DMESON_CPU_TYPE=0x80
-ccflags-y += -DMESON_CPU_TYPE_MESON6=0x60
-ccflags-y += -DMESON_CPU_TYPE_MESON6TVD=0x75
-ccflags-y += -DMESON_CPU_TYPE_MESON8=0x80
-ccflags-y += -DMESON_CPU_TYPE_MESON8B=0x8B
-
-USE_GPPLL?=0
-ifdef CONFIG_AM_VIDEO
- USE_GPPLL:=1
-endif
-
-ccflags-y += -DAMLOGIC_GPU_USE_GPPLL=$(USE_GPPLL)
+++ /dev/null
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#include <plat/io.h>
-#endif
-
-#include <linux/io.h>
-
-#include <asm/io.h>
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 29))
-#include <linux/amlogic/iomap.h>
-#endif
-#include "meson_main.h"
-
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6TVD
-
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 29))
-#define HHI_MALI_CLK_CNTL 0x106C
-#define mplt_read(r) aml_read_cbus((r))
-#define mplt_write(v, r) aml_write_cbus((r), (v))
-#define mplt_setbits(r, m) aml_write_cbus((r), (aml_read_cbus(r) | (m)));
-#define mplt_clrbits(r, m) aml_write_cbus((r), (aml_read_cbus(r) & (~(m))));
-#else
-#define mplt_read(r) aml_read_reg32((P_##r))
-#define mplt_write(v, r) aml_write_reg32((P_##r), (v))
-#define mplt_setbits(r, m) aml_write_reg32((P_##r), (aml_read_reg32(P_##r) | (m)));
-#define mplt_clrbits(r, m) aml_write_reg32((P_##r), (aml_read_reg32(P_##r) & (~(m))));
-#endif
-#define FCLK_MPLL2 (2 << 9)
-static DEFINE_SPINLOCK(lock);
-static mali_plat_info_t* pmali_plat = NULL;
-static u32 mali_extr_backup = 0;
-static u32 mali_extr_sample_backup = 0;
-
-int mali_clock_init(mali_plat_info_t* mali_plat)
-{
- u32 def_clk_data;
- if (mali_plat == NULL) {
- printk(" Mali platform data is NULL!!!\n");
- return -1;
- }
-
- pmali_plat = mali_plat;
- if (pmali_plat->have_switch) {
- def_clk_data = pmali_plat->clk[pmali_plat->def_clock];
- mplt_write(def_clk_data | (def_clk_data << 16), HHI_MALI_CLK_CNTL);
- mplt_setbits(HHI_MALI_CLK_CNTL, 1 << 24);
- mplt_setbits(HHI_MALI_CLK_CNTL, 1 << 8);
- } else {
- mali_clock_set(pmali_plat->def_clock);
- }
-
- mali_extr_backup = pmali_plat->clk[pmali_plat->clk_len - 1];
- mali_extr_sample_backup = pmali_plat->clk_sample[pmali_plat->clk_len - 1];
- return 0;
-}
-
-int mali_clock_critical(critical_t critical, size_t param)
-{
- int ret = 0;
- unsigned long flags;
-
- spin_lock_irqsave(&lock, flags);
- ret = critical(param);
- spin_unlock_irqrestore(&lock, flags);
- return ret;
-}
-
-static int critical_clock_set(size_t param)
-{
- unsigned int idx = param;
- if (pmali_plat->have_switch) {
- u32 clk_value;
- mplt_setbits(HHI_MALI_CLK_CNTL, 1 << 31);
- clk_value = mplt_read(HHI_MALI_CLK_CNTL) & 0xffff0000;
- clk_value = clk_value | pmali_plat->clk[idx] | (1 << 8);
- mplt_write(clk_value, HHI_MALI_CLK_CNTL);
- mplt_clrbits(HHI_MALI_CLK_CNTL, 1 << 31);
- } else {
- mplt_clrbits(HHI_MALI_CLK_CNTL, 1 << 8);
- mplt_clrbits(HHI_MALI_CLK_CNTL, (0x7F | (0x7 << 9)));
- mplt_write(pmali_plat->clk[idx], HHI_MALI_CLK_CNTL);
- mplt_setbits(HHI_MALI_CLK_CNTL, 1 << 8);
- }
- return 0;
-}
-
-int mali_clock_set(unsigned int clock)
-{
- return mali_clock_critical(critical_clock_set, (size_t)clock);
-}
-
-void disable_clock(void)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&lock, flags);
- mplt_clrbits(HHI_MALI_CLK_CNTL, 1 << 8);
- spin_unlock_irqrestore(&lock, flags);
-}
-
-void enable_clock(void)
-{
- u32 ret;
- unsigned long flags;
-
- spin_lock_irqsave(&lock, flags);
- mplt_setbits(HHI_MALI_CLK_CNTL, 1 << 8);
- ret = mplt_read(HHI_MALI_CLK_CNTL) & (1 << 8);
- spin_unlock_irqrestore(&lock, flags);
-}
-
-u32 get_mali_freq(u32 idx)
-{
- if (!mali_pm_statue) {
- return pmali_plat->clk_sample[idx];
- } else {
- return 0;
- }
-}
-
-void set_str_src(u32 data)
-{
-#if 0
- if (data == 11) {
- writel(0x0004d000, (u32*)P_HHI_MPLL_CNTL9);
- } else if (data > 11) {
- writel(data, (u32*)P_HHI_MPLL_CNTL9);
- }
-#endif
- if (data == 0) {
- pmali_plat->clk[pmali_plat->clk_len - 1] = mali_extr_backup;
- pmali_plat->clk_sample[pmali_plat->clk_len - 1] = mali_extr_sample_backup;
- } else if (data > 10) {
- pmali_plat->clk_sample[pmali_plat->clk_len - 1] = 600;
- pmali_plat->clk[pmali_plat->clk_len - 1] = FCLK_MPLL2;
- }
-}
-#endif
+++ /dev/null
-#ifndef _MALI_CLOCK_H_
-#define _MALI_CLOCK_H_
-
-typedef int (*critical_t)(size_t param);
-int mali_clock_critical(critical_t critical, size_t param);
-
-int mali_clock_init(mali_plat_info_t*);
-int mali_clock_set(unsigned int index);
-void disable_clock(void);
-void enable_clock(void);
-u32 get_mali_freq(u32 idx);
-void set_str_src(u32 data);
-#endif /* _MALI_CLOCK_H_ */
+++ /dev/null
-/*
- * mali_platform.h
- *
- * Created on: Nov 8, 2013
- * Author: amlogic
- */
-
-#include <linux/kernel.h>
-#ifndef MALI_PLATFORM_H_
-#define MALI_PLATFORM_H_
-
-extern u32 mali_gp_reset_fail;
-extern u32 mali_core_timeout;
-
-#endif /* MALI_PLATFORM_H_ */
+++ /dev/null
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/module.h> /* kernel module definitions */
-#include <linux/ioport.h> /* request_mem_region */
-#include <linux/slab.h>
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#endif
-#include "meson_main.h"
-#include <common/mali_kernel_common.h>
-#include <common/mali_osk_profiling.h>
-#include <common/mali_pmu.h>
-#include <linux/mali/mali_utgard.h>
-
-static int mali_os_suspend(struct device *device)
-{
- int ret = 0;
-
- MALI_DEBUG_PRINT(4, ("mali_os_suspend() called\n"));
- ret = mali_deep_suspend(device);
-
- return ret;
-}
-
-static int mali_os_resume(struct device *device)
-{
- int ret = 0;
-
- MALI_DEBUG_PRINT(4, ("mali_os_resume() called\n"));
-
- ret = mali_deep_resume(device);
-
- return ret;
-}
-
-static int mali_os_freeze(struct device *device)
-{
- int ret = 0;
-
- MALI_DEBUG_PRINT(4, ("mali_os_freeze() called\n"));
-
- mali_dev_freeze();
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->freeze)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->freeze(device);
- }
-
- return ret;
-}
-//copy from r4p1 linux/mali_pmu_power_up_down.c
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
-static int mali_pmu_powerup(void)
-{
- struct mali_pmu_core *pmu = mali_pmu_get_global_pmu_core();
-
- MALI_DEBUG_PRINT(5, ("Mali PMU: Power up\n"));
-
- MALI_DEBUG_ASSERT_POINTER(pmu);
- if (NULL == pmu) {
- return -ENXIO;
- }
-
- mali_pmu_power_up_all(pmu);
-
- return 0;
-}
-#endif
-
-static int mali_os_thaw(struct device *device)
-{
- int ret = 0;
-
- MALI_DEBUG_PRINT(4, ("mali_os_thaw() called\n"));
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
- enable_clock();
- mali_pmu_powerup();
-#endif
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->thaw)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->thaw(device);
- }
-
- return ret;
-}
-
-static int mali_os_restore(struct device *device)
-{
- MALI_DEBUG_PRINT(4, ("mali_os_thaw() called\n"));
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
- mali_dev_restore();
-#endif
- return mali_os_resume(device);
-}
-
-#ifdef CONFIG_PM_RUNTIME
-#if 0
-static int mali_runtime_suspend(struct device *device)
-{
- int ret = 0;
-
- MALI_DEBUG_PRINT(4, ("mali_runtime_suspend() called\n"));
- ret = mali_light_suspend(device);
-
- return ret;
-}
-
-static int mali_runtime_resume(struct device *device)
-{
- int ret = 0;
-
- MALI_DEBUG_PRINT(4, ("mali_run time_resume() called\n"));
- ret = mali_light_resume(device);
-
- return ret;
-}
-
-static int mali_runtime_idle(struct device *device)
-{
- MALI_DEBUG_PRINT(4, ("mali_runtime_idle() called\n"));
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_idle)
- {
- /* Need to notify Mali driver about this event */
- int ret = device->driver->pm->runtime_idle(device);
- if (0 != ret)
- {
- return ret;
- }
- }
-
- pm_runtime_suspend(device);
-
- return 0;
-}
-#endif
-#endif
-
-static struct dev_pm_ops mali_gpu_device_type_pm_ops =
-{
- .suspend = mali_os_suspend,
- .resume = mali_os_resume,
- .freeze = mali_os_freeze,
- .thaw = mali_os_thaw,
- .restore = mali_os_restore,
-#if 0//def CONFIG_PM_RUNTIME
- .runtime_suspend = mali_runtime_suspend,
- .runtime_resume = mali_runtime_resume,
- .runtime_idle = mali_runtime_idle,
-#endif
-};
-
-struct device_type mali_pm_device =
-{
- .pm = &mali_gpu_device_type_pm_ops,
-};
+++ /dev/null
-/*
- * Copyright (C) 2013 ARM Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
- *
- * A copy of the licence is included with the program, and can also be obtained from Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-/**
- * @file arm_core_scaling.h
- * Example core scaling policy.
- */
-
-#ifndef __ARM_CORE_SCALING_H__
-#define __ARM_CORE_SCALING_H__
-
-#include <linux/types.h>
-#include <linux/workqueue.h>
-#include <linux/clk-provider.h>
-#include <linux/clk.h>
-
-enum mali_scale_mode_t {
- MALI_PP_SCALING = 0,
- MALI_PP_FS_SCALING,
- MALI_SCALING_DISABLE,
- MALI_TURBO_MODE,
- MALI_SCALING_MODE_MAX
-};
-
-typedef struct mali_dvfs_threshold_table {
- uint32_t freq_index;
- uint32_t voltage;
- uint32_t keep_count;
- uint32_t downthreshold;
- uint32_t upthreshold;
- uint32_t clk_freq;
- const char *clk_parent;
- struct clk *clkp_handle;
- uint32_t clkp_freq;
-} mali_dvfs_threshold_table;
-
-/**
- * restrictions on frequency and number of pp.
- */
-typedef struct mali_scale_info_t {
- u32 minpp;
- u32 maxpp;
- u32 minclk;
- u32 maxclk;
-} mali_scale_info_t;
-
-/**
- * Platform spesific data for meson chips.
- */
-typedef struct mali_plat_info_t {
- u32 cfg_pp; /* number of pp. */
- u32 cfg_min_pp;
- u32 turbo_clock; /* reserved clock src. */
- u32 def_clock; /* gpu clock used most of time.*/
- u32 cfg_clock; /* max clock could be used.*/
- u32 cfg_clock_bkup; /* same as cfg_clock, for backup. */
- u32 cfg_min_clock;
-
- u32 sc_mpp; /* number of pp used most of time.*/
- u32 bst_gpu; /* threshold for boosting gpu. */
- u32 bst_pp; /* threshold for boosting PP. */
-
- u32 *clk;
- u32 *clk_sample;
- u32 clk_len;
- u32 have_switch; /* have clock gate switch or not. */
-
- mali_dvfs_threshold_table *dvfs_table;
- struct mali_gpu_clk_item *clk_items;
- u32 dvfs_table_size;
-
- mali_scale_info_t scale_info;
- u32 maxclk_sysfs;
- u32 maxpp_sysfs;
-
- /* set upper limit of pp or frequency, for THERMAL thermal or band width saving.*/
- u32 limit_on;
-
- /* for boost up gpu by user. */
- void (*plat_preheat)(void);
-
- struct platform_device *pdev;
- void __iomem *reg_base_hiubus;
- void __iomem *reg_base_aobus;
- struct work_struct wq_work;
- struct clk *clk_mali;
- struct clk *clk_mali_0;
- struct clk *clk_mali_1;
-} mali_plat_info_t;
-mali_plat_info_t* get_mali_plat_data(void);
-
-/**
- * Initialize core scaling policy.
- *
- * @note The core scaling policy will assume that all PP cores are on initially.
- *
- * @param num_pp_cores Total number of PP cores.
- */
-int mali_core_scaling_init(mali_plat_info_t*);
-
-/**
- * Terminate core scaling policy.
- */
-void mali_core_scaling_term(void);
-
-/**
- * cancel and flush scaling job queue.
- */
-void flush_scaling_job(void);
-
-/* get current state(pp, clk). */
-void get_mali_rt_clkpp(u32* clk, u32* pp);
-u32 set_mali_rt_clkpp(u32 clk, u32 pp, u32 flush);
-void revise_mali_rt(void);
-/* get max gpu clk level of this chip*/
-int get_gpu_max_clk_level(void);
-
-/* get or set the scale mode. */
-u32 get_mali_schel_mode(void);
-void set_mali_schel_mode(u32 mode);
-
-/* for frequency reporter in DS-5 streamline. */
-u32 get_current_frequency(void);
-void mali_dev_freeze(void);
-void mali_dev_restore(void);
-
-extern int mali_pm_statue;
-#endif /* __ARM_CORE_SCALING_H__ */
+++ /dev/null
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <linux/clk-provider.h>
-#include <linux/clk.h>
-#include <linux/of_address.h>
-#include <linux/delay.h>
-#include <linux/mali/mali_utgard.h>
-#include <linux/amlogic/cpu_version.h>
-#include "mali_scaling.h"
-#include "mali_clock.h"
-
-#ifndef AML_CLK_LOCK_ERROR
-#define AML_CLK_LOCK_ERROR 1
-#endif
-#define GXBBM_MAX_GPU_FREQ 700000000UL
-struct clk;
-static unsigned gpu_dbg_level = 0;
-module_param(gpu_dbg_level, uint, 0644);
-MODULE_PARM_DESC(gpu_dbg_level, "gpu debug level");
-
-#define gpu_dbg(level, fmt, arg...) \
- do { \
- if (gpu_dbg_level >= (level)) \
- printk("gpu_debug"fmt , ## arg); \
- } while (0)
-
-#define GPU_CLK_DBG(fmt, arg...)
-
-//disable print
-#define _dev_info(...)
-
-//static DEFINE_SPINLOCK(lock);
-static mali_plat_info_t* pmali_plat = NULL;
-//static u32 mali_extr_backup = 0;
-//static u32 mali_extr_sample_backup = 0;
-struct timeval start;
-struct timeval end;
-
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 16))
-int mali_clock_init_clk_tree(struct platform_device* pdev)
-{
- mali_dvfs_threshold_table *dvfs_tbl = &pmali_plat->dvfs_table[pmali_plat->def_clock];
- struct clk *clk_mali_0_parent = dvfs_tbl->clkp_handle;
- struct clk *clk_mali_0 = pmali_plat->clk_mali_0;
-#ifdef AML_CLK_LOCK_ERROR
- struct clk *clk_mali_1 = pmali_plat->clk_mali_1;
-#endif
- struct clk *clk_mali = pmali_plat->clk_mali;
-
- clk_set_parent(clk_mali_0, clk_mali_0_parent);
-
- clk_prepare_enable(clk_mali_0);
-
- clk_set_parent(clk_mali, clk_mali_0);
-
-#ifdef AML_CLK_LOCK_ERROR
- clk_set_parent(clk_mali_1, clk_mali_0_parent);
- clk_prepare_enable(clk_mali_1);
-#endif
-
- GPU_CLK_DBG("%s:enable(%d), %s:enable(%d)\n",
- clk_mali_0->name, clk_mali_0->enable_count,
- clk_mali_0_parent->name, clk_mali_0_parent->enable_count);
-
- return 0;
-}
-
-int mali_clock_init(mali_plat_info_t *pdev)
-{
- *pdev = *pdev;
- return 0;
-}
-
-int mali_clock_critical(critical_t critical, size_t param)
-{
- int ret = 0;
-
- ret = critical(param);
-
- return ret;
-}
-
-static int critical_clock_set(size_t param)
-{
- int ret = 0;
- unsigned int idx = param;
- mali_dvfs_threshold_table *dvfs_tbl = &pmali_plat->dvfs_table[idx];
-
- struct clk *clk_mali_0 = pmali_plat->clk_mali_0;
- struct clk *clk_mali_1 = pmali_plat->clk_mali_1;
- struct clk *clk_mali_x = NULL;
- struct clk *clk_mali_x_parent = NULL;
- struct clk *clk_mali_x_old = NULL;
- struct clk *clk_mali = pmali_plat->clk_mali;
- unsigned long time_use=0;
-
- clk_mali_x_old = clk_get_parent(clk_mali);
-
- if (!clk_mali_x_old) {
- printk("gpu: could not get clk_mali_x_old or clk_mali_x_old\n");
- return 0;
- }
- if (clk_mali_x_old == clk_mali_0) {
- clk_mali_x = clk_mali_1;
- } else if (clk_mali_x_old == clk_mali_1) {
- clk_mali_x = clk_mali_0;
- } else {
- printk("gpu: unmatched clk_mali_x_old\n");
- return 0;
- }
-
- GPU_CLK_DBG("idx=%d, clk_freq=%d\n", idx, dvfs_tbl->clk_freq);
- clk_mali_x_parent = dvfs_tbl->clkp_handle;
- if (!clk_mali_x_parent) {
- printk("gpu: could not get clk_mali_x_parent\n");
- return 0;
- }
-
- GPU_CLK_DBG();
- ret = clk_set_rate(clk_mali_x_parent, dvfs_tbl->clkp_freq);
- GPU_CLK_DBG();
- ret = clk_set_parent(clk_mali_x, clk_mali_x_parent);
- GPU_CLK_DBG();
- ret = clk_set_rate(clk_mali_x, dvfs_tbl->clk_freq);
- GPU_CLK_DBG();
-#ifndef AML_CLK_LOCK_ERROR
- ret = clk_prepare_enable(clk_mali_x);
-#endif
- GPU_CLK_DBG("new %s:enable(%d)\n", clk_mali_x->name, clk_mali_x->enable_count);
- do_gettimeofday(&start);
- udelay(1);// delay 10ns
- do_gettimeofday(&end);
- ret = clk_set_parent(clk_mali, clk_mali_x);
- GPU_CLK_DBG();
-
-#ifndef AML_CLK_LOCK_ERROR
- clk_disable_unprepare(clk_mali_x_old);
-#endif
- GPU_CLK_DBG("old %s:enable(%d)\n", clk_mali_x_old->name, clk_mali_x_old->enable_count);
- time_use = (end.tv_sec - start.tv_sec)*1000000 + end.tv_usec - start.tv_usec;
- GPU_CLK_DBG("step 1, mali_mux use: %ld us\n", time_use);
-
- return 0;
-}
-
-int mali_clock_set(unsigned int clock)
-{
- return mali_clock_critical(critical_clock_set, (size_t)clock);
-}
-
-void disable_clock(void)
-{
- struct clk *clk_mali = pmali_plat->clk_mali;
- struct clk *clk_mali_x = NULL;
-
- clk_mali_x = clk_get_parent(clk_mali);
- GPU_CLK_DBG();
-#ifndef AML_CLK_LOCK_ERROR
- clk_disable_unprepare(clk_mali_x);
-#endif
- GPU_CLK_DBG();
-}
-
-void enable_clock(void)
-{
- struct clk *clk_mali = pmali_plat->clk_mali;
- struct clk *clk_mali_x = NULL;
-
- clk_mali_x = clk_get_parent(clk_mali);
- GPU_CLK_DBG();
-#ifndef AML_CLK_LOCK_ERROR
- clk_prepare_enable(clk_mali_x);
-#endif
- GPU_CLK_DBG();
-}
-
-u32 get_mali_freq(u32 idx)
-{
- if (!mali_pm_statue) {
- return pmali_plat->clk_sample[idx];
- } else {
- return 0;
- }
-}
-
-void set_str_src(u32 data)
-{
- printk("gpu: %s, %s, %d\n", __FILE__, __func__, __LINE__);
-}
-
-int mali_dt_info(struct platform_device *pdev, struct mali_plat_info_t *mpdata)
-{
- struct device_node *gpu_dn = pdev->dev.of_node;
- struct device_node *gpu_clk_dn;
- struct mali_gpu_clk_item *clk_item;
- phandle dvfs_clk_hdl;
- mali_dvfs_threshold_table *dvfs_tbl = NULL;
- uint32_t *clk_sample = NULL;
-
- struct property *prop;
- const __be32 *p;
- int length = 0, i = 0;
- u32 u;
-
- int ret = 0;
- if (!gpu_dn) {
- dev_notice(&pdev->dev, "gpu device node not right\n");
- return -ENODEV;
- }
-
- ret = of_property_read_u32(gpu_dn,"num_of_pp",
- &mpdata->cfg_pp);
- if (ret) {
- dev_notice(&pdev->dev, "set max pp to default 6\n");
- mpdata->cfg_pp = 6;
- }
- mpdata->scale_info.maxpp = mpdata->cfg_pp;
- mpdata->maxpp_sysfs = mpdata->cfg_pp;
- _dev_info(&pdev->dev, "max pp is %d\n", mpdata->scale_info.maxpp);
-
- ret = of_property_read_u32(gpu_dn,"min_pp",
- &mpdata->cfg_min_pp);
- if (ret) {
- dev_notice(&pdev->dev, "set min pp to default 1\n");
- mpdata->cfg_min_pp = 1;
- }
- mpdata->scale_info.minpp = mpdata->cfg_min_pp;
- _dev_info(&pdev->dev, "min pp is %d\n", mpdata->scale_info.minpp);
-
- ret = of_property_read_u32(gpu_dn,"min_clk",
- &mpdata->cfg_min_clock);
- if (ret) {
- dev_notice(&pdev->dev, "set min clk default to 0\n");
- mpdata->cfg_min_clock = 0;
- }
- mpdata->scale_info.minclk = mpdata->cfg_min_clock;
- _dev_info(&pdev->dev, "min clk is %d\n", mpdata->scale_info.minclk);
-
- mpdata->reg_base_hiubus = of_iomap(gpu_dn, 1);
- _dev_info(&pdev->dev, "hiu io source 0x%p\n", mpdata->reg_base_hiubus);
-
- mpdata->reg_base_aobus = of_iomap(gpu_dn, 2);
- _dev_info(&pdev->dev, "hiu io source 0x%p\n", mpdata->reg_base_aobus);
-
- ret = of_property_read_u32(gpu_dn,"sc_mpp",
- &mpdata->sc_mpp);
- if (ret) {
- dev_notice(&pdev->dev, "set pp used most of time default to %d\n", mpdata->cfg_pp);
- mpdata->sc_mpp = mpdata->cfg_pp;
- }
- _dev_info(&pdev->dev, "num of pp used most of time %d\n", mpdata->sc_mpp);
-
- of_get_property(gpu_dn, "tbl", &length);
-
- length = length /sizeof(u32);
- _dev_info(&pdev->dev, "clock dvfs cfg table size is %d\n", length);
-
- mpdata->dvfs_table = devm_kzalloc(&pdev->dev,
- sizeof(struct mali_dvfs_threshold_table)*length,
- GFP_KERNEL);
- dvfs_tbl = mpdata->dvfs_table;
- if (mpdata->dvfs_table == NULL) {
- dev_err(&pdev->dev, "failed to alloc dvfs table\n");
- return -ENOMEM;
- }
- mpdata->clk_sample = devm_kzalloc(&pdev->dev, sizeof(u32)*length, GFP_KERNEL);
- if (mpdata->clk_sample == NULL) {
- dev_err(&pdev->dev, "failed to alloc clk_sample table\n");
- return -ENOMEM;
- }
- clk_sample = mpdata->clk_sample;
-///////////
- mpdata->clk_items = devm_kzalloc(&pdev->dev, sizeof(struct mali_gpu_clk_item) * length, GFP_KERNEL);
- if (mpdata->clk_items == NULL) {
- dev_err(&pdev->dev, "failed to alloc clk_item table\n");
- return -ENOMEM;
- }
- clk_item = mpdata->clk_items;
-//
- of_property_for_each_u32(gpu_dn, "tbl", prop, p, u) {
- dvfs_clk_hdl = (phandle) u;
- gpu_clk_dn = of_find_node_by_phandle(dvfs_clk_hdl);
- ret = of_property_read_u32(gpu_clk_dn,"clk_freq", &dvfs_tbl->clk_freq);
- if (ret) {
- dev_notice(&pdev->dev, "read clk_freq failed\n");
- }
-#if 0
-#ifdef MESON_CPU_VERSION_OPS
- if (is_meson_gxbbm_cpu()) {
- if (dvfs_tbl->clk_freq >= GXBBM_MAX_GPU_FREQ)
- continue;
- }
-#endif
-#endif
- ret = of_property_read_string(gpu_clk_dn,"clk_parent",
- &dvfs_tbl->clk_parent);
- if (ret) {
- dev_notice(&pdev->dev, "read clk_parent failed\n");
- }
- dvfs_tbl->clkp_handle = devm_clk_get(&pdev->dev, dvfs_tbl->clk_parent);
- if (IS_ERR(dvfs_tbl->clkp_handle)) {
- dev_notice(&pdev->dev, "failed to get %s's clock pointer\n", dvfs_tbl->clk_parent);
- }
- ret = of_property_read_u32(gpu_clk_dn,"clkp_freq", &dvfs_tbl->clkp_freq);
- if (ret) {
- dev_notice(&pdev->dev, "read clk_parent freq failed\n");
- }
- ret = of_property_read_u32(gpu_clk_dn,"voltage", &dvfs_tbl->voltage);
- if (ret) {
- dev_notice(&pdev->dev, "read voltage failed\n");
- }
- ret = of_property_read_u32(gpu_clk_dn,"keep_count", &dvfs_tbl->keep_count);
- if (ret) {
- dev_notice(&pdev->dev, "read keep_count failed\n");
- }
- //downthreshold and upthreshold shall be u32
- ret = of_property_read_u32_array(gpu_clk_dn,"threshold",
- &dvfs_tbl->downthreshold, 2);
- if (ret) {
- dev_notice(&pdev->dev, "read threshold failed\n");
- }
- dvfs_tbl->freq_index = i;
- clk_item->clock = dvfs_tbl->clk_freq / 1000000;
- clk_item->vol = dvfs_tbl->voltage;
-
- *clk_sample = dvfs_tbl->clk_freq / 1000000;
-
- dvfs_tbl ++;
- clk_item ++;
- clk_sample ++;
- i++;
- mpdata->dvfs_table_size ++;
- }
-
- ret = of_property_read_u32(gpu_dn,"max_clk",
- &mpdata->cfg_clock);
- if (ret) {
- dev_notice(&pdev->dev, "max clk set %d\n", mpdata->dvfs_table_size-2);
- mpdata->cfg_clock = mpdata->dvfs_table_size-2;
- }
-
- mpdata->cfg_clock_bkup = mpdata->cfg_clock;
- mpdata->maxclk_sysfs = mpdata->cfg_clock;
- mpdata->scale_info.maxclk = mpdata->cfg_clock;
- _dev_info(&pdev->dev, "max clk is %d\n", mpdata->scale_info.maxclk);
-
- ret = of_property_read_u32(gpu_dn,"turbo_clk",
- &mpdata->turbo_clock);
- if (ret) {
- dev_notice(&pdev->dev, "turbo clk set to %d\n", mpdata->dvfs_table_size-1);
- mpdata->turbo_clock = mpdata->dvfs_table_size-1;
- }
- _dev_info(&pdev->dev, "turbo clk is %d\n", mpdata->turbo_clock);
-
- ret = of_property_read_u32(gpu_dn,"def_clk",
- &mpdata->def_clock);
- if (ret) {
- dev_notice(&pdev->dev, "default clk set to %d\n", mpdata->dvfs_table_size/2-1);
- mpdata->def_clock = mpdata->dvfs_table_size/2 - 1;
- }
- _dev_info(&pdev->dev, "default clk is %d\n", mpdata->def_clock);
-
- dvfs_tbl = mpdata->dvfs_table;
- clk_sample = mpdata->clk_sample;
- for (i = 0; i< mpdata->dvfs_table_size; i++) {
- _dev_info(&pdev->dev, "====================%d====================\n"
- "clk_freq=%10d, clk_parent=%9s, voltage=%d, keep_count=%d, threshod=<%d %d>, clk_sample=%d\n",
- i,
- dvfs_tbl->clk_freq, dvfs_tbl->clk_parent,
- dvfs_tbl->voltage, dvfs_tbl->keep_count,
- dvfs_tbl->downthreshold, dvfs_tbl->upthreshold, *clk_sample);
- dvfs_tbl ++;
- clk_sample ++;
- }
- _dev_info(&pdev->dev, "clock dvfs table size is %d\n", mpdata->dvfs_table_size);
-
- mpdata->clk_mali = devm_clk_get(&pdev->dev, "clk_mali");
- mpdata->clk_mali_0 = devm_clk_get(&pdev->dev, "clk_mali_0");
- mpdata->clk_mali_1 = devm_clk_get(&pdev->dev, "clk_mali_1");
- if (IS_ERR(mpdata->clk_mali) || IS_ERR(mpdata->clk_mali_0) || IS_ERR(mpdata->clk_mali_1)) {
- dev_err(&pdev->dev, "failed to get clock pointer\n");
- return -EFAULT;
- }
-
- pmali_plat = mpdata;
- mpdata->pdev = pdev;
- return 0;
-}
-#else
-int mali_clock_init_clk_tree(struct platform_device* pdev)
-{
- //mali_dvfs_threshold_table *dvfs_tbl = &pmali_plat->dvfs_table[pmali_plat->def_clock];
- struct clk *clk_mali = pmali_plat->clk_mali;
-
- clk_prepare_enable(clk_mali);
-
- return 0;
-}
-
-int mali_clock_init(mali_plat_info_t *pdev)
-{
- *pdev = *pdev;
- return 0;
-}
-
-int mali_clock_critical(critical_t critical, size_t param)
-{
- int ret = 0;
-
- ret = critical(param);
-
- return ret;
-}
-
-static int critical_clock_set(size_t param)
-{
- int ret = 0;
- unsigned int idx = param;
- mali_dvfs_threshold_table *dvfs_tbl = &pmali_plat->dvfs_table[idx];
-
- struct clk *clk_mali = pmali_plat->clk_mali;
- unsigned long time_use=0;
-
-
- GPU_CLK_DBG();
- do_gettimeofday(&start);
- ret = clk_set_rate(clk_mali, dvfs_tbl->clk_freq);
- do_gettimeofday(&end);
- GPU_CLK_DBG();
-
-#ifndef AML_CLK_LOCK_ERROR
- clk_disable_unprepare(clk_mali_x_old);
-#endif
- time_use = (end.tv_sec - start.tv_sec)*1000000 + end.tv_usec - start.tv_usec;
- GPU_CLK_DBG("step 1, mali_mux use: %ld us\n", time_use);
-
- return 0;
-}
-
-int mali_clock_set(unsigned int clock)
-{
- return mali_clock_critical(critical_clock_set, (size_t)clock);
-}
-
-void disable_clock(void)
-{
-#ifndef AML_CLK_LOCK_ERROR
- struct clk *clk_mali = pmali_plat->clk_mali;
-
- GPU_CLK_DBG();
- clk_disable_unprepare(clk_mali);
-#endif
- GPU_CLK_DBG();
-}
-
-void enable_clock(void)
-{
-#ifndef AML_CLK_LOCK_ERROR
- struct clk *clk_mali = pmali_plat->clk_mali;
-
- clk_prepare_enable(clk_mali);
-#endif
- GPU_CLK_DBG();
-}
-
-u32 get_mali_freq(u32 idx)
-{
- if (!mali_pm_statue) {
- return pmali_plat->clk_sample[idx];
- } else {
- return 0;
- }
-}
-
-void set_str_src(u32 data)
-{
- printk("gpu: %s, %s, %d\n", __FILE__, __func__, __LINE__);
-}
-
-int mali_dt_info(struct platform_device *pdev, struct mali_plat_info_t *mpdata)
-{
- struct device_node *gpu_dn = pdev->dev.of_node;
- struct device_node *gpu_clk_dn;
- struct mali_gpu_clk_item *clk_item;
- phandle dvfs_clk_hdl;
- mali_dvfs_threshold_table *dvfs_tbl = NULL;
- uint32_t *clk_sample = NULL;
-
- struct property *prop;
- const __be32 *p;
- int length = 0, i = 0;
- u32 u;
-
- int ret = 0;
- if (!gpu_dn) {
- dev_notice(&pdev->dev, "gpu device node not right\n");
- return -ENODEV;
- }
-
- ret = of_property_read_u32(gpu_dn,"num_of_pp",
- &mpdata->cfg_pp);
- if (ret) {
- dev_notice(&pdev->dev, "set max pp to default 6\n");
- mpdata->cfg_pp = 6;
- }
- mpdata->scale_info.maxpp = mpdata->cfg_pp;
- mpdata->maxpp_sysfs = mpdata->cfg_pp;
- _dev_info(&pdev->dev, "max pp is %d\n", mpdata->scale_info.maxpp);
-
- ret = of_property_read_u32(gpu_dn,"min_pp",
- &mpdata->cfg_min_pp);
- if (ret) {
- dev_notice(&pdev->dev, "set min pp to default 1\n");
- mpdata->cfg_min_pp = 1;
- }
- mpdata->scale_info.minpp = mpdata->cfg_min_pp;
- _dev_info(&pdev->dev, "min pp is %d\n", mpdata->scale_info.minpp);
-
- ret = of_property_read_u32(gpu_dn,"min_clk",
- &mpdata->cfg_min_clock);
- if (ret) {
- dev_notice(&pdev->dev, "set min clk default to 0\n");
- mpdata->cfg_min_clock = 0;
- }
- mpdata->scale_info.minclk = mpdata->cfg_min_clock;
- _dev_info(&pdev->dev, "min clk is %d\n", mpdata->scale_info.minclk);
-
- mpdata->reg_base_hiubus = of_iomap(gpu_dn, 1);
- _dev_info(&pdev->dev, "hiu io source 0x%p\n", mpdata->reg_base_hiubus);
-
- mpdata->reg_base_aobus = of_iomap(gpu_dn, 2);
- _dev_info(&pdev->dev, "hiu io source 0x%p\n", mpdata->reg_base_aobus);
-
- ret = of_property_read_u32(gpu_dn,"sc_mpp",
- &mpdata->sc_mpp);
- if (ret) {
- dev_notice(&pdev->dev, "set pp used most of time default to %d\n", mpdata->cfg_pp);
- mpdata->sc_mpp = mpdata->cfg_pp;
- }
- _dev_info(&pdev->dev, "num of pp used most of time %d\n", mpdata->sc_mpp);
-
- of_get_property(gpu_dn, "tbl", &length);
-
- length = length /sizeof(u32);
- _dev_info(&pdev->dev, "clock dvfs cfg table size is %d\n", length);
-
- mpdata->dvfs_table = devm_kzalloc(&pdev->dev,
- sizeof(struct mali_dvfs_threshold_table)*length,
- GFP_KERNEL);
- dvfs_tbl = mpdata->dvfs_table;
- if (mpdata->dvfs_table == NULL) {
- dev_err(&pdev->dev, "failed to alloc dvfs table\n");
- return -ENOMEM;
- }
- mpdata->clk_sample = devm_kzalloc(&pdev->dev, sizeof(u32)*length, GFP_KERNEL);
- if (mpdata->clk_sample == NULL) {
- dev_err(&pdev->dev, "failed to alloc clk_sample table\n");
- return -ENOMEM;
- }
- clk_sample = mpdata->clk_sample;
-///////////
- mpdata->clk_items = devm_kzalloc(&pdev->dev, sizeof(struct mali_gpu_clk_item) * length, GFP_KERNEL);
- if (mpdata->clk_items == NULL) {
- dev_err(&pdev->dev, "failed to alloc clk_item table\n");
- return -ENOMEM;
- }
- clk_item = mpdata->clk_items;
-//
- of_property_for_each_u32(gpu_dn, "tbl", prop, p, u) {
- dvfs_clk_hdl = (phandle) u;
- gpu_clk_dn = of_find_node_by_phandle(dvfs_clk_hdl);
- ret = of_property_read_u32(gpu_clk_dn,"clk_freq", &dvfs_tbl->clk_freq);
- if (ret) {
- dev_notice(&pdev->dev, "read clk_freq failed\n");
- }
-#if 0
-#ifdef MESON_CPU_VERSION_OPS
- if (is_meson_gxbbm_cpu()) {
- if (dvfs_tbl->clk_freq >= GXBBM_MAX_GPU_FREQ)
- continue;
- }
-#endif
-#endif
-#if 0
- ret = of_property_read_string(gpu_clk_dn,"clk_parent",
- &dvfs_tbl->clk_parent);
- if (ret) {
- dev_notice(&pdev->dev, "read clk_parent failed\n");
- }
- dvfs_tbl->clkp_handle = devm_clk_get(&pdev->dev, dvfs_tbl->clk_parent);
- if (IS_ERR(dvfs_tbl->clkp_handle)) {
- dev_notice(&pdev->dev, "failed to get %s's clock pointer\n", dvfs_tbl->clk_parent);
- }
- ret = of_property_read_u32(gpu_clk_dn,"clkp_freq", &dvfs_tbl->clkp_freq);
- if (ret) {
- dev_notice(&pdev->dev, "read clk_parent freq failed\n");
- }
-#endif
- ret = of_property_read_u32(gpu_clk_dn,"voltage", &dvfs_tbl->voltage);
- if (ret) {
- dev_notice(&pdev->dev, "read voltage failed\n");
- }
- ret = of_property_read_u32(gpu_clk_dn,"keep_count", &dvfs_tbl->keep_count);
- if (ret) {
- dev_notice(&pdev->dev, "read keep_count failed\n");
- }
- //downthreshold and upthreshold shall be u32
- ret = of_property_read_u32_array(gpu_clk_dn,"threshold",
- &dvfs_tbl->downthreshold, 2);
- if (ret) {
- dev_notice(&pdev->dev, "read threshold failed\n");
- }
- dvfs_tbl->freq_index = i;
- clk_item->clock = dvfs_tbl->clk_freq / 1000000;
- clk_item->vol = dvfs_tbl->voltage;
-
- *clk_sample = dvfs_tbl->clk_freq / 1000000;
-
- dvfs_tbl ++;
- clk_item ++;
- clk_sample ++;
- i++;
- mpdata->dvfs_table_size ++;
- }
-
- ret = of_property_read_u32(gpu_dn,"max_clk",
- &mpdata->cfg_clock);
- if (ret) {
- dev_notice(&pdev->dev, "max clk set %d\n", mpdata->dvfs_table_size-2);
- mpdata->cfg_clock = mpdata->dvfs_table_size-2;
- }
-
- mpdata->cfg_clock_bkup = mpdata->cfg_clock;
- mpdata->maxclk_sysfs = mpdata->cfg_clock;
- mpdata->scale_info.maxclk = mpdata->cfg_clock;
- _dev_info(&pdev->dev, "max clk is %d\n", mpdata->scale_info.maxclk);
-
- ret = of_property_read_u32(gpu_dn,"turbo_clk",
- &mpdata->turbo_clock);
- if (ret) {
- dev_notice(&pdev->dev, "turbo clk set to %d\n", mpdata->dvfs_table_size-1);
- mpdata->turbo_clock = mpdata->dvfs_table_size-1;
- }
- _dev_info(&pdev->dev, "turbo clk is %d\n", mpdata->turbo_clock);
-
- ret = of_property_read_u32(gpu_dn,"def_clk",
- &mpdata->def_clock);
- if (ret) {
- dev_notice(&pdev->dev, "default clk set to %d\n", mpdata->dvfs_table_size/2-1);
- mpdata->def_clock = mpdata->dvfs_table_size/2 - 1;
- }
- _dev_info(&pdev->dev, "default clk is %d\n", mpdata->def_clock);
-
- dvfs_tbl = mpdata->dvfs_table;
- clk_sample = mpdata->clk_sample;
- for (i = 0; i< mpdata->dvfs_table_size; i++) {
- _dev_info(&pdev->dev, "====================%d====================\n"
- "clk_freq=%10d, clk_parent=%9s, voltage=%d, keep_count=%d, threshod=<%d %d>, clk_sample=%d\n",
- i,
- dvfs_tbl->clk_freq, dvfs_tbl->clk_parent,
- dvfs_tbl->voltage, dvfs_tbl->keep_count,
- dvfs_tbl->downthreshold, dvfs_tbl->upthreshold, *clk_sample);
- dvfs_tbl ++;
- clk_sample ++;
- }
- _dev_info(&pdev->dev, "clock dvfs table size is %d\n", mpdata->dvfs_table_size);
-
- mpdata->clk_mali = devm_clk_get(&pdev->dev, "gpu_mux");
-#if 0
- mpdata->clk_mali_0 = devm_clk_get(&pdev->dev, "clk_mali_0");
- mpdata->clk_mali_1 = devm_clk_get(&pdev->dev, "clk_mali_1");
-#endif
- if (IS_ERR(mpdata->clk_mali)) {
- dev_err(&pdev->dev, "failed to get clock pointer\n");
- return -EFAULT;
- }
-
- pmali_plat = mpdata;
- mpdata->pdev = pdev;
- return 0;
-}
-
-#endif
+++ /dev/null
-#ifndef __MALI_CLOCK_H__
-#define __MALI_CLOCK_H__
-#include <linux/version.h>
-#include <linux/pm.h>
-#include <linux/io.h>
-#include <linux/types.h>
-#include <linux/of.h>
-
-#include <asm/io.h>
-#include <linux/clk.h>
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 29))
-#include <linux/amlogic/iomap.h>
-#endif
-
-#ifndef HHI_MALI_CLK_CNTL
-#define HHI_MALI_CLK_CNTL 0x6C
-#define mplt_read(r) readl((pmali_plat->reg_base_hiubus) + ((r)<<2))
-#define mplt_write(r, v) writel((v), ((pmali_plat->reg_base_hiubus) + ((r)<<2)))
-#define mplt_setbits(r, m) mplt_write((r), (mplt_read(r) | (m)));
-#define mplt_clrbits(r, m) mplt_write((r), (mplt_read(r) & (~(m))));
-#endif
-
-//extern int mali_clock_init(struct platform_device *dev);
-int mali_clock_init_clk_tree(struct platform_device *pdev);
-
-typedef int (*critical_t)(size_t param);
-int mali_clock_critical(critical_t critical, size_t param);
-
-int mali_clock_init(mali_plat_info_t*);
-int mali_clock_set(unsigned int index);
-void disable_clock(void);
-void enable_clock(void);
-u32 get_mali_freq(u32 idx);
-void set_str_src(u32 data);
-int mali_dt_info(struct platform_device *pdev,
- struct mali_plat_info_t *mpdata);
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2013 ARM Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
- *
- * A copy of the licence is included with the program, and can also be obtained from Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-/**
- * @file arm_core_scaling.c
- * Example core scaling policy.
- */
-
-#include <linux/version.h>
-#include <linux/module.h>
-#include <linux/workqueue.h>
-#include <linux/mali/mali_utgard.h>
-#include <mali_kernel_common.h>
-#include <mali_osk_profiling.h>
-#include <linux/time.h>
-
-//#include <linux/amlogic/amports/gp_pll.h>
-#include "meson_main2.h"
-
-
-static int currentStep;
-static int scaling_mode = MALI_PP_FS_SCALING;
-//static int scaling_mode = MALI_SCALING_DISABLE;
-//static int scaling_mode = MALI_PP_SCALING;
-
-//static struct gp_pll_user_handle_s *gp_pll_user_gpu;
-//static int is_gp_pll_get;
-//static int is_gp_pll_put;
-
-static unsigned scaling_dbg_level = 0;
-module_param(scaling_dbg_level, uint, 0644);
-MODULE_PARM_DESC(scaling_dbg_level , "scaling debug level");
-
-static mali_plat_info_t* pmali_plat = NULL;
-static struct workqueue_struct *mali_scaling_wq = NULL;
-//static DEFINE_SPINLOCK(lock);
-
-static int cur_gpu_clk_index = 0;
-static int exec_gpu_clk_index = 0;
-#define scalingdbg(level, fmt, arg...) \
- do { \
- if (scaling_dbg_level >= (level)) \
- printk(fmt , ## arg); \
- } while (0)
-
-struct mali_gpu_clock meson_gpu_clk_info = {
- .item = NULL,
- .num_of_steps = 0,
-};
-
-u32 revise_set_clk(u32 val, u32 flush)
-{
- u32 ret = 0;
- return ret;
-}
-
-void get_mali_rt_clkpp(u32* clk, u32* pp)
-{
-}
-
-u32 set_mali_rt_clkpp(u32 clk, u32 pp, u32 flush)
-{
- u32 ret = 0;
- return ret;
-}
-
-void revise_mali_rt(void)
-{
-}
-
-static void do_scaling(struct work_struct *work)
-{
- //unsigned long flags;
- mali_plat_info_t *pinfo = container_of(work, struct mali_plat_info_t, wq_work);
-
- *pinfo = *pinfo;
- //mali_dev_pause();
- //spin_lock_irqsave(&lock, flags);
- mali_clock_set(exec_gpu_clk_index);
- cur_gpu_clk_index = exec_gpu_clk_index;
- //spin_unlock_irqrestore(&lock, flags);
- //mali_dev_resume();
-}
-void flush_scaling_job(void)
-{
- if (mali_scaling_wq == NULL) return;
-
- flush_workqueue(mali_scaling_wq);
- printk("%s, %d\n", __func__, __LINE__);
-}
-
-
-int mali_core_scaling_init(mali_plat_info_t *mali_plat)
-{
- pmali_plat = mali_plat;
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)
- mali_scaling_wq = alloc_workqueue("gpu_scaling_wq", WQ_HIGHPRI | WQ_UNBOUND, 0);
-#else
- mali_scaling_wq = create_workqueue("gpu_scaling_wq");
-#endif
- INIT_WORK(&pmali_plat->wq_work, do_scaling);
- if (mali_scaling_wq == NULL) printk("Unable to create gpu scaling workqueue\n");
-
- meson_gpu_clk_info.num_of_steps = pmali_plat->scale_info.maxclk;
-
- return 0;
-}
-
-void mali_core_scaling_term(void)
-{
- flush_scaling_job();
- destroy_workqueue(mali_scaling_wq);
- mali_scaling_wq = NULL;
-}
-
-void mali_pp_scaling_update(struct mali_gpu_utilization_data *data)
-{
-}
-
-void mali_pp_fs_scaling_update(struct mali_gpu_utilization_data *data)
-{
-}
-
-u32 get_mali_schel_mode(void)
-{
- return scaling_mode;
-}
-
-void set_mali_schel_mode(u32 mode)
-{
- scaling_mode = mode;
- if (scaling_mode == MALI_TURBO_MODE) {
- printk ("turbo mode\n");
- pmali_plat->limit_on = 0;
- meson_gpu_clk_info.num_of_steps = pmali_plat->turbo_clock;
- } else {
- printk ("not turbo mode\n");
- pmali_plat->limit_on = 1;
- meson_gpu_clk_info.num_of_steps = pmali_plat->scale_info.maxclk;
- }
-
- printk("total_enable_steps = %d\n", meson_gpu_clk_info.num_of_steps);
-}
-
-u32 get_current_frequency(void)
-{
- return get_mali_freq(currentStep);
-}
-
-void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data)
-{
-}
-
-void mali_dev_restore(void)
-{
- //TO add this
- //mali_perf_set_num_pp_cores(num_cores_enabled);
- if (pmali_plat && pmali_plat->pdev) {
- mali_clock_init_clk_tree(pmali_plat->pdev);
- } else {
- printk("error: init clock failed, pmali_plat=%p, pmali_plat->pdev=%p\n",
- pmali_plat, pmali_plat == NULL ? NULL: pmali_plat->pdev);
- }
-}
-
-/* Function that platfrom report it's clock info which driver can set, needed when CONFIG_MALI_DVFS enabled */
-static void meson_platform_get_clock_info(struct mali_gpu_clock **data) {
- if (pmali_plat) {
- meson_gpu_clk_info.item = pmali_plat->clk_items;
- meson_gpu_clk_info.num_of_steps = pmali_plat->scale_info.maxclk;
- printk("get clock info\n");
- } else {
- printk("error pmali_plat is null");
- }
- *data = &meson_gpu_clk_info;
-}
-
-/* Function that get the current clock info, needed when CONFIG_MALI_DVFS enabled */
-static int meson_platform_get_freq(void) {
- scalingdbg(1, "cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
- //dynamically changed the num of steps;
- return cur_gpu_clk_index;
-}
-
-/* Fuction that platform callback for freq setting, needed when CONFIG_MALI_DVFS enabled */
-static int meson_platform_set_freq(int setting_clock_step) {
-
- if (exec_gpu_clk_index == setting_clock_step) {
- return 0;
- }
-
- queue_work(mali_scaling_wq, &pmali_plat->wq_work);
- exec_gpu_clk_index = setting_clock_step;
- scalingdbg(1, "set cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
- return 0;
-}
-
-int mali_meson_get_gpu_data(struct mali_gpu_device_data *mgpu_data)
-{
- mgpu_data->get_clock_info = meson_platform_get_clock_info,
- mgpu_data->get_freq = meson_platform_get_freq,
- mgpu_data->set_freq = meson_platform_set_freq,
- mgpu_data->utilization_callback = NULL;
- return 0;
-}
+++ /dev/null
-/*
- * mali_platform.h
- *
- * Created on: Nov 8, 2013
- * Author: amlogic
- */
-
-#include <linux/kernel.h>
-#ifndef MALI_PLATFORM_H_
-#define MALI_PLATFORM_H_
-
-extern u32 mali_gp_reset_fail;
-extern u32 mali_core_timeout;
-
-#endif /* MALI_PLATFORM_H_ */
+++ /dev/null
-../mali_scaling.h
\ No newline at end of file
+++ /dev/null
-/*
- * Copyright (C) 2010, 2012-2014 Amlogic Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
- *
- */
-
-/**
- * @file mali_platform.c
- * Platform specific Mali driver functions for:
- * meson8m2 and the newer chip
- */
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#ifdef CONFIG_PM_RUNTIME
-#include <linux/pm_runtime.h>
-#endif
-#include <asm/io.h>
-#include <linux/mali/mali_utgard.h>
-#include "mali_kernel_common.h"
-#include <linux/dma-mapping.h>
-#include <linux/moduleparam.h>
-
-#include "mali_executor.h"
-#include "mali_scaling.h"
-#include "mali_clock.h"
-#include "meson_main2.h"
-
-int mali_pm_statue = 0;
-extern void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data);
-
-u32 mali_gp_reset_fail = 0;
-module_param(mali_gp_reset_fail, int, S_IRUSR | S_IWUSR | S_IWGRP | S_IRGRP | S_IROTH); /* rw-rw-r-- */
-MODULE_PARM_DESC(mali_gp_reset_fail, "times of failed to reset GP");
-u32 mali_core_timeout = 0;
-module_param(mali_core_timeout, int, S_IRUSR | S_IWUSR | S_IWGRP | S_IRGRP | S_IROTH); /* rw-rw-r-- */
-MODULE_PARM_DESC(mali_core_timeout, "timeout of failed to reset GP");
-
-static struct mali_gpu_device_data mali_gpu_data = {
-
-#if defined(CONFIG_ARCH_REALVIEW)
- .dedicated_mem_start = 0x80000000, /* Physical start address (use 0xD0000000 for old indirect setup) */
- .dedicated_mem_size = 0x10000000, /* 256MB */
-#endif
-#if defined(CONFIG_ARM64)
- .fb_start = 0x5f000000,
- .fb_size = 0x91000000,
-#else
- .fb_start = 0xe0000000,
- .fb_size = 0x01000000,
-#endif
- .control_interval = 200, /* 1000ms */
-};
-
-int mali_platform_device_init(struct platform_device *device)
-{
- int err = -1;
-
- err = mali_meson_init_start(device);
- if (0 != err) printk("mali init failed\n");
- err = mali_meson_get_gpu_data(&mali_gpu_data);
- if (0 != err) printk("mali get gpu data failed\n");
-
- err = platform_device_add_data(device, &mali_gpu_data, sizeof(mali_gpu_data));
-
- if (0 == err) {
- device->dev.type = &mali_pm_device; /* We should probably use the pm_domain instead of type on newer kernels */
-#ifdef CONFIG_PM_RUNTIME
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
- pm_runtime_set_autosuspend_delay(&device->dev, 1000);
- pm_runtime_use_autosuspend(&device->dev);
-#endif
- pm_runtime_enable(&device->dev);
-#endif
- mali_meson_init_finish(device);
- }
-
- mali_gp_reset_fail = 0;
- mali_core_timeout = 0;
-
- return err;
-}
-
-int mali_platform_device_deinit(struct platform_device *device)
-{
- MALI_IGNORE(device);
-
- printk("%s, %d\n", __FILE__, __LINE__);
- MALI_DEBUG_PRINT(4, ("mali_platform_device_deinit() called\n"));
-
-
- mali_meson_uninit(device);
-
- return 0;
-}
-
-#if 0
-static int param_set_core_scaling(const char *val, const struct kernel_param *kp)
-{
- int ret = param_set_int(val, kp);
- printk("%s, %d\n", __FILE__, __LINE__);
-
- if (1 == mali_core_scaling_enable) {
- mali_core_scaling_sync(mali_executor_get_num_cores_enabled());
- }
- return ret;
-}
-
-static struct kernel_param_ops param_ops_core_scaling = {
- .set = param_set_core_scaling,
- .get = param_get_int,
-};
-
-module_param_cb(mali_core_scaling_enable, ¶m_ops_core_scaling, &mali_core_scaling_enable, 0644);
-MODULE_PARM_DESC(mali_core_scaling_enable, "1 means to enable core scaling policy, 0 means to disable core scaling policy");
-#endif
+++ /dev/null
-/*
- * mali_platform.h
- *
- * Created on: Nov 8, 2013
- * Author: amlogic
- */
-
-#ifndef MESON_MAIN_H_
-#define MESON_MAIN_H_
-#include <linux/version.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#ifdef CONFIG_PM_RUNTIME
-#include <linux/pm_runtime.h>
-#endif
-#include <linux/mali/mali_utgard.h>
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/cpu.h>
-#endif
-
-#include "mali_scaling.h"
-#include "mali_clock.h"
-
-extern struct device_type mali_pm_device;
-extern int mali_pm_statue;
-
-u32 set_max_mali_freq(u32 idx);
-u32 get_max_mali_freq(void);
-
-int mali_meson_init_start(struct platform_device* ptr_plt_dev);
-int mali_meson_get_gpu_data(struct mali_gpu_device_data *mgpu_data);
-int mali_meson_init_finish(struct platform_device* ptr_plt_dev);
-int mali_meson_uninit(struct platform_device* ptr_plt_dev);
-int mali_light_suspend(struct device *device);
-int mali_light_resume(struct device *device);
-int mali_deep_suspend(struct device *device);
-int mali_deep_resume(struct device *device);
-
-#endif /* MESON_MAIN_H_ */
+++ /dev/null
-/*******************************************************************
- *
- * Copyright C 2013 by Amlogic, Inc. All Rights Reserved.
- *
- * Description:
- *
- * Author: Amlogic Software
- * Created: 2010/4/1 19:46
- *
- *******************************************************************/
-/* Standard Linux headers */
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/string.h>
-#include <linux/slab.h>
-#include <linux/list.h>
-
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/io.h>
-#include <plat/io.h>
-#include <asm/io.h>
-#endif
-
-#include <linux/mali/mali_utgard.h>
-#include <common/mali_kernel_common.h>
-#include <common/mali_pmu.h>
-//#include "mali_pp_scheduler.h"
-#include "meson_main.h"
-
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
-static ssize_t domain_stat_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- unsigned int val;
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
-
- val = readl(pmali_plat->reg_base_aobus + 0xf0) & 0xff;
- return sprintf(buf, "%x\n", val>>4);
- return 0;
-}
-
-#define PREHEAT_CMD "preheat"
-#define PLL2_CMD "mpl2" /* mpl2 [11] or [0xxxxxxx] */
-#define SCMPP_CMD "scmpp" /* scmpp [number of pp your want in most of time]. */
-#define BSTGPU_CMD "bstgpu" /* bstgpu [0-256] */
-#define BSTPP_CMD "bstpp" /* bstpp [0-256] */
-#define LIMIT_CMD "lmt" /* lmt [0 or 1] */
-#define MAX_TOKEN 20
-#define FULL_UTILIZATION 256
-
-static ssize_t mpgpu_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- char *pstart, *cprt = NULL;
- u32 val = 0;
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
-
- cprt = skip_spaces(buf);
- pstart = strsep(&cprt," ");
- if (strlen(pstart) < 1)
- goto quit;
-
- if (!strncmp(pstart, PREHEAT_CMD, MAX_TOKEN)) {
- if (pmali_plat->plat_preheat) {
- pmali_plat->plat_preheat();
- }
- } else if (!strncmp(pstart, PLL2_CMD, MAX_TOKEN)) {
- int base = 10;
- if ((strlen(cprt) > 2) && (cprt[0] == '0') &&
- (cprt[1] == 'x' || cprt[1] == 'X'))
- base = 16;
- if (kstrtouint(cprt, base, &val) <0)
- goto quit;
- if (val < 11)
- pmali_plat->cfg_clock = pmali_plat->cfg_clock_bkup;
- else
- pmali_plat->cfg_clock = pmali_plat->turbo_clock;
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- set_str_src(val);
- } else if (!strncmp(pstart, SCMPP_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
- if ((val > 0) && (val < pmali_plat->cfg_pp)) {
- pmali_plat->sc_mpp = val;
- }
- } else if (!strncmp(pstart, BSTGPU_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
- if ((val > 0) && (val < FULL_UTILIZATION)) {
- pmali_plat->bst_gpu = val;
- }
- } else if (!strncmp(pstart, BSTPP_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
- if ((val > 0) && (val < FULL_UTILIZATION)) {
- pmali_plat->bst_pp = val;
- }
- } else if (!strncmp(pstart, LIMIT_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
-
- if (val < 2) {
- pmali_plat->limit_on = val;
- if (val == 0) {
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- pmali_plat->scale_info.maxpp = pmali_plat->cfg_pp;
- revise_mali_rt();
- }
- }
- }
-quit:
- return count;
-}
-
-static ssize_t scale_mode_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- return sprintf(buf, "%d\n", get_mali_schel_mode());
-}
-
-static ssize_t scale_mode_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
-
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- {
- return -EINVAL;
- }
-
- set_mali_schel_mode(val);
-
- return count;
-}
-
-static ssize_t max_pp_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- printk("maxpp:%d, maxpp_sysfs:%d, total=%d\n",
- pmali_plat->scale_info.maxpp, pmali_plat->maxpp_sysfs,
- pmali_plat->cfg_pp);
- return sprintf(buf, "%d\n", pmali_plat->cfg_pp);
-}
-
-static ssize_t max_pp_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pmali_plat->cfg_pp) || (val < pinfo->minpp))
- return -EINVAL;
-
- pmali_plat->maxpp_sysfs = val;
- pinfo->maxpp = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t min_pp_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- return sprintf(buf, "%d\n", pmali_plat->scale_info.minpp);
-}
-
-static ssize_t min_pp_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pinfo->maxpp) || (val < 1))
- return -EINVAL;
-
- pinfo->minpp = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t max_freq_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- printk("maxclk:%d, maxclk_sys:%d, max gpu level=%d\n",
- pmali_plat->scale_info.maxclk, pmali_plat->maxclk_sysfs, get_gpu_max_clk_level());
- return sprintf(buf, "%d\n", get_gpu_max_clk_level());
-}
-
-static ssize_t max_freq_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pmali_plat->cfg_clock) || (val < pinfo->minclk))
- return -EINVAL;
-
- pmali_plat->maxclk_sysfs = val;
- pinfo->maxclk = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t min_freq_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- return sprintf(buf, "%d\n", pmali_plat->scale_info.minclk);
-}
-
-static ssize_t min_freq_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pinfo->maxclk))
- return -EINVAL;
-
- pinfo->minclk = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t freq_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- return sprintf(buf, "%d\n", get_current_frequency());
-}
-
-static ssize_t freq_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- u32 clk, pp;
- get_mali_rt_clkpp(&clk, &pp);
-
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- return -EINVAL;
-
- set_mali_rt_clkpp(val, pp, 1);
-
- return count;
-}
-
-static ssize_t current_pp_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- u32 clk, pp;
- get_mali_rt_clkpp(&clk, &pp);
- return sprintf(buf, "%d\n", pp);
-}
-
-static ssize_t current_pp_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- u32 clk, pp;
-
- get_mali_rt_clkpp(&clk, &pp);
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- {
- return -EINVAL;
- }
-
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- return -EINVAL;
-
- set_mali_rt_clkpp(clk, val, 1);
-
- return count;
-}
-
-static struct class_attribute mali_class_attrs[] = {
- __ATTR(domain_stat, 0644, domain_stat_read, NULL),
- __ATTR(mpgpucmd, 0644, NULL, mpgpu_write),
- __ATTR(scale_mode, 0644, scale_mode_read, scale_mode_write),
- __ATTR(min_freq, 0644, min_freq_read, min_freq_write),
- __ATTR(max_freq, 0644, max_freq_read, max_freq_write),
- __ATTR(min_pp, 0644, min_pp_read, min_pp_write),
- __ATTR(max_pp, 0644, max_pp_read, max_pp_write),
- __ATTR(cur_freq, 0644, freq_read, freq_write),
- __ATTR(cur_pp, 0644, current_pp_read, current_pp_write),
-};
-
-static struct class mpgpu_class = {
- .name = "mpgpu",
-};
-#endif
-
-int mpgpu_class_init(void)
-{
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
- int ret = 0;
- int i;
- int attr_num = ARRAY_SIZE(mali_class_attrs);
-
- ret = class_register(&mpgpu_class);
- if (ret) {
- printk(KERN_ERR "%s: class_register failed\n", __func__);
- return ret;
- }
- for (i = 0; i< attr_num; i++) {
- ret = class_create_file(&mpgpu_class, &mali_class_attrs[i]);
- if (ret) {
- printk(KERN_ERR "%d ST: class item failed to register\n", i);
- }
- }
- return ret;
-#else
- return 0;
-#endif
-}
-
-void mpgpu_class_exit(void)
-{
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
- class_unregister(&mpgpu_class);
-#endif
-}
-
+++ /dev/null
-/*
- * platform.c
- *
- * clock source setting and resource config
- *
- * Created on: Dec 4, 2013
- * Author: amlogic
- */
-
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/module.h> /* kernel module definitions */
-#include <linux/ioport.h> /* request_mem_region */
-#include <linux/slab.h>
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#endif
-#include <asm/io.h>
-#include <linux/mali/mali_utgard.h>
-#ifdef CONFIG_GPU_THERMAL
-#include <linux/gpu_cooling.h>
-#include <linux/gpucore_cooling.h>
-#ifdef CONFIG_DEVFREQ_THERMAL
-#include <linux/amlogic/aml_thermal_hw.h>
-#include <common/mali_ukk.h>
-#endif
-#endif
-#include <common/mali_kernel_common.h>
-#include <common/mali_osk_profiling.h>
-#include <common/mali_pmu.h>
-
-#include "mali_scaling.h"
-#include "mali_clock.h"
-#include "meson_main.h"
-#include "mali_executor.h"
-
-/*
- * For Meson 8 M2.
- *
- */
-static void mali_plat_preheat(void);
-static mali_plat_info_t mali_plat_data = {
- .bst_gpu = 210, /* threshold for boosting gpu. */
- .bst_pp = 160, /* threshold for boosting PP. */
- .have_switch = 1,
- .limit_on = 1,
- .plat_preheat = mali_plat_preheat,
-};
-
-static void mali_plat_preheat(void)
-{
-#ifndef CONFIG_MALI_DVFS
- u32 pre_fs;
- u32 clk, pp;
-
- if (get_mali_schel_mode() != MALI_PP_FS_SCALING)
- return;
-
- get_mali_rt_clkpp(&clk, &pp);
- pre_fs = mali_plat_data.def_clock + 1;
- if (clk < pre_fs)
- clk = pre_fs;
- if (pp < mali_plat_data.sc_mpp)
- pp = mali_plat_data.sc_mpp;
- set_mali_rt_clkpp(clk, pp, 1);
-#endif
-}
-
-mali_plat_info_t* get_mali_plat_data(void) {
- return &mali_plat_data;
-}
-
-int get_mali_freq_level(int freq)
-{
- int i = 0, level = -1;
- int mali_freq_num;
-
- if (freq < 0)
- return level;
-
- mali_freq_num = mali_plat_data.dvfs_table_size - 1;
- if (freq < mali_plat_data.clk_sample[0])
- level = mali_freq_num-1;
- else if (freq >= mali_plat_data.clk_sample[mali_freq_num - 1])
- level = 0;
- else {
- for (i=0; i<mali_freq_num - 1 ;i++) {
- if (freq >= mali_plat_data.clk_sample[i] && freq < mali_plat_data.clk_sample[i + 1]) {
- level = i;
- level = mali_freq_num-level - 1;
- break;
- }
- }
- }
- return level;
-}
-
-unsigned int get_mali_max_level(void)
-{
- return mali_plat_data.dvfs_table_size - 1;
-}
-
-int get_gpu_max_clk_level(void)
-{
- return mali_plat_data.cfg_clock;
-}
-
-#ifdef CONFIG_GPU_THERMAL
-static void set_limit_mali_freq(u32 idx)
-{
- if (mali_plat_data.limit_on == 0)
- return;
- if (idx > mali_plat_data.turbo_clock || idx < mali_plat_data.scale_info.minclk)
- return;
- if (idx > mali_plat_data.maxclk_sysfs) {
- printk("idx > max freq\n");
- return;
- }
- mali_plat_data.scale_info.maxclk= idx;
- revise_mali_rt();
-}
-
-static u32 get_limit_mali_freq(void)
-{
- return mali_plat_data.scale_info.maxclk;
-}
-
-#ifdef CONFIG_DEVFREQ_THERMAL
-static u32 get_mali_utilization(void)
-{
- return (_mali_ukk_utilization_pp() * 100) / 256;
-}
-#endif
-#endif
-
-#ifdef CONFIG_GPU_THERMAL
-static u32 set_limit_pp_num(u32 num)
-{
- u32 ret = -1;
- if (mali_plat_data.limit_on == 0)
- goto quit;
- if (num > mali_plat_data.cfg_pp ||
- num < mali_plat_data.scale_info.minpp)
- goto quit;
-
- if (num > mali_plat_data.maxpp_sysfs) {
- printk("pp > sysfs set pp\n");
- goto quit;
- }
-
- mali_plat_data.scale_info.maxpp = num;
- revise_mali_rt();
- ret = 0;
-quit:
- return ret;
-}
-#ifdef CONFIG_DEVFREQ_THERMAL
-static u32 mali_get_online_pp(void)
-{
- unsigned int val;
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
-
- val = readl(pmali_plat->reg_base_aobus + 0xf0) & 0xff;
- if (val == 0x07) /* No pp is working */
- return 0;
-
- return mali_executor_get_num_cores_enabled();
-}
-#endif
-#endif
-
-void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data);
-int mali_meson_init_start(struct platform_device* ptr_plt_dev)
-{
- dev_set_drvdata(&ptr_plt_dev->dev, &mali_plat_data);
- mali_dt_info(ptr_plt_dev, &mali_plat_data);
- mali_clock_init_clk_tree(ptr_plt_dev);
- return 0;
-}
-
-int mali_meson_init_finish(struct platform_device* ptr_plt_dev)
-{
- if (mali_core_scaling_init(&mali_plat_data) < 0)
- return -1;
- return 0;
-}
-
-int mali_meson_uninit(struct platform_device* ptr_plt_dev)
-{
- mali_core_scaling_term();
- return 0;
-}
-
-static int mali_cri_light_suspend(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- mali_pm_statue = 1;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_suspend(device);
- }
- mali_pmu_power_down_all(pmu);
- return ret;
-}
-
-static int mali_cri_light_resume(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- mali_pmu_power_up_all(pmu);
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_resume(device);
- }
- mali_pm_statue = 0;
- return ret;
-}
-
-static int mali_cri_deep_suspend(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->suspend(device);
- }
- mali_pmu_power_down_all(pmu);
- return ret;
-}
-
-static int mali_cri_deep_resume(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- mali_pmu_power_up_all(pmu);
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->resume(device);
- }
- return ret;
-
-}
-
-int mali_light_suspend(struct device *device)
-{
- int ret = 0;
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- 0, 0, 0, 0, 0);
-#endif
-
- flush_scaling_job();
- /* clock scaling. Kasin..*/
- ret = mali_clock_critical(mali_cri_light_suspend, (size_t)device);
- disable_clock();
- return ret;
-}
-
-int mali_light_resume(struct device *device)
-{
- int ret = 0;
- enable_clock();
- ret = mali_clock_critical(mali_cri_light_resume, (size_t)device);
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- get_current_frequency(), 0, 0, 0, 0);
-#endif
- return ret;
-}
-
-int mali_deep_suspend(struct device *device)
-{
- int ret = 0;
-
- mali_pm_statue = 1;
- flush_scaling_job();
-
-
- /* clock scaling off. Kasin... */
- ret = mali_clock_critical(mali_cri_deep_suspend, (size_t)device);
- disable_clock();
- return ret;
-}
-
-int mali_deep_resume(struct device *device)
-{
- int ret = 0;
-
- /* clock scaling up. Kasin.. */
- enable_clock();
- ret = mali_clock_critical(mali_cri_deep_resume, (size_t)device);
- mali_pm_statue = 0;
- return ret;
-
-}
-
-void mali_post_init(void)
-{
-#ifdef CONFIG_GPU_THERMAL
- int err;
- struct gpufreq_cooling_device *gcdev = NULL;
- struct gpucore_cooling_device *gccdev = NULL;
-
- gcdev = gpufreq_cooling_alloc();
- register_gpu_freq_info(get_current_frequency);
- if (IS_ERR(gcdev))
- printk("malloc gpu cooling buffer error!!\n");
- else if (!gcdev)
- printk("system does not enable thermal driver\n");
- else {
- gcdev->get_gpu_freq_level = get_mali_freq_level;
- gcdev->get_gpu_max_level = get_mali_max_level;
- gcdev->set_gpu_freq_idx = set_limit_mali_freq;
- gcdev->get_gpu_current_max_level = get_limit_mali_freq;
-#ifdef CONFIG_DEVFREQ_THERMAL
- gcdev->get_gpu_freq = get_mali_freq;
- gcdev->get_gpu_loading = get_mali_utilization;
- gcdev->get_online_pp = mali_get_online_pp;
-#endif
- err = gpufreq_cooling_register(gcdev);
-#ifdef CONFIG_DEVFREQ_THERMAL
- aml_thermal_min_update(gcdev->cool_dev);
-#endif
- if (err < 0)
- printk("register GPU cooling error\n");
- printk("gpu cooling register okay with err=%d\n",err);
- }
-
- gccdev = gpucore_cooling_alloc();
- if (IS_ERR(gccdev))
- printk("malloc gpu core cooling buffer error!!\n");
- else if (!gccdev)
- printk("system does not enable thermal driver\n");
- else {
- gccdev->max_gpu_core_num=mali_plat_data.cfg_pp;
- gccdev->set_max_pp_num=set_limit_pp_num;
- err = (int)gpucore_cooling_register(gccdev);
-#ifdef CONFIG_DEVFREQ_THERMAL
- aml_thermal_min_update(gccdev->cool_dev);
-#endif
- if (err < 0)
- printk("register GPU cooling error\n");
- printk("gpu core cooling register okay with err=%d\n",err);
- }
-#endif
-}
+++ /dev/null
-/*
- * Copyright (C) 2013 ARM Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
- *
- * A copy of the licence is included with the program, and can also be obtained from Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-/**
- * @file arm_core_scaling.c
- * Example core scaling policy.
- */
-
-#include <linux/version.h>
-#include <linux/module.h>
-#include <linux/workqueue.h>
-#include <linux/mali/mali_utgard.h>
-#include <mali_kernel_common.h>
-#include <mali_osk_profiling.h>
-
-#if AMLOGIC_GPU_USE_GPPLL
-#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 16)
-#include <linux/amlogic/amports/gp_pll.h>
-#else
-#include <linux/amlogic/media/clk/gp_pll.h>
-#endif
-#endif
-#define LOG_MALI_SCALING 1
-#include "meson_main2.h"
-#include "mali_clock.h"
-
-static int currentStep;
-#ifndef CONFIG_MALI_DVFS
-static int num_cores_enabled;
-static int lastStep;
-static struct work_struct wq_work;
-static mali_plat_info_t* pmali_plat = NULL;
-#endif
-static int scaling_mode = MALI_PP_FS_SCALING;
-//static int scaling_mode = MALI_SCALING_DISABLE;
-//static int scaling_mode = MALI_PP_SCALING;
-
-#if AMLOGIC_GPU_USE_GPPLL
-static struct gp_pll_user_handle_s *gp_pll_user_gpu;
-static int is_gp_pll_get;
-static int is_gp_pll_put;
-#endif
-
-static unsigned scaling_dbg_level = 0;
-module_param(scaling_dbg_level, uint, 0644);
-MODULE_PARM_DESC(scaling_dbg_level , "scaling debug level");
-
-#define scalingdbg(level, fmt, arg...) \
- do { \
- if (scaling_dbg_level >= (level)) \
- printk(fmt , ## arg); \
- } while (0)
-
-#ifndef CONFIG_MALI_DVFS
-static inline void mali_clk_exected(void)
-{
- mali_dvfs_threshold_table * pdvfs = pmali_plat->dvfs_table;
- uint32_t execStep = currentStep;
-#if AMLOGIC_GPU_USE_GPPLL
- mali_dvfs_threshold_table *dvfs_tbl = &pmali_plat->dvfs_table[currentStep];
-#endif
-
- //if (pdvfs[currentStep].freq_index == pdvfs[lastStep].freq_index) return;
- if ((pdvfs[execStep].freq_index == pdvfs[lastStep].freq_index) ||
- (pdvfs[execStep].clk_freq == pdvfs[lastStep].clk_freq)){
- return;
- }
-
-#if AMLOGIC_GPU_USE_GPPLL
- if (0 == strcmp(dvfs_tbl->clk_parent, "gp0_pll")) {
- gp_pll_request(gp_pll_user_gpu);
- if (!is_gp_pll_get) {
- //printk("not get pll\n");
- execStep = currentStep - 1;
- }
- } else {
- //not get the gp pll, do need put
- is_gp_pll_get = 0;
- is_gp_pll_put = 0;
- gp_pll_release(gp_pll_user_gpu);
- }
-#endif
-
- //mali_dev_pause();
- mali_clock_set(pdvfs[execStep].freq_index);
- //mali_dev_resume();
- lastStep = execStep;
-#if AMLOGIC_GPU_USE_GPPLL
- if (is_gp_pll_put) {
- //printk("release gp0 pll\n");
- gp_pll_release(gp_pll_user_gpu);
- gp_pll_request(gp_pll_user_gpu);
- is_gp_pll_get = 0;
- is_gp_pll_put = 0;
- }
-#endif
-
-}
-#if AMLOGIC_GPU_USE_GPPLL
-static int gp_pll_user_cb_gpu(struct gp_pll_user_handle_s *user,
- int event)
-{
- if (event == GP_PLL_USER_EVENT_GRANT) {
- //printk("granted\n");
- is_gp_pll_get = 1;
- is_gp_pll_put = 0;
- schedule_work(&wq_work);
- } else if (event == GP_PLL_USER_EVENT_YIELD) {
- //printk("ask for yield\n");
- is_gp_pll_get = 0;
- is_gp_pll_put = 1;
- schedule_work(&wq_work);
- }
-
- return 0;
-}
-#endif
-
-static void do_scaling(struct work_struct *work)
-{
- mali_dvfs_threshold_table * pdvfs = pmali_plat->dvfs_table;
- int err = mali_perf_set_num_pp_cores(num_cores_enabled);
- scalingdbg(1, "set pp cores to %d\n", num_cores_enabled);
- MALI_DEBUG_ASSERT(0 == err);
- MALI_IGNORE(err);
- scalingdbg(1, "pdvfs[%d].freq_index=%d, pdvfs[%d].freq_index=%d\n",
- currentStep, pdvfs[currentStep].freq_index,
- lastStep, pdvfs[lastStep].freq_index);
- mali_clk_exected();
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- get_current_frequency(),
- 0, 0, 0, 0);
-#endif
-}
-#endif
-
-u32 revise_set_clk(u32 val, u32 flush)
-{
- u32 ret = 0;
-#ifndef CONFIG_MALI_DVFS
- mali_scale_info_t* pinfo;
-
- pinfo = &pmali_plat->scale_info;
-
- if (val < pinfo->minclk)
- val = pinfo->minclk;
- else if (val > pinfo->maxclk)
- val = pinfo->maxclk;
-
- if (val != currentStep) {
- currentStep = val;
- if (flush)
- schedule_work(&wq_work);
- else
- ret = 1;
- }
-#endif
- return ret;
-}
-
-void get_mali_rt_clkpp(u32* clk, u32* pp)
-{
-#ifndef CONFIG_MALI_DVFS
- *clk = currentStep;
- *pp = num_cores_enabled;
-#endif
-}
-
-u32 set_mali_rt_clkpp(u32 clk, u32 pp, u32 flush)
-{
- u32 ret = 0;
-#ifndef CONFIG_MALI_DVFS
- mali_scale_info_t* pinfo;
- u32 flush_work = 0;
-
- pinfo = &pmali_plat->scale_info;
- if (clk < pinfo->minclk)
- clk = pinfo->minclk;
- else if (clk > pinfo->maxclk)
- clk = pinfo->maxclk;
-
- if (clk != currentStep) {
- currentStep = clk;
- if (flush)
- flush_work++;
- else
- ret = 1;
- }
- if (pp < pinfo->minpp)
- pp = pinfo->minpp;
- else if (pp > pinfo->maxpp)
- pp = pinfo->maxpp;
-
- if (pp != num_cores_enabled) {
- num_cores_enabled = pp;
- if (flush)
- flush_work++;
- else
- ret = 1;
- }
-
- if (flush_work)
- schedule_work(&wq_work);
-#endif
- return ret;
-}
-
-void revise_mali_rt(void)
-{
-#ifndef CONFIG_MALI_DVFS
- set_mali_rt_clkpp(currentStep, num_cores_enabled, 1);
-#endif
-}
-
-void flush_scaling_job(void)
-{
-#ifndef CONFIG_MALI_DVFS
- cancel_work_sync(&wq_work);
-#endif
-}
-
-#ifndef CONFIG_MALI_DVFS
-static u32 enable_one_core(void)
-{
- scalingdbg(2, "meson: one more pp, curent has %d pp cores\n", num_cores_enabled + 1);
- return set_mali_rt_clkpp(currentStep, num_cores_enabled + 1, 0);
-}
-
-static u32 disable_one_core(void)
-{
- scalingdbg(2, "meson: disable one pp, current has %d pp cores\n", num_cores_enabled - 1);
- return set_mali_rt_clkpp(currentStep, num_cores_enabled - 1, 0);
-}
-
-static u32 enable_max_num_cores(void)
-{
- return set_mali_rt_clkpp(currentStep, pmali_plat->scale_info.maxpp, 0);
-}
-
-static u32 enable_pp_cores(u32 val)
-{
- scalingdbg(2, "meson: enable %d pp cores\n", val);
- return set_mali_rt_clkpp(currentStep, val, 0);
-}
-#endif
-
-int mali_core_scaling_init(mali_plat_info_t *mali_plat)
-{
-#ifndef CONFIG_MALI_DVFS
- if (mali_plat == NULL) {
- scalingdbg(2, " Mali platform data is NULL!!!\n");
- return -1;
- }
-
- pmali_plat = mali_plat;
- num_cores_enabled = pmali_plat->sc_mpp;
-#if AMLOGIC_GPU_USE_GPPLL
- gp_pll_user_gpu = gp_pll_user_register("gpu", 1,
- gp_pll_user_cb_gpu);
- //not get the gp pll, do need put
- is_gp_pll_get = 0;
- is_gp_pll_put = 0;
- if (gp_pll_user_gpu == NULL) printk("register gp pll user for gpu failed\n");
-#endif
-
- currentStep = pmali_plat->def_clock;
- lastStep = currentStep;
- INIT_WORK(&wq_work, do_scaling);
-#endif
- return 0;
- /* NOTE: Mali is not fully initialized at this point. */
-}
-
-void mali_core_scaling_term(void)
-{
-#ifndef CONFIG_MALI_DVFS
- flush_scheduled_work();
-#if AMLOGIC_GPU_USE_GPPLL
- gp_pll_user_unregister(gp_pll_user_gpu);
-#endif
-#endif
-}
-
-#ifndef CONFIG_MALI_DVFS
-static u32 mali_threshold [] = {
- 102, /* 40% */
- 128, /* 50% */
- 230, /* 90% */
-};
-#endif
-
-void mali_pp_scaling_update(struct mali_gpu_utilization_data *data)
-{
-#ifndef CONFIG_MALI_DVFS
- int ret = 0;
-
- if (mali_threshold[2] < data->utilization_pp)
- ret = enable_max_num_cores();
- else if (mali_threshold[1]< data->utilization_pp)
- ret = enable_one_core();
- else if (0 < data->utilization_pp)
- ret = disable_one_core();
- if (ret == 1)
- schedule_work(&wq_work);
-#endif
-}
-
-#if LOG_MALI_SCALING
-void trace_utilization(struct mali_gpu_utilization_data *data, u32 current_idx, u32 next,
- u32 current_pp, u32 next_pp)
-{
- char direction;
- if (next > current_idx)
- direction = '>';
- else if ((current_idx > pmali_plat->scale_info.minpp) && (next < current_idx))
- direction = '<';
- else
- direction = '~';
-
- scalingdbg(2, "[SCALING]%c (%3d-->%3d)@%3d{%3d - %3d}. pp:(%d-->%d)\n",
- direction,
- get_mali_freq(current_idx),
- get_mali_freq(next),
- data->utilization_gpu,
- pmali_plat->dvfs_table[current_idx].downthreshold,
- pmali_plat->dvfs_table[current_idx].upthreshold,
- current_pp, next_pp);
-}
-#endif
-
-#ifndef CONFIG_MALI_DVFS
-static int mali_stay_count = 0;
-static void mali_decide_next_status(struct mali_gpu_utilization_data *data, int* next_fs_idx,
- int* pp_change_flag)
-{
- u32 utilization, mali_up_limit, decided_fs_idx;
- u32 ld_left, ld_right;
- u32 ld_up, ld_down;
- u32 change_mode;
-
- *pp_change_flag = 0;
- change_mode = 0;
- utilization = data->utilization_gpu;
-
- scalingdbg(5, "line(%d), scaling_mode=%d, MALI_TURBO_MODE=%d, turbo=%d, maxclk=%d\n",
- __LINE__, scaling_mode, MALI_TURBO_MODE,
- pmali_plat->turbo_clock, pmali_plat->scale_info.maxclk);
-
- mali_up_limit = (scaling_mode == MALI_TURBO_MODE) ?
- pmali_plat->turbo_clock : pmali_plat->scale_info.maxclk;
- decided_fs_idx = currentStep;
-
- ld_up = pmali_plat->dvfs_table[currentStep].upthreshold;
- ld_down = pmali_plat->dvfs_table[currentStep].downthreshold;
-
- scalingdbg(2, "utilization=%d, ld_up=%d\n ", utilization, ld_up);
- if (utilization >= ld_up) { /* go up */
-
- scalingdbg(2, "currentStep=%d, mali_up_limit=%d\n ", currentStep, mali_up_limit);
- if (currentStep < mali_up_limit) {
- change_mode = 1;
- if ((currentStep < pmali_plat->def_clock) && (utilization > pmali_plat->bst_gpu))
- decided_fs_idx = pmali_plat->def_clock;
- else
- decided_fs_idx++;
- }
- if ((data->utilization_pp >= ld_up) &&
- (num_cores_enabled < pmali_plat->scale_info.maxpp)) {
- if ((num_cores_enabled < pmali_plat->sc_mpp) && (data->utilization_pp >= pmali_plat->bst_pp)) {
- *pp_change_flag = 1;
- change_mode = 1;
- } else if (change_mode == 0) {
- *pp_change_flag = 2;
- change_mode = 1;
- }
- }
-#if LOG_MALI_SCALING
- scalingdbg(2, "[nexting..] [LD:%d]-> FS[CRNT:%d LMT:%d NEXT:%d] PP[NUM:%d LMT:%d MD:%d][F:%d]\n",
- data->utilization_pp, currentStep, mali_up_limit, decided_fs_idx,
- num_cores_enabled, pmali_plat->scale_info.maxpp, *pp_change_flag, change_mode);
-#endif
- } else if (utilization <= ld_down) { /* go down */
- if (mali_stay_count > 0) {
- *next_fs_idx = decided_fs_idx;
- mali_stay_count--;
- return;
- }
-
- if (num_cores_enabled > pmali_plat->sc_mpp) {
- change_mode = 1;
- if (data->utilization_pp <= ld_down) {
- ld_left = data->utilization_pp * num_cores_enabled;
- ld_right = (pmali_plat->dvfs_table[currentStep].upthreshold) *
- (num_cores_enabled - 1);
- if (ld_left < ld_right) {
- change_mode = 2;
- }
- }
- } else if (currentStep > pmali_plat->scale_info.minclk) {
- change_mode = 1;
- } else if (num_cores_enabled > 1) { /* decrease PPS */
- if (data->utilization_pp <= ld_down) {
- ld_left = data->utilization_pp * num_cores_enabled;
- ld_right = (pmali_plat->dvfs_table[currentStep].upthreshold) *
- (num_cores_enabled - 1);
- scalingdbg(2, "ld_left=%d, ld_right=%d\n", ld_left, ld_right);
- if (ld_left < ld_right) {
- change_mode = 2;
- }
- }
- }
-
- if (change_mode == 1) {
- decided_fs_idx--;
- } else if (change_mode == 2) { /* decrease PPS */
- *pp_change_flag = -1;
- }
- }
-
- if (decided_fs_idx < 0 ) {
- printk("gpu debug, next index below 0\n");
- decided_fs_idx = 0;
- }
- if (decided_fs_idx > pmali_plat->scale_info.maxclk) {
- decided_fs_idx = pmali_plat->scale_info.maxclk;
- printk("gpu debug, next index above max, set to %d\n", decided_fs_idx);
- }
-
- if (change_mode)
- mali_stay_count = pmali_plat->dvfs_table[decided_fs_idx].keep_count;
- *next_fs_idx = decided_fs_idx;
-}
-#endif
-
-void mali_pp_fs_scaling_update(struct mali_gpu_utilization_data *data)
-{
-#ifndef CONFIG_MALI_DVFS
- int ret = 0;
- int pp_change_flag = 0;
- u32 next_idx = 0;
-
-#if LOG_MALI_SCALING
- u32 last_pp = num_cores_enabled;
-#endif
- mali_decide_next_status(data, &next_idx, &pp_change_flag);
-
- if (pp_change_flag == 1)
- ret = enable_pp_cores(pmali_plat->sc_mpp);
- else if (pp_change_flag == 2)
- ret = enable_one_core();
- else if (pp_change_flag == -1) {
- ret = disable_one_core();
- }
-
-#if LOG_MALI_SCALING
- if (pp_change_flag || (next_idx != currentStep))
- trace_utilization(data, currentStep, next_idx, last_pp, num_cores_enabled);
-#endif
-
- if (next_idx != currentStep) {
- ret = 1;
- currentStep = next_idx;
- }
-
- if (ret == 1)
- schedule_work(&wq_work);
-#ifdef CONFIG_MALI400_PROFILING
- else
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- get_current_frequency(),
- 0, 0, 0, 0);
-#endif
-#endif
-}
-
-u32 get_mali_schel_mode(void)
-{
- return scaling_mode;
-}
-
-void set_mali_schel_mode(u32 mode)
-{
-#ifndef CONFIG_MALI_DVFS
- MALI_DEBUG_ASSERT(mode < MALI_SCALING_MODE_MAX);
- if (mode >= MALI_SCALING_MODE_MAX)
- return;
- scaling_mode = mode;
-
- //disable thermal in turbo mode
- if (scaling_mode == MALI_TURBO_MODE) {
- pmali_plat->limit_on = 0;
- } else {
- pmali_plat->limit_on = 1;
- }
- /* set default performance range. */
- pmali_plat->scale_info.minclk = pmali_plat->cfg_min_clock;
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- pmali_plat->scale_info.minpp = pmali_plat->cfg_min_pp;
- pmali_plat->scale_info.maxpp = pmali_plat->cfg_pp;
-
- /* set current status and tune max freq */
- if (scaling_mode == MALI_PP_FS_SCALING) {
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- enable_pp_cores(pmali_plat->sc_mpp);
- } else if (scaling_mode == MALI_SCALING_DISABLE) {
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- enable_max_num_cores();
- } else if (scaling_mode == MALI_TURBO_MODE) {
- pmali_plat->scale_info.maxclk = pmali_plat->turbo_clock;
- enable_max_num_cores();
- }
- currentStep = pmali_plat->scale_info.maxclk;
- schedule_work(&wq_work);
-#endif
-}
-
-u32 get_current_frequency(void)
-{
- return get_mali_freq(currentStep);
-}
-
-void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data)
-{
-#ifndef CONFIG_MALI_DVFS
- if (mali_pm_statue)
- return;
-
- switch (scaling_mode) {
- case MALI_PP_FS_SCALING:
- mali_pp_fs_scaling_update(data);
- break;
- case MALI_PP_SCALING:
- mali_pp_scaling_update(data);
- break;
- default:
- break;
- }
-#endif
-}
-static u32 clk_cntl_save = 0;
-void mali_dev_freeze(void)
-{
- clk_cntl_save = mplt_read(HHI_MALI_CLK_CNTL);
-}
-
-void mali_dev_restore(void)
-{
-
- mplt_write(HHI_MALI_CLK_CNTL, clk_cntl_save);
- if (pmali_plat && pmali_plat->pdev) {
- mali_clock_init_clk_tree(pmali_plat->pdev);
- } else {
- printk("error: init clock failed, pmali_plat=%p, pmali_plat->pdev=%p\n",
- pmali_plat, pmali_plat == NULL ? NULL: pmali_plat->pdev);
- }
-}
-
-int mali_meson_get_gpu_data(struct mali_gpu_device_data *mgpu_data)
-{
- mgpu_data->get_clock_info = NULL;
- mgpu_data->get_freq = NULL;
- mgpu_data->set_freq = NULL;
- mgpu_data->utilization_callback = mali_gpu_utilization_callback;
- return 0;
-}
+++ /dev/null
-/*
- * AMLOGIC Mali fix driver.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the named License,
- * or any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
- *
- * Author: Tim Yao <timyao@amlogic.com>
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/timer.h>
-#include <asm/io.h>
-#include <linux/ioport.h>
-#include <linux/dma-mapping.h>
-
-#include <linux/module.h>
-
-#include <mach/am_regs.h>
-#include <mach/clock.h>
-#include <linux/io.h>
-#include <mach/io.h>
-#include <plat/io.h>
-#include <asm/io.h>
-
-#include "mali_kernel_common.h"
-#include "mali_osk.h"
-#include "mali_platform.h"
-#include "mali_fix.h"
-
-#define MALI_MM1_REG_ADDR 0xd0064000
-#define MALI_MMU_REGISTER_INT_STATUS 0x0008
-#define MALI_MM2_REG_ADDR 0xd0065000
-#define MALI_MMU_REGISTER_INT_STATUS 0x0008
-#define MALI_MM_REG_SIZE 0x1000
-
-#define READ_MALI_MMU1_REG(r) (ioread32(((u8*)mali_mm1_regs) + r))
-#define READ_MALI_MMU2_REG(r) (ioread32(((u8*)mali_mm2_regs) + r))
-
-extern int mali_PP0_int_cnt(void);
-extern int mali_PP1_int_cnt(void);
-
-#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
-static ulong * mali_mm1_regs = NULL;
-static ulong * mali_mm2_regs = NULL;
-static struct timer_list timer;
-
-static u32 mali_pp1_int_count = 0;
-static u32 mali_pp2_int_count = 0;
-static u32 mali_pp1_mmu_int_count = 0;
-static u32 mali_pp2_mmu_int_count = 0;
-static u32 mali_mmu_int_process_state[2];
-
-static void timer_callback(ulong data)
-{
- unsigned long mali_flags;
-
- mali_pp1_int_count = mali_PP0_int_cnt();
- mali_pp2_int_count = mali_PP1_int_cnt();
-
- /* lock mali_clock_gating when access Mali registers */
- mali_flags = mali_clock_gating_lock();
-
- if (readl((u32 *)P_HHI_MALI_CLK_CNTL) & 0x100) {
- /* polling for PP1 MMU interrupt */
- if (mali_mmu_int_process_state[0] == MMU_INT_NONE) {
- if (READ_MALI_MMU1_REG(MALI_MMU_REGISTER_INT_STATUS) != 0) {
- mali_pp1_mmu_int_count++;
- MALI_DEBUG_PRINT(3, ("Mali MMU: core0 page fault emit \n"));
- mali_mmu_int_process_state[0] = MMU_INT_HIT;
- __raw_writel(1, (volatile void *)P_ISA_TIMERC);
- }
- }
-
- /* polling for PP2 MMU interrupt */
- if (mali_mmu_int_process_state[1] == MMU_INT_NONE) {
- if (READ_MALI_MMU2_REG(MALI_MMU_REGISTER_INT_STATUS) != 0) {
- mali_pp2_mmu_int_count++;
- MALI_DEBUG_PRINT(3, ("Mali MMU: core1 page fault emit \n"));
- mali_mmu_int_process_state[1] = MMU_INT_HIT;
- __raw_writel(1, (volatile void *)P_ISA_TIMERC);
- }
- }
- }
-
- mali_clock_gating_unlock(mali_flags);
-
- timer.expires = jiffies + HZ/100;
-
- add_timer(&timer);
-}
-
-void malifix_set_mmu_int_process_state(int index, int state)
-{
- if (index < 2)
- mali_mmu_int_process_state[index] = state;
-}
-
-int malifix_get_mmu_int_process_state(int index)
-{
- if (index < 2)
- return mali_mmu_int_process_state[index];
- return 0;
-}
-#endif
-
-void malifix_init(void)
-{
-#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
- if (!mali_meson_is_revb())
- return;
-
- if ((mali_mm1_regs) && (mali_mm2_regs)) return;
- mali_mmu_int_process_state[0] = 0;
- mali_mmu_int_process_state[1] = 0;
-
- /* set up Timer C as a 1uS one-shot timer */
- aml_clr_reg32_mask(P_ISA_TIMER_MUX, (1<<18)|(1<<14)|(3<<4));
- aml_set_reg32_mask(P_ISA_TIMER_MUX, (1<<18)|(0<<14)|(0<<4));
-
- setup_timer(&timer, timer_callback, 0);
-
- mali_mm1_regs = (ulong *)ioremap_nocache(MALI_MM1_REG_ADDR, MALI_MM_REG_SIZE);
- if (mali_mm1_regs)
- printk("Mali pp1 MMU register mapped at %p...\n", mali_mm1_regs);
-
- mali_mm2_regs = (ulong *)ioremap_nocache(MALI_MM2_REG_ADDR, MALI_MM_REG_SIZE);
- if (mali_mm2_regs)
- printk("Mali pp2 MMU register mapped at %p...\n", mali_mm2_regs);
-
- if ((mali_mm1_regs != NULL) && (mali_mm2_regs != NULL))
- mod_timer(&timer, jiffies + HZ/100);
-#endif
-}
-
-void malifix_exit(void)
-{
-#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
- if (!mali_meson_is_revb())
- return;
-
- del_timer(&timer);
-
- if (mali_mm1_regs != NULL)
- iounmap(mali_mm1_regs);
- mali_mm1_regs = NULL;
-
- if (mali_mm2_regs != NULL)
- iounmap(mali_mm2_regs);
- mali_mm2_regs = NULL;
-
-#endif
- return;
-}
-
-#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
-module_param(mali_pp1_int_count, uint, 0664);
-MODULE_PARM_DESC(mali_pp1_int_count, "Mali PP1 interrupt count\n");
-
-module_param(mali_pp2_int_count, uint, 0664);
-MODULE_PARM_DESC(mali_pp2_int_count, "Mali PP1 interrupt count\n");
-
-module_param(mali_pp1_mmu_int_count, uint, 0664);
-MODULE_PARM_DESC(mali_pp1_mmu_int_count, "Mali PP1 mmu interrupt count\n");
-
-module_param(mali_pp2_mmu_int_count, uint, 0664);
-MODULE_PARM_DESC(mali_pp2_mmu_int_count, "Mali PP2 mmu interrupt count\n");
-#endif
-
-MODULE_DESCRIPTION("AMLOGIC mali fix driver");
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Tim Yao <timyao@amlogic.com>");
+++ /dev/null
-#ifndef MALI_FIX_H
-#define MALI_FIX_H
-
-#define MMU_INT_NONE 0
-#define MMU_INT_HIT 1
-#define MMU_INT_TOP 2
-#define MMU_INT_BOT 3
-
-extern void malifix_init(void);
-extern void malifix_exit(void);
-extern void malifix_set_mmu_int_process_state(int, int);
-extern int malifix_get_mmu_int_process_state(int);
-extern int mali_meson_is_revb(void);
-#endif /* MALI_FIX_H */
+++ /dev/null
-/*
- * This confidential and proprietary software may be used only as
- * authorised by a licensing agreement from AMLOGIC, INC.
- * (C) COPYRIGHT 2011 AMLOGIC, INC.
- * ALL RIGHTS RESERVED
- * The entire notice above must be reproduced on all authorised
- * copies and copies may only be made to the extent permitted
- * by a licensing agreement from AMLOGIC, INC.
- */
-
-/**
- * @file mali_platform.c
- * Platform specific Mali driver functions for meson platform
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/dma-mapping.h>
-#include <linux/spinlock.h>
-#include <linux/spinlock_types.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <mach/am_regs.h>
-#include <mach/clock.h>
-
-#include "mali_kernel_common.h"
-#include "mali_osk.h"
-#include "mali_platform.h"
-#include "mali_poweron_reg.h"
-#include "mali_fix.h"
-#include "mali_platform.h"
-
-static int last_power_mode = -1;
-static int mali_init_flag = 0;
-static const u32 poweron_data[] =
-{
-/* commands */
-/* 000 */ 0x00000040, 0x20400000, 0x00000300, 0x30040000,
-/* 010 */ 0x00000400, 0x400a0000, 0x0f000033, 0x10000042,
-/* 020 */ 0x00300c00, 0x10000040, 0x4c000001, 0x00000000,
-/* 030 */ 0x00000000, 0x60000000, 0x00000000, 0x00000000,
-/* 040 */ 0x00004000, 0x00002000, 0x00000210, 0x0000203f,
-/* 050 */ 0x00000220, 0x0000203f, 0x00000230, 0x0000203f,
-/* 060 */ 0x00000240, 0x0000203f, 0x00000250, 0x0000203f,
-/* 070 */ 0x00000260, 0x0000203f, 0x00000270, 0x0000203f,
-/* 080 */ 0x00000280, 0x0000203f, 0x00000290, 0x0000203f,
-/* 090 */ 0x000002a0, 0x0000203f, 0x000002b0, 0x0000203f,
-/* 0a0 */ 0x000002c0, 0x0000203f, 0x000002d0, 0x0000203f,
-/* 0b0 */ 0x000002e0, 0x0000203f, 0x000002f0, 0x0000203f,
-/* 0c0 */ 0x00002000, 0x00002000, 0x00002010, 0x0000203f,
-/* 0d0 */ 0x00002020, 0x0000203f, 0x00002030, 0x0000203f,
-/* 0e0 */ 0x00002040, 0x0000203f, 0x00002050, 0x0000203f,
-/* 0f0 */ 0x00002060, 0x0000203f, 0x00002070, 0x0000203f,
-/* 100 */ 0x00002080, 0x0000203f, 0x00002090, 0x0000203f,
-/* 110 */ 0x000020a0, 0x0000203f, 0x000020b0, 0x0000203f,
-/* 120 */ 0x000020c0, 0x0000203f, 0x000020d0, 0x0000203f,
-/* 130 */ 0x000020e0, 0x0000203f, 0x000020f0, 0x0000203f,
-/* 140 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 150 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 160 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 170 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 180 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 190 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 1a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 1b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 1c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 1d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 1e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 1f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 200 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 210 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 220 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 230 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 240 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 250 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 260 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 270 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 280 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 290 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 2a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 2b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 2c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 2d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 2e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 2f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* const */
-/* 300 */ 0x3f2a6400, 0xbf317600, 0x3e8d8e00, 0x00000000,
-/* 310 */ 0x3f2f7000, 0x3f36e200, 0x3e10c500, 0x00000000,
-/* 320 */ 0xbe974e00, 0x3dc35300, 0x3f735800, 0x00000000,
-/* 330 */ 0x00000000, 0x00000000, 0x00000000, 0x3f800000,
-/* 340 */ 0x42b00000, 0x42dc0000, 0x3f800000, 0x3f800000,
-/* 350 */ 0x42b00000, 0x42dc0000, 0x00000000, 0x00000000,
-/* 360 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 370 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 380 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 390 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 3a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 3b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 3c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 3d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 3e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* 3f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-/* inst */
-/* 400 */ 0xad4ad6b5, 0x438002b5, 0x0007ffe0, 0x00001e00,
-/* 410 */ 0xad4ad694, 0x038002b5, 0x0087ffe0, 0x00005030,
-/* 420 */ 0xad4bda56, 0x038002b5, 0x0007ffe0, 0x00001c10,
-/* 430 */ 0xad4ad6b5, 0x038002b5, 0x4007fee0, 0x00001c00
-};
-
-static struct clk *mali_clk = NULL;
-
-#if MESON_CPU_TYPE <= MESON_CPU_TYPE_MESON6
-
-#define OFFSET_MMU_DTE 0
-#define OFFSET_MMU_PTE 4096
-#define OFFSET_MMU_VIRTUAL_ZERO 8192
-
-#define INT_MALI_GP_BITS (1<<16)
-#define INT_MALI_PP_BITS (1<<18)
-#define INT_MALI_PP_MMU_BITS (1<<19)
-#define INT_ALL (0xffffffff)
-
-#define INT_MALI_PP_MMU_PAGE_FAULT (1<<0)
-
-#define MMU_FLAG_DTE_PRESENT 0x01
-#define MMU_FLAG_PTE_PAGE_PRESENT 0x01
-#define MMU_FLAG_PTE_RD_PERMISSION 0x02
-#define MMU_FLAG_PTE_WR_PERMISSION 0x04
-
-//static int mali_revb_flag = -1;
-static DEFINE_SPINLOCK(lock);
-extern int mali_revb_flag;
-int mali_meson_is_revb(void)
-{
- printk("mail version=%d\n",mali_revb_flag);
- if (mali_revb_flag == -1)
- mali_revb_flag = 1;
- else if (mali_revb_flag == 0)
- panic("rev-a! you should neet earlier version of mali_driver.!\n");
-
- return mali_revb_flag;
-}
-
-static void mali_meson_poweron(int first_poweron)
-{
- unsigned long flags;
- u32 p, p_aligned;
- dma_addr_t p_phy;
- int i;
- unsigned int_mask;
-
- if(!first_poweron) {
- if ((last_power_mode != -1) && (last_power_mode != MALI_POWER_MODE_DEEP_SLEEP)) {
- MALI_DEBUG_PRINT(3, ("Maybe your system not deep sleep now.......\n"));
- //printk("Maybe your system not deep sleep now.......\n");
- return;
- }
- }
-
- MALI_DEBUG_PRINT(2, ("mali_meson_poweron: Mali APB bus accessing\n"));
- if (READ_MALI_REG(MALI_PP_PP_VERSION) != MALI_PP_PP_VERSION_MAGIC) {
- MALI_DEBUG_PRINT(3, ("mali_meson_poweron: Mali APB bus access failed\n"));
- //printk("mali_meson_poweron: Mali APB bus access failed.");
- return;
- }
- MALI_DEBUG_PRINT(2, ("..........accessing done.\n"));
- if (READ_MALI_REG(MALI_MMU_DTE_ADDR) != 0) {
- MALI_DEBUG_PRINT(3, ("mali_meson_poweron: Mali is not really powered off\n"));
- //printk("mali_meson_poweron: Mali is not really powered off.");
- return;
- }
-
- p = (u32)kcalloc(4096 * 4, 1, GFP_KERNEL);
- if (!p) {
- printk("mali_meson_poweron: NOMEM in meson_poweron\n");
- return;
- }
-
- p_aligned = __ALIGN_MASK(p, 4096);
-
- /* DTE */
- *(u32 *)(p_aligned) = (virt_to_phys((void *)p_aligned) + OFFSET_MMU_PTE) | MMU_FLAG_DTE_PRESENT;
- /* PTE */
- for (i=0; i<1024; i++) {
- *(u32 *)(p_aligned + OFFSET_MMU_PTE + i*4) =
- (virt_to_phys((void *)p_aligned) + OFFSET_MMU_VIRTUAL_ZERO + 4096 * i) |
- MMU_FLAG_PTE_PAGE_PRESENT |
- MMU_FLAG_PTE_RD_PERMISSION;
- }
-
- /* command & data */
- memcpy((void *)(p_aligned + OFFSET_MMU_VIRTUAL_ZERO), poweron_data, 4096);
-
- p_phy = dma_map_single(NULL, (void *)p_aligned, 4096 * 3, DMA_TO_DEVICE);
-
- /* Set up Mali GP MMU */
- WRITE_MALI_REG(MALI_MMU_DTE_ADDR, p_phy);
- WRITE_MALI_REG(MALI_MMU_CMD, 0);
-
- if ((READ_MALI_REG(MALI_MMU_STATUS) & 1) != 1)
- printk("mali_meson_poweron: MMU enabling failed.\n");
-
- /* Set up Mali command registers */
- WRITE_MALI_REG(MALI_APB_GP_VSCL_START, 0);
- WRITE_MALI_REG(MALI_APB_GP_VSCL_END, 0x38);
-
- spin_lock_irqsave(&lock, flags);
-
- int_mask = READ_MALI_REG(MALI_APB_GP_INT_MASK);
- WRITE_MALI_REG(MALI_APB_GP_INT_CLEAR, 0x707bff);
- WRITE_MALI_REG(MALI_APB_GP_INT_MASK, 0);
-
- /* Start GP */
- WRITE_MALI_REG(MALI_APB_GP_CMD, 1);
-
- for (i = 0; i<100; i++)
- udelay(500);
-
- /* check Mali GP interrupt */
- if (READ_MALI_REG(MALI_APB_GP_INT_RAWSTAT) & 0x707bff)
- printk("mali_meson_poweron: Interrupt received.\n");
- else
- printk("mali_meson_poweron: No interrupt received.\n");
-
- /* force reset GP */
- WRITE_MALI_REG(MALI_APB_GP_CMD, 1 << 5);
-
- /* stop MMU paging and reset */
- WRITE_MALI_REG(MALI_MMU_CMD, 1);
- WRITE_MALI_REG(MALI_MMU_CMD, 6);
-
- for (i = 0; i<100; i++)
- udelay(500);
-
- WRITE_MALI_REG(MALI_APB_GP_INT_CLEAR, 0x3ff);
- WRITE_MALI_REG(MALI_MMU_INT_CLEAR, INT_ALL);
- WRITE_MALI_REG(MALI_MMU_INT_MASK, 0);
-
- WRITE_MALI_REG(MALI_APB_GP_INT_CLEAR, 0x707bff);
- WRITE_MALI_REG(MALI_APB_GP_INT_MASK, int_mask);
-
- spin_unlock_irqrestore(&lock, flags);
-
- dma_unmap_single(NULL, p_phy, 4096 * 3, DMA_TO_DEVICE);
-
- kfree((void *)p);
-
- /* Mali revision detection */
- if (last_power_mode == -1)
- mali_revb_flag = mali_meson_is_revb();
-}
-#else
-static void mali_meson_poweron(int first_poweron) {
- return;
-}
-#endif /*MESON_CPU_TYPE <= MESON_CPU_TYPE_MESON6 */
-
-_mali_osk_errcode_t mali_platform_init(void)
-{
- mali_clk = clk_get_sys("mali", "pll_fixed");
-
- if (mali_clk ) {
- if (!mali_init_flag) {
- clk_set_rate(mali_clk, 333000000);
- mali_clk->enable(mali_clk);
- malifix_init();
- mali_meson_poweron(1);
- mali_init_flag = 1;
- }
- MALI_SUCCESS;
- } else
- panic("linux kernel should > 3.0\n");
-
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6
- MALI_PRINT_ERROR(("Failed to lookup mali clock"));
- MALI_ERROR(_MALI_OSK_ERR_FAULT);
-#else
- MALI_SUCCESS;
-#endif /* CONFIG_ARCH_MESON6 */
-}
-
-_mali_osk_errcode_t mali_platform_deinit(void)
-{
- mali_init_flag =0;
- printk("MALI:mali_platform_deinit\n");
- malifix_exit();
-
- MALI_SUCCESS;
-}
-
-_mali_osk_errcode_t mali_platform_power_mode_change(mali_power_mode power_mode)
-{
- MALI_DEBUG_PRINT(3, ( "mali_platform_power_mode_change power_mode=%d\n", power_mode));
-
- switch (power_mode) {
- case MALI_POWER_MODE_LIGHT_SLEEP:
- case MALI_POWER_MODE_DEEP_SLEEP:
- /* Turn off mali clock gating */
- mali_clk->disable(mali_clk);
- break;
-
- case MALI_POWER_MODE_ON:
- /* Turn on MALI clock gating */
- mali_clk->enable(mali_clk);
- mali_meson_poweron(0);
- break;
- }
- last_power_mode = power_mode;
- MALI_SUCCESS;
-}
-
+++ /dev/null
-/*
- * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
- *
- * A copy of the licence is included with the program, and can also be obtained from Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-/**
- * @file mali_platform.h
- * Platform specific Mali driver functions
- */
-
-#ifndef __MALI_PLATFORM_H__
-#define __MALI_PLATFORM_H__
-
-#include "mali_osk.h"
-
-/** @brief description of power change reasons
- */
-typedef enum mali_power_mode_tag
-{
- MALI_POWER_MODE_ON, /**< Power Mali on */
- MALI_POWER_MODE_LIGHT_SLEEP, /**< Mali has been idle for a short time, or runtime PM suspend */
- MALI_POWER_MODE_DEEP_SLEEP, /**< Mali has been idle for a long time, or OS suspend */
-} mali_power_mode;
-
-/** @brief Platform specific setup and initialisation of MALI
- *
- * This is called from the entrypoint of the driver to initialize the platform
- *
- * @return _MALI_OSK_ERR_OK on success otherwise, a suitable _mali_osk_errcode_t error.
- */
-_mali_osk_errcode_t mali_platform_init(void);
-
-/** @brief Platform specific deinitialisation of MALI
- *
- * This is called on the exit of the driver to terminate the platform
- *
- * @return _MALI_OSK_ERR_OK on success otherwise, a suitable _mali_osk_errcode_t error.
- */
-_mali_osk_errcode_t mali_platform_deinit(void);
-
-/** @brief Platform specific powerdown sequence of MALI
- *
- * Notification from the Mali device driver stating the new desired power mode.
- * MALI_POWER_MODE_ON must be obeyed, while the other modes are optional.
- * @param power_mode defines the power modes
- * @return _MALI_OSK_ERR_OK on success otherwise, a suitable _mali_osk_errcode_t error.
- */
-_mali_osk_errcode_t mali_platform_power_mode_change(mali_power_mode power_mode);
-
-
-/** @brief Platform specific handling of GPU utilization data
- *
- * When GPU utilization data is enabled, this function will be
- * periodically called.
- *
- * @param utilization The workload utilization of the Mali GPU. 0 = no utilization, 256 = full utilization.
- */
-void mali_gpu_utilization_handler(u32 utilization);
-
-/** @brief Setting the power domain of MALI
- *
- * This function sets the power domain of MALI if Linux run time power management is enabled
- *
- * @param dev Reference to struct platform_device (defined in linux) used by MALI GPU
- */
-void set_mali_parent_power_domain(void* dev);
-
-#endif
+++ /dev/null
-/*
- * This confidential and proprietary software may be used only as
- * authorised by a licensing agreement from AMLOGIC, INC.
- * (C) COPYRIGHT 2011 AMLOGIC, INC.
- * ALL RIGHTS RESERVED
- * The entire notice above must be reproduced on all authorised
- * copies and copies may only be made to the extent permitted
- * by a licensing agreement from AMLOGIC, INC.
- */
-
-#ifndef MALI_POWERON_REG_H
-#define MALI_POWERON_REG_H
-
-#define MALI_PP_PP_VERSION_MAGIC 0xCD070100UL
-
-#if defined(IO_APB2_BUS_PHY_BASE)
-#define WRITE_MALI_REG(reg, val) \
- __raw_writel(val, (volatile void *)(reg - IO_APB2_BUS_PHY_BASE + IO_APB2_BUS_BASE))
-#define READ_MALI_REG(reg) \
- __raw_readl((volatile void *)(reg - IO_APB2_BUS_PHY_BASE + IO_APB2_BUS_BASE))
-#else
-#define WRITE_MALI_REG(reg, val) \
- __raw_writel(val, (volatile void *)(reg - IO_APB_BUS_PHY_BASE + IO_APB_BUS_BASE))
-#define READ_MALI_REG(reg) \
- __raw_readl((volatile void *)(reg - IO_APB_BUS_PHY_BASE + IO_APB_BUS_BASE))
-#endif
-
-#define MALI_APB_GP_VSCL_START 0xd0060000
-#define MALI_APB_GP_VSCL_END 0xd0060004
-#define MALI_APB_GP_CMD 0xd0060020
-#define MALI_APB_GP_INT_RAWSTAT 0xd0060024
-#define MALI_APB_GP_INT_CLEAR 0xd0060028
-#define MALI_APB_GP_INT_MASK 0xd006002c
-#define MALI_APB_GP_INT_STAT 0xd0060030
-
-#define MALI_MMU_DTE_ADDR 0xd0063000
-#define MALI_MMU_STATUS 0xd0063004
-#define MALI_MMU_CMD 0xd0063008
-#define MALI_MMU_RAW_STATUS 0xd0064014
-#define MALI_MMU_INT_CLEAR 0xd0064018
-#define MALI_MMU_INT_MASK 0xd006401c
-#define MALI_MMU_INT_STATUS 0xd0064020
-
-#define MALI_PP_MMU_DTE_ADDR 0xd0064000
-#define MALI_PP_MMU_STATUS 0xd0064004
-#define MALI_PP_MMU_CMD 0xd0064008
-#define MALI_PP_MMU_RAW_STATUS 0xd0064014
-#define MALI_PP_MMU_INT_CLEAR 0xd0064018
-#define MALI_PP_MMU_INT_MASK 0xd006401c
-#define MALI_PP_MMU_INT_STATUS 0xd0064020
-
-#define MALI_APB_PP_REND_LIST_ADDR 0xd0068000
-#define MALI_APB_PP_REND_RSW_BASE 0xd0068004
-#define MALI_APB_PP_REND_VERTEX_BASE 0xd0068008
-#define MALI_APB_PPSUBPIXEL_SPECIFIER 0xd0068048
-#define MALI_APB_WB0_SOURCE_SELECT 0xd0068100
-#define MALI_APB_WB0_TARGET_ADDR 0xd0068104
-#define MALI_APB_WB0_TARGET_SCANLINE_LENGTH 0xd0068114
-
-#define MALI_PP_PP_VERSION 0xd0069000
-#define MALI_PP_STATUS 0xd0069008
-#define MALI_PP_CTRL_MGMT 0xd006900C
-#define MALI_PP_INT_RAWSTAT 0xd0069020
-#define MALI_PP_INT_CLEAR 0xd0069024
-#define MALI_PP_INT_MASK 0xd0069028
-#define MALI_PP_INT_STAT 0xd006902C
-
-#endif /* MALI_POWERON_REG_H */
+++ /dev/null
-/*
- * platform.c
- *
- * clock source setting and resource config
- *
- * Created on: Dec 4, 2013
- * Author: amlogic
- */
-
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/module.h>
-#include <linux/ioport.h>
-#include <linux/slab.h>
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#include <asm/io.h>
-#include <linux/mali/mali_utgard.h>
-
-#include <common/mali_kernel_common.h>
-#include <common/mali_osk_profiling.h>
-#include <common/mali_pmu.h>
-
-#include "meson_main.h"
-#include "mali_fix.h"
-#include "mali_platform.h"
-
-/**
- * For Meson 6tvd.
- *
- */
-
-#if MESON_CPU_TYPE <= MESON_CPU_TYPE_MESON6TV
-
-u32 mali_dvfs_clk[1];
-u32 mali_dvfs_clk_sample[1];
-
-#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6TV
-#undef INT_MALI_GP
-#undef INT_MALI_GP_MMU
-#undef INT_MALI_PP
-#undef INT_MALI_PP2
-#undef INT_MALI_PP3
-#undef INT_MALI_PP4
-#undef INT_MALI_PP_MMU
-#undef INT_MALI_PP2_MMU
-#undef INT_MALI_PP3_MMU
-#undef INT_MALI_PP4_MMU
-
-#define INT_MALI_GP (48+32)
-#define INT_MALI_GP_MMU (49+32)
-#define INT_MALI_PP (50+32)
-#define INT_MALI_PP2 (58+32)
-#define INT_MALI_PP3 (60+32)
-#define INT_MALI_PP4 (62+32)
-#define INT_MALI_PP_MMU (51+32)
-#define INT_MALI_PP2_MMU (59+32)
-#define INT_MALI_PP3_MMU (61+32)
-#define INT_MALI_PP4_MMU (63+32)
-
-#ifndef CONFIG_MALI400_4_PP
-static struct resource meson_mali_resources[] =
-{
- MALI_GPU_RESOURCES_MALI400_MP2(0xd0060000,
- INT_MALI_GP, INT_MALI_GP_MMU,
- INT_MALI_PP, INT_MALI_PP_MMU,
- INT_MALI_PP2, INT_MALI_PP2_MMU)
-};
-#else
-static struct resource meson_mali_resources[] =
-{
- MALI_GPU_RESOURCES_MALI400_MP4(0xd0060000,
- INT_MALI_GP, INT_MALI_GP_MMU,
- INT_MALI_PP, INT_MALI_PP_MMU,
- INT_MALI_PP2, INT_MALI_PP2_MMU,
- INT_MALI_PP3, INT_MALI_PP3_MMU,
- INT_MALI_PP4, INT_MALI_PP4_MMU
- )
-};
-#endif
-
-#elif MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
-
-#undef INT_MALI_GP
-#undef INT_MALI_GP_MMU
-#undef INT_MALI_PP
-#undef INT_MALI_PP2
-#undef INT_MALI_PP_MMU
-#undef INT_MALI_PP2_MMU
-
-#define INT_MALI_GP (48+32)
-#define INT_MALI_GP_MMU (49+32)
-#define INT_MALI_PP (50+32)
-#define INT_MALI_PP_MMU (51+32)
-#define INT_MALI_PP2_MMU ( 6+32)
-
-static struct resource meson_mali_resources[] =
-{
- MALI_GPU_RESOURCES_MALI400_MP2(0xd0060000,
- INT_MALI_GP, INT_MALI_GP_MMU,
- INT_MALI_PP, INT_MALI_PP2_MMU,
- INT_MALI_PP_MMU, INT_MALI_PP2_MMU)
-};
-
-#else /* MESON_CPU_TYPE == MESON_CPU_TYPE_MESON3 */
-
-#undef INT_MALI_GP
-#undef INT_MALI_GP_MMU
-#undef INT_MALI_PP
-#undef INT_MALI_PP_MMU
-
-#define INT_MALI_GP 48
-#define INT_MALI_GP_MMU 49
-#define INT_MALI_PP 50
-#define INT_MALI_PP_MMU 51
-
-static struct resource meson_mali_resources[] =
-{
- MALI_GPU_RESOURCES_MALI400_MP1(0xd0060000,
- INT_MALI_GP, INT_MALI_GP_MMU, INT_MALI_PP, INT_MALI_PP_MMU)
-};
-#endif /* MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6TV */
-
-void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data)
-{
-
-}
-
-mali_plat_info_t mali_plat_data = {
-
-};
-
-int mali_meson_init_start(struct platform_device* ptr_plt_dev)
-{
- /* for mali platform data. */
- struct mali_gpu_device_data* pdev = ptr_plt_dev->dev.platform_data;
-
- pdev->control_interval = 1000;
- pdev->utilization_callback = mali_gpu_utilization_callback;
-
- /* for resource data. */
- ptr_plt_dev->num_resources = ARRAY_SIZE(meson_mali_resources);
- ptr_plt_dev->resource = meson_mali_resources;
- return 0;
-}
-
-int mali_meson_init_finish(struct platform_device* ptr_plt_dev)
-{
- mali_platform_init();
- return 0;
-}
-
-int mali_meson_uninit(struct platform_device* ptr_plt_dev)
-{
- mali_platform_deinit();
- return 0;
-}
-
-int mali_light_suspend(struct device *device)
-{
- int ret = 0;
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_suspend(device);
- }
-
- mali_platform_power_mode_change(MALI_POWER_MODE_LIGHT_SLEEP);
- return ret;
-}
-
-int mali_light_resume(struct device *device)
-{
- int ret = 0;
-
- mali_platform_power_mode_change(MALI_POWER_MODE_ON);
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_resume(device);
- }
- return ret;
-}
-
-int mali_deep_suspend(struct device *device)
-{
- int ret = 0;
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->suspend(device);
- }
-
- mali_platform_power_mode_change(MALI_POWER_MODE_DEEP_SLEEP);
- return ret;
-}
-
-int mali_deep_resume(struct device *device)
-{
- int ret = 0;
-
- mali_platform_power_mode_change(MALI_POWER_MODE_ON);
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->resume(device);
- }
- return ret;
-
-}
-
-void mali_core_scaling_term(void)
-{
-
-}
-
-int get_gpu_max_clk_level(void)
-{
- return 0;
-}
-
-void mali_post_init(void)
-{
-}
-#endif /* MESON_CPU_TYPE <= MESON_CPU_TYPE_MESON6 */
+++ /dev/null
-/*
- * platform.c
- *
- * clock source setting and resource config
- *
- * Created on: Dec 4, 2013
- * Author: amlogic
- */
-
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/module.h> /* kernel module definitions */
-#include <linux/ioport.h> /* request_mem_region */
-#include <linux/slab.h>
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#include <asm/io.h>
-#include <linux/mali/mali_utgard.h>
-
-#include <common/mali_kernel_common.h>
-#include <common/mali_osk_profiling.h>
-#include <common/mali_pmu.h>
-
-#include "meson_main.h"
-
-/*
- * For Meson 8TVD.
- *
- */
-
-#define CFG_PP 2
-#define CFG_CLOCK 3
-#define CFG_MIN_PP 1
-#define CFG_MIN_CLOCK 0
-
-/* fclk is 2Ghz. */
-#define FCLK_DEV5 (7 << 9) /* 400 Mhz */
-#define FCLK_DEV3 (6 << 9) /* 666 Mhz */
-#define FCLK_DEV2 (5 << 9) /* 1000 Mhz */
-#define FCLK_DEV7 (4 << 9) /* 285 Mhz */
-
-u32 mali_dvfs_clk[] = {
- FCLK_DEV7 | 9, /* 100 Mhz */
- FCLK_DEV2 | 4, /* 200 Mhz */
- FCLK_DEV3 | 1, /* 333 Mhz */
- FCLK_DEV5 | 0, /* 400 Mhz */
-};
-
-u32 mali_dvfs_clk_sample[] = {
- 100, /* 182.1 Mhz */
- 200, /* 318.7 Mhz */
- 333, /* 425 Mhz */
- 400, /* 510 Mhz */
-};
-
-static mali_plat_info_t mali_plat_data = {
- .cfg_pp = CFG_PP, /* number of pp. */
- .cfg_min_pp = CFG_MIN_PP,
- .def_clock = CFG_CLOCK, /* gpu clock used most of time.*/
- .cfg_clock = CFG_CLOCK, /* max gpu clock. */
- .cfg_min_clock = CFG_MIN_CLOCK,
-
- .clk = mali_dvfs_clk, /* clock source table. */
- .clk_sample = mali_dvfs_clk_sample, /* freqency table for show. */
- .clk_len = sizeof(mali_dvfs_clk) / sizeof(mali_dvfs_clk[0]),
- .have_switch = 0,
-};
-
-#define MALI_USER_PP0 AM_IRQ4(31)
-
-static struct resource mali_gpu_resources[] =
-{
-MALI_GPU_RESOURCES_MALI450_MP2_PMU(0xC9140000, INT_MALI_GP, INT_MALI_GP_MMU,
- MALI_USER_PP0, INT_MALI_PP_MMU,
- INT_MALI_PP1, INT_MALI_PP_MMU1,
- INT_MALI_PP)
-};
-
-int mali_meson_init_start(struct platform_device* ptr_plt_dev)
-{
- ptr_plt_dev->num_resources = ARRAY_SIZE(mali_gpu_resources);
- ptr_plt_dev->resource = mali_gpu_resources;
- return mali_clock_init(&mali_plat_data);
-}
-
-int mali_meson_init_finish(struct platform_device* ptr_plt_dev)
-{
- return 0;
-}
-
-int mali_meson_uninit(struct platform_device* ptr_plt_dev)
-{
- return 0;
-}
-
-static int mali_cri_pmu_on_off(size_t param)
-{
- struct mali_pmu_core *pmu;
-
- MALI_DEBUG_PRINT(4, ("mali_os_suspend() called\n"));
- pmu = mali_pmu_get_global_pmu_core();
- if (param == 0)
- mali_pmu_power_down_all(pmu);
- else
- mali_pmu_power_up_all(pmu);
- return 0;
-}
-
-int mali_light_suspend(struct device *device)
-{
- int ret = 0;
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- 0, 0, 0, 0, 0);
-#endif
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_suspend(device);
- }
-
- /* clock scaling. Kasin..*/
- mali_clock_critical(mali_cri_pmu_on_off, 0);
- disable_clock();
- return ret;
-}
-
-int mali_light_resume(struct device *device)
-{
- int ret = 0;
- /* clock scaling. Kasin..*/
- enable_clock();
-
- mali_clock_critical(mali_cri_pmu_on_off, 1);
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- 0, 0, 0, 0, 0);
-#endif
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_resume(device);
- }
- return ret;
-}
-
-int mali_deep_suspend(struct device *device)
-{
- int ret = 0;
- //enable_clock();
- //flush_scaling_job();
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->suspend(device);
- }
-
- /* clock scaling off. Kasin... */
- mali_clock_critical(mali_cri_pmu_on_off, 0);
- disable_clock();
- return ret;
-}
-
-int mali_deep_resume(struct device *device)
-{
- int ret = 0;
- /* clock scaling up. Kasin.. */
- enable_clock();
- mali_clock_critical(mali_cri_pmu_on_off, 1);
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->resume(device);
- }
- return ret;
-
-}
-
-void mali_post_init(void)
-{
-}
+++ /dev/null
-/*
- * platform.c
- *
- * clock source setting and resource config
- *
- * Created on: Dec 4, 2013
- * Author: amlogic
- */
-
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/module.h> /* kernel module definitions */
-#include <linux/ioport.h> /* request_mem_region */
-#include <linux/slab.h>
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#endif
-#include <asm/io.h>
-#include <linux/mali/mali_utgard.h>
-#ifdef CONFIG_GPU_THERMAL
-#include <linux/gpu_cooling.h>
-#include <linux/gpucore_cooling.h>
-#endif
-#include <common/mali_kernel_common.h>
-#include <common/mali_osk_profiling.h>
-#include <common/mali_pmu.h>
-
-#include "meson_main.h"
-
-/*
- * For Meson 8 M2.
- *
- */
-
-#define CFG_PP 6
-#define CFG_CLOCK 3
-#define CFG_MIN_PP 1
-#define CFG_MIN_CLOCK 0
-
-/* fclk is 2550Mhz. */
-#define FCLK_DEV3 (6 << 9) /* 850 Mhz */
-#define FCLK_DEV4 (5 << 9) /* 637.5 Mhz */
-#define FCLK_DEV5 (7 << 9) /* 510 Mhz */
-#define FCLK_DEV7 (4 << 9) /* 364.3 Mhz */
-
-static u32 mali_dvfs_clk[] = {
- FCLK_DEV7 | 1, /* 182.1 Mhz */
- FCLK_DEV4 | 1, /* 318.7 Mhz */
- FCLK_DEV3 | 1, /* 425 Mhz */
- FCLK_DEV5 | 0, /* 510 Mhz */
- FCLK_DEV4 | 0, /* 637.5 Mhz */
-};
-
-static u32 mali_dvfs_clk_sample[] = {
- 182, /* 182.1 Mhz */
- 319, /* 318.7 Mhz */
- 425, /* 425 Mhz */
- 510, /* 510 Mhz */
- 637, /* 637.5 Mhz */
-};
-//////////////////////////////////////
-//for dvfs
-struct mali_gpu_clk_item meson_gpu_clk[] = {
- {182, 1150}, /* 182.1 Mhz, 1150mV */
- {319, 1150}, /* 318.7 Mhz */
- {425, 1150}, /* 425 Mhz */
- {510, 1150}, /* 510 Mhz */
- {637, 1150}, /* 637.5 Mhz */
-};
-struct mali_gpu_clock meson_gpu_clk_info = {
- .item = meson_gpu_clk,
- .num_of_steps = ARRAY_SIZE(meson_gpu_clk),
-};
-static int cur_gpu_clk_index = 0;
-//////////////////////////////////////
-static mali_dvfs_threshold_table mali_dvfs_table[]={
- { 0, 0, 3, 30, 80}, /* for 182.1 */
- { 1, 1, 3, 40, 205}, /* for 318.7 */
- { 2, 2, 3, 150, 215}, /* for 425.0 */
- { 3, 3, 3, 170, 253}, /* for 510.0 */
- { 4, 4, 3, 230, 255}, /* for 637.5 */
- { 0, 0, 3, 0, 0}
-};
-
-static void mali_plat_preheat(void);
-static mali_plat_info_t mali_plat_data = {
- .cfg_pp = CFG_PP, /* number of pp. */
- .cfg_min_pp = CFG_MIN_PP,
- .turbo_clock = 4, /* reserved clock src. */
- .def_clock = 2, /* gpu clock used most of time.*/
- .cfg_clock = CFG_CLOCK, /* max gpu clock. */
- .cfg_clock_bkup = CFG_CLOCK,
- .cfg_min_clock = CFG_MIN_CLOCK,
-
- .sc_mpp = 3, /* number of pp used most of time.*/
- .bst_gpu = 210, /* threshold for boosting gpu. */
- .bst_pp = 160, /* threshold for boosting PP. */
-
- .clk = mali_dvfs_clk, /* clock source table. */
- .clk_sample = mali_dvfs_clk_sample, /* freqency table for show. */
- .clk_len = sizeof(mali_dvfs_clk) / sizeof(mali_dvfs_clk[0]),
- .have_switch = 1,
-
- .dvfs_table = mali_dvfs_table, /* DVFS table. */
- .dvfs_table_size = sizeof(mali_dvfs_table) / sizeof(mali_dvfs_threshold_table),
-
- .scale_info = {
- CFG_MIN_PP, /* minpp */
- CFG_PP, /* maxpp, should be same as cfg_pp */
- CFG_MIN_CLOCK, /* minclk */
- CFG_CLOCK, /* maxclk should be same as cfg_clock */
- },
-
- .limit_on = 1,
- .plat_preheat = mali_plat_preheat,
-};
-
-static void mali_plat_preheat(void)
-{
-#ifndef CONFIG_MALI_DVFS
- u32 pre_fs;
- u32 clk, pp;
-
- if (get_mali_schel_mode() != MALI_PP_FS_SCALING)
- return;
-
- get_mali_rt_clkpp(&clk, &pp);
- pre_fs = mali_plat_data.def_clock + 1;
- if (clk < pre_fs)
- clk = pre_fs;
- if (pp < mali_plat_data.sc_mpp)
- pp = mali_plat_data.sc_mpp;
- set_mali_rt_clkpp(clk, pp, 1);
-#endif
-}
-
-mali_plat_info_t* get_mali_plat_data(void) {
- return &mali_plat_data;
-}
-
-int get_mali_freq_level(int freq)
-{
- int i = 0, level = -1;
- int mali_freq_num;
-
- if (freq < 0)
- return level;
-
- mali_freq_num = mali_plat_data.dvfs_table_size - 1;
- if (freq <= mali_plat_data.clk_sample[0])
- level = mali_freq_num-1;
- if (freq >= mali_plat_data.clk_sample[mali_freq_num - 1])
- level = 0;
- for (i=0; i<mali_freq_num - 1 ;i++) {
- if (freq >= mali_plat_data.clk_sample[i] && freq <= mali_plat_data.clk_sample[i + 1]) {
- level = i;
- level = mali_freq_num-level - 1;
- }
- }
- return level;
-}
-
-unsigned int get_mali_max_level(void)
-{
- return mali_plat_data.dvfs_table_size - 1;
-}
-
-#if 0
-static struct resource mali_gpu_resources[] =
-{
- MALI_GPU_RESOURCES_MALI450_MP6_PMU(IO_MALI_APB_PHY_BASE, INT_MALI_GP, INT_MALI_GP_MMU,
- INT_MALI_PP0, INT_MALI_PP0_MMU,
- INT_MALI_PP1, INT_MALI_PP1_MMU,
- INT_MALI_PP2, INT_MALI_PP2_MMU,
- INT_MALI_PP4, INT_MALI_PP4_MMU,
- INT_MALI_PP5, INT_MALI_PP5_MMU,
- INT_MALI_PP6, INT_MALI_PP6_MMU,
- INT_MALI_PP)
-};
-#else
-static struct resource mali_gpu_resources[] =
-{
- { .name = "Mali_L2", .flags = 0x00000200, .start = 0xd00c0000 + 0x10000, .end = 0xd00c0000 + 0x10000 + 0x200, },
- { .name = "Mali_GP", .flags = 0x00000200, .start = 0xd00c0000 + 0x00000, .end = 0xd00c0000 + 0x00000 + 0x100, },
- { .name = "Mali_GP_IRQ", .flags = 0x00000400, .start = (160 + 32), .end = (160 + 32), },
- { .name = "Mali_GP_MMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x03000, .end = 0xd00c0000 + 0x03000 + 0x100, },
- { .name = "Mali_GP_MMU_IRQ", .flags = 0x00000400, .start = (161 + 32), .end = (161 + 32), },
- { .name = "Mali_L2", .flags = 0x00000200, .start = 0xd00c0000 + 0x01000, .end = 0xd00c0000 + 0x01000 + 0x200, },
- { .name = "Mali_PP" "0", .flags = 0x00000200, .start = 0xd00c0000 + 0x08000, .end = 0xd00c0000 + 0x08000 + 0x1100, },
- { .name = "Mali_PP" "0" "_IRQ", .flags = 0x00000400, .start = (164 + 32), .end = (164 + 32), },
- { .name = "Mali_PP" "0" "_MMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x04000, .end = 0xd00c0000 + 0x04000 + 0x100, },
- { .name = "Mali_PP" "0" "_MMU_IRQ", .flags = 0x00000400, .start = (165 + 32), .end = (165 + 32), },
- { .name = "Mali_PP" "1", .flags = 0x00000200, .start = 0xd00c0000 + 0x0A000, .end = 0xd00c0000 + 0x0A000 + 0x1100, },
- { .name = "Mali_PP" "1" "_IRQ", .flags = 0x00000400, .start = (166 + 32), .end = (166 + 32), },
- { .name = "Mali_PP" "1" "_MMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x05000, .end = 0xd00c0000 + 0x05000 + 0x100, },
- { .name = "Mali_PP" "1" "_MMU_IRQ", .flags = 0x00000400, .start = (167 + 32), .end = (167 + 32), },
- { .name = "Mali_PP" "2", .flags = 0x00000200, .start = 0xd00c0000 + 0x0C000, .end = 0xd00c0000 + 0x0C000 + 0x1100, },
- { .name = "Mali_PP" "2" "_IRQ", .flags = 0x00000400, .start = (168 + 32), .end = (168 + 32), },
- { .name = "Mali_PP" "2" "_MMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x06000, .end = 0xd00c0000 + 0x06000 + 0x100, },
- { .name = "Mali_PP" "2" "_MMU_IRQ", .flags = 0x00000400, .start = (169 + 32), .end = (169 + 32), },
- { .name = "Mali_L2", .flags = 0x00000200, .start = 0xd00c0000 + 0x11000, .end = 0xd00c0000 + 0x11000 + 0x200, },
- { .name = "Mali_PP" "3", .flags = 0x00000200, .start = 0xd00c0000 + 0x28000, .end = 0xd00c0000 + 0x28000 + 0x1100, },
- { .name = "Mali_PP" "3" "_IRQ", .flags = 0x00000400, .start = (172 + 32), .end = (172 + 32), },
- { .name = "Mali_PP" "3" "_MMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x1C000, .end = 0xd00c0000 + 0x1C000 + 0x100, },
- { .name = "Mali_PP" "3" "_MMU_IRQ", .flags = 0x00000400, .start = (173 + 32), .end = (173 + 32), },
- { .name = "Mali_PP" "4", .flags = 0x00000200, .start = 0xd00c0000 + 0x2A000, .end = 0xd00c0000 + 0x2A000 + 0x1100, },
- { .name = "Mali_PP" "4" "_IRQ", .flags = 0x00000400, .start = (174 + 32), .end = (174 + 32), },
- { .name = "Mali_PP" "4" "_MMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x1D000, .end = 0xd00c0000 + 0x1D000 + 0x100, },
- { .name = "Mali_PP" "4" "_MMU_IRQ", .flags = 0x00000400, .start = (175 + 32), .end = (175 + 32), },
- { .name = "Mali_PP" "5", .flags = 0x00000200, .start = 0xd00c0000 + 0x2C000, .end = 0xd00c0000 + 0x2C000 + 0x1100, },
- { .name = "Mali_PP" "5" "_IRQ", .flags = 0x00000400, .start = (176 + 32), .end = (176 + 32), },
- { .name = "Mali_PP" "5" "_MMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x1E000, .end = 0xd00c0000 + 0x1E000 + 0x100, },
- { .name = "Mali_PP" "5" "_MMU_IRQ", .flags = 0x00000400, .start = (177 + 32), .end = (177 + 32), },
- { .name = "Mali_Broadcast", .flags = 0x00000200, .start = 0xd00c0000 + 0x13000, .end = 0xd00c0000 + 0x13000 + 0x100, },
- { .name = "Mali_DLBU", .flags = 0x00000200, .start = 0xd00c0000 + 0x14000, .end = 0xd00c0000 + 0x14000 + 0x100, },
- { .name = "Mali_PP_Broadcast", .flags = 0x00000200, .start = 0xd00c0000 + 0x16000, .end = 0xd00c0000 + 0x16000 + 0x1100, },
- { .name = "Mali_PP_Broadcast_IRQ", .flags = 0x00000400, .start = (162 + 32), .end = (162 + 32), },
- { .name = "Mali_PP_MMU_Broadcast", .flags = 0x00000200, .start = 0xd00c0000 + 0x15000, .end = 0xd00c0000 + 0x15000 + 0x100, },
- { .name = "Mali_DMA", .flags = 0x00000200, .start = 0xd00c0000 + 0x12000, .end = 0xd00c0000 + 0x12000 + 0x100, },
- { .name = "Mali_PMU", .flags = 0x00000200, .start = 0xd00c0000 + 0x02000, .end = 0xd00c0000 + 0x02000 + 0x100, },
-};
-#endif
-#ifdef CONFIG_GPU_THERMAL
-static void set_limit_mali_freq(u32 idx)
-{
- if (mali_plat_data.limit_on == 0)
- return;
- if (idx > mali_plat_data.turbo_clock || idx < mali_plat_data.scale_info.minclk)
- return;
- mali_plat_data.scale_info.maxclk= idx;
- revise_mali_rt();
-}
-
-static u32 get_limit_mali_freq(void)
-{
- return mali_plat_data.scale_info.maxclk;
-}
-#endif
-
-#ifdef CONFIG_GPU_THERMAL
-static u32 set_limit_pp_num(u32 num)
-{
- u32 ret = -1;
- if (mali_plat_data.limit_on == 0)
- goto quit;
- if (num > mali_plat_data.cfg_pp ||
- num < mali_plat_data.scale_info.minpp)
- goto quit;
- mali_plat_data.scale_info.maxpp = num;
- revise_mali_rt();
- ret = 0;
-quit:
- return ret;
-}
-#endif
-
-void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data);
-
-#if 0
-struct mali_gpu_clk_item {
- unsigned int clock; /* unit(MHz) */
- unsigned int vol;
-};
-
-struct mali_gpu_clock {
- struct mali_gpu_clk_item *item;
- unsigned int num_of_steps;
-};
-#endif
-
-/* Function that platfrom report it's clock info which driver can set, needed when CONFIG_MALI_DVFS enabled */
-void meson_platform_get_clock_info(struct mali_gpu_clock **data) {
- *data = &meson_gpu_clk_info;
-}
-
-/* Function that get the current clock info, needed when CONFIG_MALI_DVFS enabled */
-int meson_platform_get_freq(void) {
- printk("get cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
- return cur_gpu_clk_index;
-}
-
-/* Fuction that platform callback for freq setting, needed when CONFIG_MALI_DVFS enabled */
-int meson_platform_set_freq(int setting_clock_step) {
-
- if (cur_gpu_clk_index == setting_clock_step) {
- return 0;
- }
-
- mali_clock_set(setting_clock_step);
-
- cur_gpu_clk_index = setting_clock_step;
- printk("set cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
-
- return 0;
-}
-
-int mali_meson_init_start(struct platform_device* ptr_plt_dev)
-{
- struct mali_gpu_device_data* pdev = ptr_plt_dev->dev.platform_data;
-
- /* chip mark detect. */
-#ifdef IS_MESON_M8_CPU
- if (IS_MESON_M8_CPU) {
- mali_plat_data.have_switch = 0;
- }
-#endif
-
- /* for resource data. */
- ptr_plt_dev->num_resources = ARRAY_SIZE(mali_gpu_resources);
- ptr_plt_dev->resource = mali_gpu_resources;
-
- /*for dvfs*/
-#ifndef CONFIG_MALI_DVFS
- /* for mali platform data. */
- pdev->control_interval = 300;
- pdev->utilization_callback = mali_gpu_utilization_callback;
-#else
- pdev->get_clock_info = meson_platform_get_clock_info;
- pdev->get_freq = meson_platform_get_freq;
- pdev->set_freq = meson_platform_set_freq;
-#endif
-
- return mali_clock_init(&mali_plat_data);
-}
-
-int mali_meson_init_finish(struct platform_device* ptr_plt_dev)
-{
-#ifndef CONFIG_MALI_DVFS
- if (mali_core_scaling_init(&mali_plat_data) < 0)
- return -1;
-#else
- printk("disable meson own dvfs\n");
-#endif
- return 0;
-}
-
-int mali_meson_uninit(struct platform_device* ptr_plt_dev)
-{
- return 0;
-}
-
-static int mali_cri_light_suspend(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- mali_pm_statue = 1;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_suspend(device);
- }
- mali_pmu_power_down_all(pmu);
- return ret;
-}
-
-static int mali_cri_light_resume(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- mali_pmu_power_up_all(pmu);
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_resume(device);
- }
- mali_pm_statue = 0;
- return ret;
-}
-
-static int mali_cri_deep_suspend(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->suspend(device);
- }
- mali_pmu_power_down_all(pmu);
- return ret;
-}
-
-static int mali_cri_deep_resume(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- mali_pmu_power_up_all(pmu);
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->resume(device);
- }
- return ret;
-
-}
-
-int mali_light_suspend(struct device *device)
-{
- int ret = 0;
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- 0, 0, 0, 0, 0);
-#endif
-
- /* clock scaling. Kasin..*/
- ret = mali_clock_critical(mali_cri_light_suspend, (size_t)device);
- disable_clock();
- return ret;
-}
-
-int mali_light_resume(struct device *device)
-{
- int ret = 0;
- enable_clock();
- ret = mali_clock_critical(mali_cri_light_resume, (size_t)device);
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- get_current_frequency(), 0, 0, 0, 0);
-#endif
- return ret;
-}
-
-int mali_deep_suspend(struct device *device)
-{
- int ret = 0;
-
- mali_pm_statue = 1;
- enable_clock();
-#ifndef CONFIG_MALI_DVFS
- flush_scaling_job();
-#endif
-
- /* clock scaling off. Kasin... */
- ret = mali_clock_critical(mali_cri_deep_suspend, (size_t)device);
- disable_clock();
- return ret;
-}
-
-int mali_deep_resume(struct device *device)
-{
- int ret = 0;
-
- /* clock scaling up. Kasin.. */
- enable_clock();
- ret = mali_clock_critical(mali_cri_deep_resume, (size_t)device);
- mali_pm_statue = 0;
- return ret;
-
-}
-
-void mali_post_init(void)
-{
-#ifdef CONFIG_GPU_THERMAL
- int err;
- struct gpufreq_cooling_device *gcdev = NULL;
- struct gpucore_cooling_device *gccdev = NULL;
-
- gcdev = gpufreq_cooling_alloc();
- register_gpu_freq_info(get_current_frequency);
- if (IS_ERR(gcdev))
- printk("malloc gpu cooling buffer error!!\n");
- else if (!gcdev)
- printk("system does not enable thermal driver\n");
- else {
- gcdev->get_gpu_freq_level = get_mali_freq_level;
- gcdev->get_gpu_max_level = get_mali_max_level;
- gcdev->set_gpu_freq_idx = set_limit_mali_freq;
- gcdev->get_gpu_current_max_level = get_limit_mali_freq;
- err = gpufreq_cooling_register(gcdev);
- if (err < 0)
- printk("register GPU cooling error\n");
- printk("gpu cooling register okay with err=%d\n",err);
- }
-
- gccdev = gpucore_cooling_alloc();
- if (IS_ERR(gccdev))
- printk("malloc gpu core cooling buffer error!!\n");
- else if (!gccdev)
- printk("system does not enable thermal driver\n");
- else {
- gccdev->max_gpu_core_num=mali_plat_data.cfg_pp;
- gccdev->set_max_pp_num=set_limit_pp_num;
- err = (int)gpucore_cooling_register(gccdev);
- if (err < 0)
- printk("register GPU cooling error\n");
- printk("gpu core cooling register okay with err=%d\n",err);
- }
-#endif
-}
+++ /dev/null
-/*
- * platform.c
- *
- * clock source setting and resource config
- *
- * Created on: Dec 4, 2013
- * Author: amlogic
- */
-
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/module.h> /* kernel module definitions */
-#include <linux/ioport.h> /* request_mem_region */
-#include <linux/slab.h>
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#include <asm/io.h>
-#include <linux/mali/mali_utgard.h>
-#include <linux/gpu_cooling.h>
-#include <linux/gpucore_cooling.h>
-#include <common/mali_kernel_common.h>
-#include <common/mali_osk_profiling.h>
-#include <common/mali_pmu.h>
-
-#include "meson_main.h"
-
-/*
- * For Meson 8B.
- *
- */
-
-#define CFG_PP 2
-#define CFG_CLOCK 3
-#define CFG_MIN_PP 1
-#define CFG_MIN_CLOCK 0
-
-/* fclk is 2550Mhz. */
-#define FCLK_DEV3 (6 << 9) /* 850 Mhz */
-#define FCLK_DEV4 (5 << 9) /* 637.5 Mhz */
-#define FCLK_DEV5 (7 << 9) /* 510 Mhz */
-#define FCLK_DEV7 (4 << 9) /* 364.3 Mhz */
-
-static u32 mali_dvfs_clk[] = {
- FCLK_DEV5 | 1, /* 255 Mhz */
- FCLK_DEV7 | 0, /* 364 Mhz */
- FCLK_DEV3 | 1, /* 425 Mhz */
- FCLK_DEV5 | 0, /* 510 Mhz */
- FCLK_DEV4 | 0, /* 637.5 Mhz */
-};
-
-static u32 mali_dvfs_clk_sample[] = {
- 255, /* 182.1 Mhz */
- 364, /* 318.7 Mhz */
- 425, /* 425 Mhz */
- 510, /* 510 Mhz */
- 637, /* 637.5 Mhz */
-};
-
-//////////////////////////////////////
-//for dvfs
-struct mali_gpu_clk_item meson_gpu_clk[] = {
- {255, 1150}, /* 182.1 Mhz, 1150mV */
- {364, 1150}, /* 318.7 Mhz */
- {425, 1150}, /* 425 Mhz */
- {510, 1150}, /* 510 Mhz */
- {637, 1150}, /* 637.5 Mhz */
-};
-struct mali_gpu_clock meson_gpu_clk_info = {
- .item = meson_gpu_clk,
- .num_of_steps = ARRAY_SIZE(meson_gpu_clk),
-};
-static int cur_gpu_clk_index = 0;
-//////////////////////////////////////
-
-static mali_dvfs_threshold_table mali_dvfs_table[]={
- { 0, 0, 5, 30 , 180}, /* for 255 */
- { 1, 1, 5, 152, 205}, /* for 364 */
- { 2, 2, 5, 180, 212}, /* for 425 */
- { 3, 3, 5, 205, 236}, /* for 510 */
- { 4, 4, 5, 230, 255}, /* for 637 */
- { 0, 0, 5, 0, 0}
-};
-
-static void mali_plat_preheat(void);
-static mali_plat_info_t mali_plat_data = {
- .cfg_pp = CFG_PP, /* number of pp. */
- .cfg_min_pp = CFG_MIN_PP,
- .turbo_clock = 4, /* reserved clock src. */
- .def_clock = 2, /* gpu clock used most of time.*/
- .cfg_clock = CFG_CLOCK, /* max gpu clock. */
- .cfg_clock_bkup = CFG_CLOCK,
- .cfg_min_clock = CFG_MIN_CLOCK,
-
- .sc_mpp = 2, /* number of pp used most of time.*/
- .bst_gpu = 210, /* threshold for boosting gpu. */
- .bst_pp = 160, /* threshold for boosting PP. */
-
- .clk = mali_dvfs_clk, /* clock source table. */
- .clk_sample = mali_dvfs_clk_sample, /* freqency table for show. */
- .clk_len = sizeof(mali_dvfs_clk) / sizeof(mali_dvfs_clk[0]),
- .have_switch = 1,
-
- .dvfs_table = mali_dvfs_table, /* DVFS table. */
- .dvfs_table_size = sizeof(mali_dvfs_table) / sizeof(mali_dvfs_threshold_table),
-
- .scale_info = {
- CFG_MIN_PP, /* minpp */
- CFG_PP, /* maxpp, should be same as cfg_pp */
- CFG_MIN_CLOCK, /* minclk */
- CFG_CLOCK, /* maxclk should be same as cfg_clock */
- },
-
- .limit_on = 1,
- .plat_preheat = mali_plat_preheat,
-};
-
-static void mali_plat_preheat(void)
-{
-#ifndef CONFIG_MALI_DVFS
- u32 pre_fs;
- u32 clk, pp;
-
- if (get_mali_schel_mode() != MALI_PP_FS_SCALING)
- return;
-
- get_mali_rt_clkpp(&clk, &pp);
- pre_fs = mali_plat_data.def_clock + 1;
- if (clk < pre_fs)
- clk = pre_fs;
- if (pp < mali_plat_data.sc_mpp)
- pp = mali_plat_data.sc_mpp;
- set_mali_rt_clkpp(clk, pp, 1);
-#endif
-}
-
-mali_plat_info_t* get_mali_plat_data(void) {
- return &mali_plat_data;
-}
-
-int get_mali_freq_level(int freq)
-{
- int i = 0, level = -1;
- int mali_freq_num;
-
- if (freq < 0)
- return level;
- mali_freq_num = mali_plat_data.dvfs_table_size - 1;
- if (freq <= mali_plat_data.clk_sample[0])
- level = mali_freq_num-1;
- if (freq >= mali_plat_data.clk_sample[mali_freq_num - 1])
- level = 0;
- for (i=0; i<mali_freq_num - 1 ;i++) {
- if (freq >= mali_plat_data.clk_sample[i] && freq <= mali_plat_data.clk_sample[i + 1]) {
- level = i;
- level = mali_freq_num-level - 1;
- }
- }
- return level;
-}
-
-unsigned int get_mali_max_level(void)
-{
- return mali_plat_data.dvfs_table_size - 1;
-}
-
-static struct resource mali_gpu_resources[] =
-{
- MALI_GPU_RESOURCES_MALI450_MP2_PMU(IO_MALI_APB_PHY_BASE, INT_MALI_GP, INT_MALI_GP_MMU,
- INT_MALI_PP0, INT_MALI_PP0_MMU,
- INT_MALI_PP1, INT_MALI_PP1_MMU,
- INT_MALI_PP)
-};
-
-static void set_limit_mali_freq(u32 idx)
-{
- if (mali_plat_data.limit_on == 0)
- return;
- if (idx > mali_plat_data.turbo_clock || idx < mali_plat_data.scale_info.minclk)
- return;
- mali_plat_data.scale_info.maxclk= idx;
-
- revise_mali_rt();
-}
-
-static u32 get_limit_mali_freq(void)
-{
- return mali_plat_data.scale_info.maxclk;
-}
-
-static u32 set_limit_pp_num(u32 num)
-{
- u32 ret = -1;
- if (mali_plat_data.limit_on == 0)
- goto quit;
- if (num > mali_plat_data.cfg_pp ||
- num < mali_plat_data.scale_info.minpp)
- goto quit;
- mali_plat_data.scale_info.maxpp = num;
- revise_mali_rt();
- ret = 0;
-quit:
- return ret;
-}
-
-void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data);
-
-#if 0
-struct mali_gpu_clk_item {
- unsigned int clock; /* unit(MHz) */
- unsigned int vol;
-};
-
-struct mali_gpu_clock {
- struct mali_gpu_clk_item *item;
- unsigned int num_of_steps;
-};
-#endif
-
-/* Function that platfrom report it's clock info which driver can set, needed when CONFIG_MALI_DVFS enabled */
-void meson_platform_get_clock_info(struct mali_gpu_clock **data) {
- *data = &meson_gpu_clk_info;
-}
-
-/* Function that get the current clock info, needed when CONFIG_MALI_DVFS enabled */
-int meson_platform_get_freq(void) {
- printk("get cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
- return cur_gpu_clk_index;
-}
-
-/* Fuction that platform callback for freq setting, needed when CONFIG_MALI_DVFS enabled */
-int meson_platform_set_freq(int setting_clock_step) {
-
- if (cur_gpu_clk_index == setting_clock_step) {
- return 0;
- }
-
- mali_clock_set(setting_clock_step);
-
- cur_gpu_clk_index = setting_clock_step;
- printk("set cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
-
- return 0;
-}
-int mali_meson_init_start(struct platform_device* ptr_plt_dev)
-{
- struct mali_gpu_device_data* pdev = ptr_plt_dev->dev.platform_data;
-
-
- /* for resource data. */
- ptr_plt_dev->num_resources = ARRAY_SIZE(mali_gpu_resources);
- ptr_plt_dev->resource = mali_gpu_resources;
-
- /*for dvfs*/
-#ifndef CONFIG_MALI_DVFS
- /* for mali platform data. */
- pdev->control_interval = 200;
- pdev->utilization_callback = mali_gpu_utilization_callback;
-#else
- pdev->get_clock_info = meson_platform_get_clock_info;
- pdev->get_freq = meson_platform_get_freq;
- pdev->set_freq = meson_platform_set_freq;
-#endif
-
- return mali_clock_init(&mali_plat_data);
-}
-
-int mali_meson_init_finish(struct platform_device* ptr_plt_dev)
-{
-#ifndef CONFIG_MALI_DVFS
- if (mali_core_scaling_init(&mali_plat_data) < 0)
- return -1;
-#endif
- return 0;
-}
-
-int mali_meson_uninit(struct platform_device* ptr_plt_dev)
-{
- return 0;
-}
-
-static int mali_cri_light_suspend(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- mali_pm_statue = 1;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_suspend(device);
- }
- mali_pmu_power_down_all(pmu);
- return ret;
-}
-
-static int mali_cri_light_resume(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- mali_pmu_power_up_all(pmu);
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->runtime_resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->runtime_resume(device);
- }
- mali_pm_statue = 0;
- return ret;
-}
-
-static int mali_cri_deep_suspend(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->suspend)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->suspend(device);
- }
- mali_pmu_power_down_all(pmu);
- return ret;
-}
-
-static int mali_cri_deep_resume(size_t param)
-{
- int ret;
- struct device *device;
- struct mali_pmu_core *pmu;
-
- ret = 0;
- device = (struct device *)param;
- pmu = mali_pmu_get_global_pmu_core();
-
- mali_pmu_power_up_all(pmu);
- if (NULL != device->driver &&
- NULL != device->driver->pm &&
- NULL != device->driver->pm->resume)
- {
- /* Need to notify Mali driver about this event */
- ret = device->driver->pm->resume(device);
- }
- return ret;
-
-}
-
-int mali_light_suspend(struct device *device)
-{
- int ret = 0;
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- 0, 0, 0, 0, 0);
-#endif
-
- /* clock scaling. Kasin..*/
- ret = mali_clock_critical(mali_cri_light_suspend, (size_t)device);
- disable_clock();
- return ret;
-}
-
-int mali_light_resume(struct device *device)
-{
- int ret = 0;
- enable_clock();
- ret = mali_clock_critical(mali_cri_light_resume, (size_t)device);
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- get_current_frequency(), 0, 0, 0, 0);
-#endif
- return ret;
-}
-
-int mali_deep_suspend(struct device *device)
-{
- int ret = 0;
- struct mali_pmu_core *pmu;
-
- mali_pm_statue = 1;
- pmu = mali_pmu_get_global_pmu_core();
- enable_clock();
-#ifndef CONFIG_MALI_DVFS
- flush_scaling_job();
-#endif
-
- /* clock scaling off. Kasin... */
- ret = mali_clock_critical(mali_cri_deep_suspend, (size_t)device);
- disable_clock();
- return ret;
-}
-
-int mali_deep_resume(struct device *device)
-{
- int ret = 0;
-
- /* clock scaling up. Kasin.. */
- enable_clock();
- ret = mali_clock_critical(mali_cri_deep_resume, (size_t)device);
- mali_pm_statue = 0;
- return ret;
-}
-
-void mali_post_init(void)
-{
-#ifdef CONFIG_GPU_THERMAL
- int err;
- struct gpufreq_cooling_device *gcdev = NULL;
- struct gpucore_cooling_device *gccdev = NULL;
-
- gcdev = gpufreq_cooling_alloc();
- register_gpu_freq_info(get_current_frequency);
- if (IS_ERR(gcdev))
- printk("malloc gpu cooling buffer error!!\n");
- else if (!gcdev)
- printk("system does not enable thermal driver\n");
- else {
- gcdev->get_gpu_freq_level = get_mali_freq_level;
- gcdev->get_gpu_max_level = get_mali_max_level;
- gcdev->set_gpu_freq_idx = set_limit_mali_freq;
- gcdev->get_gpu_current_max_level = get_limit_mali_freq;
- err = gpufreq_cooling_register(gcdev);
- if (err < 0)
- printk("register GPU cooling error\n");
- printk("gpu cooling register okay with err=%d\n",err);
- }
-
- gccdev = gpucore_cooling_alloc();
- if (IS_ERR(gccdev))
- printk("malloc gpu core cooling buffer error!!\n");
- else if (!gccdev)
- printk("system does not enable thermal driver\n");
- else {
- gccdev->max_gpu_core_num=mali_plat_data.cfg_pp;
- gccdev->set_max_pp_num=set_limit_pp_num;
- err = (int)gpucore_cooling_register(gccdev);
- if (err < 0)
- printk("register GPU cooling error\n");
- printk("gpu core cooling register okay with err=%d\n",err);
- }
-#endif
-}
+++ /dev/null
-/*
- * Copyright (C) 2013 ARM Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
- *
- * A copy of the licence is included with the program, and can also be obtained from Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-/**
- * @file arm_core_scaling.c
- * Example core scaling policy.
- */
-
-#include <linux/version.h>
-#include <linux/module.h>
-#include <linux/workqueue.h>
-#include <linux/mali/mali_utgard.h>
-#include <mali_kernel_common.h>
-#include <mali_osk_profiling.h>
-
-#include <meson_main.h>
-
-#define LOG_MALI_SCALING 0
-
-
-static int currentStep;
-#ifndef CONFIG_MALI_DVFS
-static int num_cores_enabled;
-static int lastStep;
-static struct work_struct wq_work;
-static mali_plat_info_t* pmali_plat = NULL;
-#endif
-static int scaling_mode = MALI_PP_FS_SCALING;
-
-
-static unsigned scaling_dbg_level = 0;
-module_param(scaling_dbg_level, uint, 0644);
-MODULE_PARM_DESC(scaling_dbg_level , "scaling debug level");
-
-#define scalingdbg(level, fmt, arg...) \
- do { \
- if (scaling_dbg_level >= (level)) \
- printk(fmt , ## arg); \
- } while (0)
-
-#ifndef CONFIG_MALI_DVFS
-static void do_scaling(struct work_struct *work)
-{
- mali_dvfs_threshold_table * pdvfs = pmali_plat->dvfs_table;
- int err = mali_perf_set_num_pp_cores(num_cores_enabled);
- scalingdbg(1, "set pp cores to %d\n", num_cores_enabled);
- MALI_DEBUG_ASSERT(0 == err);
- MALI_IGNORE(err);
- if (pdvfs[currentStep].freq_index != pdvfs[lastStep].freq_index) {
- mali_dev_pause();
- mali_clock_set(pdvfs[currentStep].freq_index);
- mali_dev_resume();
- lastStep = currentStep;
- }
-#ifdef CONFIG_MALI400_PROFILING
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- get_current_frequency(),
- 0, 0, 0, 0);
-#endif
-}
-#endif
-
-u32 revise_set_clk(u32 val, u32 flush)
-{
- u32 ret = 0;
-#ifndef CONFIG_MALI_DVFS
- mali_scale_info_t* pinfo;
-
- pinfo = &pmali_plat->scale_info;
-
- if (val < pinfo->minclk)
- val = pinfo->minclk;
- else if (val > pinfo->maxclk)
- val = pinfo->maxclk;
-
- if (val != currentStep) {
- currentStep = val;
- if (flush)
- schedule_work(&wq_work);
- else
- ret = 1;
- }
-#endif
- return ret;
-}
-
-void get_mali_rt_clkpp(u32* clk, u32* pp)
-{
-#ifndef CONFIG_MALI_DVFS
- *clk = currentStep;
- *pp = num_cores_enabled;
-#endif
-}
-
-u32 set_mali_rt_clkpp(u32 clk, u32 pp, u32 flush)
-{
- u32 ret = 0;
-#ifndef CONFIG_MALI_DVFS
- mali_scale_info_t* pinfo;
- u32 flush_work = 0;
-
- pinfo = &pmali_plat->scale_info;
- if (clk < pinfo->minclk)
- clk = pinfo->minclk;
- else if (clk > pinfo->maxclk)
- clk = pinfo->maxclk;
-
- if (clk != currentStep) {
- currentStep = clk;
- if (flush)
- flush_work++;
- else
- ret = 1;
- }
- if (pp < pinfo->minpp)
- pp = pinfo->minpp;
- else if (pp > pinfo->maxpp)
- pp = pinfo->maxpp;
-
- if (pp != num_cores_enabled) {
- num_cores_enabled = pp;
- if (flush)
- flush_work++;
- else
- ret = 1;
- }
-
- if (flush_work)
- schedule_work(&wq_work);
-#endif
- return ret;
-}
-
-void revise_mali_rt(void)
-{
-#ifndef CONFIG_MALI_DVFS
- set_mali_rt_clkpp(currentStep, num_cores_enabled, 1);
-#endif
-}
-
-void flush_scaling_job(void)
-{
-#ifndef CONFIG_MALI_DVFS
- cancel_work_sync(&wq_work);
-#endif
-}
-
-#ifndef CONFIG_MALI_DVFS
-static u32 enable_one_core(void)
-{
- scalingdbg(2, "meson: one more pp, curent has %d pp cores\n", num_cores_enabled + 1);
- return set_mali_rt_clkpp(currentStep, num_cores_enabled + 1, 0);
-}
-
-static u32 disable_one_core(void)
-{
- scalingdbg(2, "meson: disable one pp, current has %d pp cores\n", num_cores_enabled - 1);
- return set_mali_rt_clkpp(currentStep, num_cores_enabled - 1, 0);
-}
-
-static u32 enable_max_num_cores(void)
-{
- return set_mali_rt_clkpp(currentStep, pmali_plat->scale_info.maxpp, 0);
-}
-
-static u32 enable_pp_cores(u32 val)
-{
- scalingdbg(2, "meson: enable %d pp cores\n", val);
- return set_mali_rt_clkpp(currentStep, val, 0);
-}
-#endif
-
-int mali_core_scaling_init(mali_plat_info_t *mali_plat)
-{
-#ifndef CONFIG_MALI_DVFS
- if (mali_plat == NULL) {
- scalingdbg(2, " Mali platform data is NULL!!!\n");
- return -1;
- }
-
- pmali_plat = mali_plat;
- num_cores_enabled = pmali_plat->sc_mpp;
-
- currentStep = pmali_plat->def_clock;
- lastStep = currentStep;
- INIT_WORK(&wq_work, do_scaling);
-#endif
- return 0;
- /* NOTE: Mali is not fully initialized at this point. */
-}
-
-void mali_core_scaling_term(void)
-{
-#ifndef CONFIG_MALI_DVFS
- flush_scheduled_work();
-#endif
-}
-
-#ifndef CONFIG_MALI_DVFS
-static u32 mali_threshold [] = {
- 102, /* 40% */
- 128, /* 50% */
- 230, /* 90% */
-};
-#endif
-
-void mali_pp_scaling_update(struct mali_gpu_utilization_data *data)
-{
-#ifndef CONFIG_MALI_DVFS
- int ret = 0;
-
- if (mali_threshold[2] < data->utilization_pp)
- ret = enable_max_num_cores();
- else if (mali_threshold[1]< data->utilization_pp)
- ret = enable_one_core();
- else if (0 < data->utilization_pp)
- ret = disable_one_core();
- if (ret == 1)
- schedule_work(&wq_work);
-#endif
-}
-
-#if LOG_MALI_SCALING
-void trace_utilization(struct mali_gpu_utilization_data *data, u32 current_idx, u32 next,
- u32 current_pp, u32 next_pp)
-{
- char direction;
- if (next > current_idx)
- direction = '>';
- else if ((current_idx > pmali_plat->scale_info.minpp) && (next < current_idx))
- direction = '<';
- else
- direction = '~';
-
- scalingdbg(2, "[SCALING]%c (%3d-->%3d)@%3d{%3d - %3d}. pp:(%d-->%d)\n",
- direction,
- get_mali_freq(current_idx),
- get_mali_freq(next),
- data->utilization_gpu,
- pmali_plat->dvfs_table[current_idx].downthreshold,
- pmali_plat->dvfs_table[current_idx].upthreshold,
- current_pp, next_pp);
-}
-#endif
-
-#ifndef CONFIG_MALI_DVFS
-static int mali_stay_count = 0;
-static void mali_decide_next_status(struct mali_gpu_utilization_data *data, int* next_fs_idx,
- int* pp_change_flag)
-{
- u32 utilization, mali_up_limit, decided_fs_idx;
- u32 ld_left, ld_right;
- u32 ld_up, ld_down;
- u32 change_mode;
-
- *pp_change_flag = 0;
- change_mode = 0;
- utilization = data->utilization_gpu;
-
- mali_up_limit = (scaling_mode == MALI_TURBO_MODE) ?
- pmali_plat->turbo_clock : pmali_plat->scale_info.maxclk;
- decided_fs_idx = currentStep;
-
- ld_up = pmali_plat->dvfs_table[currentStep].upthreshold;
- ld_down = pmali_plat->dvfs_table[currentStep].downthreshold;
-
- scalingdbg(2, "utilization=%d, ld_up=%d\n ", utilization, ld_up);
- if (utilization >= ld_up) { /* go up */
-
- scalingdbg(2, "currentStep=%d, mali_up_limit=%d\n ", currentStep, mali_up_limit);
- if (currentStep < mali_up_limit) {
- change_mode = 1;
- if ((currentStep < pmali_plat->def_clock) && (utilization > pmali_plat->bst_gpu))
- decided_fs_idx = pmali_plat->def_clock;
- else
- decided_fs_idx++;
- }
- if ((data->utilization_pp >= ld_up) &&
- (num_cores_enabled < pmali_plat->scale_info.maxpp)) {
- if ((num_cores_enabled < pmali_plat->sc_mpp) && (data->utilization_pp >= pmali_plat->bst_pp)) {
- *pp_change_flag = 1;
- change_mode = 1;
- } else if (change_mode == 0) {
- *pp_change_flag = 2;
- change_mode = 1;
- }
- }
-#if LOG_MALI_SCALING
- scalingdbg(2, "[nexting..] [LD:%d]-> FS[CRNT:%d LMT:%d NEXT:%d] PP[NUM:%d LMT:%d MD:%d][F:%d]\n",
- data->utilization_pp, currentStep, mali_up_limit, decided_fs_idx,
- num_cores_enabled, pmali_plat->scale_info.maxpp, *pp_change_flag, change_mode);
-#endif
- } else if (utilization <= ld_down) { /* go down */
- if (mali_stay_count > 0) {
- *next_fs_idx = decided_fs_idx;
- mali_stay_count--;
- return;
- }
-
- if (num_cores_enabled > pmali_plat->sc_mpp) {
- change_mode = 1;
- if (data->utilization_pp <= ld_down) {
- ld_left = data->utilization_pp * num_cores_enabled;
- ld_right = (pmali_plat->dvfs_table[currentStep].upthreshold) *
- (num_cores_enabled - 1);
- if (ld_left < ld_right) {
- change_mode = 2;
- }
- }
- } else if (currentStep > pmali_plat->scale_info.minclk) {
- change_mode = 1;
- } else if (num_cores_enabled > 1) { /* decrease PPS */
- if (data->utilization_pp <= ld_down) {
- ld_left = data->utilization_pp * num_cores_enabled;
- ld_right = (pmali_plat->dvfs_table[currentStep].upthreshold) *
- (num_cores_enabled - 1);
- scalingdbg(2, "ld_left=%d, ld_right=%d\n", ld_left, ld_right);
- if (ld_left < ld_right) {
- change_mode = 2;
- }
- }
- }
-
- if (change_mode == 1) {
- decided_fs_idx--;
- } else if (change_mode == 2) { /* decrease PPS */
- *pp_change_flag = -1;
- }
- }
- if (change_mode)
- mali_stay_count = pmali_plat->dvfs_table[decided_fs_idx].keep_count;
- *next_fs_idx = decided_fs_idx;
-}
-#endif
-
-void mali_pp_fs_scaling_update(struct mali_gpu_utilization_data *data)
-{
-#ifndef CONFIG_MALI_DVFS
- int ret = 0;
- int pp_change_flag = 0;
- u32 next_idx = 0;
-
-#if LOG_MALI_SCALING
- u32 last_pp = num_cores_enabled;
-#endif
- mali_decide_next_status(data, &next_idx, &pp_change_flag);
-
- if (pp_change_flag == 1)
- ret = enable_pp_cores(pmali_plat->sc_mpp);
- else if (pp_change_flag == 2)
- ret = enable_one_core();
- else if (pp_change_flag == -1) {
- ret = disable_one_core();
- }
-
-#if LOG_MALI_SCALING
- if (pp_change_flag || (next_idx != currentStep))
- trace_utilization(data, currentStep, next_idx, last_pp, num_cores_enabled);
-#endif
-
- if (next_idx != currentStep) {
- ret = 1;
- currentStep = next_idx;
- }
-
- if (ret == 1)
- schedule_work(&wq_work);
-#ifdef CONFIG_MALI400_PROFILING
- else
- _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
- MALI_PROFILING_EVENT_CHANNEL_GPU |
- MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
- get_current_frequency(),
- 0, 0, 0, 0);
-#endif
-#endif
-}
-
-u32 get_mali_schel_mode(void)
-{
- return scaling_mode;
-}
-
-void set_mali_schel_mode(u32 mode)
-{
-#ifndef CONFIG_MALI_DVFS
- MALI_DEBUG_ASSERT(mode < MALI_SCALING_MODE_MAX);
- if (mode >= MALI_SCALING_MODE_MAX)
- return;
- scaling_mode = mode;
-
- /* set default performance range. */
- pmali_plat->scale_info.minclk = pmali_plat->cfg_min_clock;
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- pmali_plat->scale_info.minpp = pmali_plat->cfg_min_pp;
- pmali_plat->scale_info.maxpp = pmali_plat->cfg_pp;
-
- /* set current status and tune max freq */
- if (scaling_mode == MALI_PP_FS_SCALING) {
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- enable_pp_cores(pmali_plat->sc_mpp);
- } else if (scaling_mode == MALI_SCALING_DISABLE) {
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- enable_max_num_cores();
- } else if (scaling_mode == MALI_TURBO_MODE) {
- pmali_plat->scale_info.maxclk = pmali_plat->turbo_clock;
- enable_max_num_cores();
- }
- currentStep = pmali_plat->scale_info.maxclk;
- schedule_work(&wq_work);
-#endif
-}
-
-u32 get_current_frequency(void)
-{
- return get_mali_freq(currentStep);
-}
-
-void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data)
-{
-#ifndef CONFIG_MALI_DVFS
- if (mali_pm_statue)
- return;
-
- switch (scaling_mode) {
- case MALI_PP_FS_SCALING:
- mali_pp_fs_scaling_update(data);
- break;
- case MALI_PP_SCALING:
- mali_pp_scaling_update(data);
- break;
- default:
- break;
- }
-#endif
-}
-
-void mali_dev_restore(void)
-{
-#ifndef CONFIG_MALI_DVFS
- mali_dvfs_threshold_table * pdvfs = pmali_plat->dvfs_table;
-
- //mali_perf_set_num_pp_cores(num_cores_enabled);
- mali_clock_set(pdvfs[currentStep].freq_index);
-#endif
-}
+++ /dev/null
-/*
- * Copyright (C) 2010, 2012-2013 ARM Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
- *
- * A copy of the licence is included with the program, and can also be obtained from Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-#include <linux/version.h>
-#include <linux/dma-mapping.h>
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/ioport.h>
-#include <linux/slab.h>
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/register.h>
-#include <mach/irqs.h>
-#include <mach/io.h>
-#endif
-#include <asm/io.h>
-
-#include "meson_main.h"
-#include <linux/mali/mali_utgard.h>
-#include "mali_kernel_common.h"
-#include "common/mali_pmu.h"
-#include "common/mali_osk_profiling.h"
-
-int mali_pm_statue = 0;
-u32 mali_gp_reset_fail = 0;
-module_param(mali_gp_reset_fail, int, S_IRUSR | S_IWUSR | S_IWGRP | S_IRGRP | S_IROTH); /* rw-rw-r-- */
-MODULE_PARM_DESC(mali_gp_reset_fail, "times of failed to reset GP");
-u32 mali_core_timeout = 0;
-module_param(mali_core_timeout, int, S_IRUSR | S_IWUSR | S_IWGRP | S_IRGRP | S_IROTH); /* rw-rw-r-- */
-MODULE_PARM_DESC(mali_core_timeout, "times of failed to reset GP");
-
-static struct mali_gpu_device_data mali_gpu_data =
-{
- .shared_mem_size = 1024 * 1024 * 1024,
- .max_job_runtime = 60000, /* 60 seconds */
- .pmu_switch_delay = 0xFFFF, /* do not have to be this high on FPGA, but it is good for testing to have a delay */
-#if defined(CONFIG_ARCH_MESON8B)||defined(CONFIG_ARCH_MESONG9BB)
- .pmu_domain_config = {0x1, 0x2, 0x4, 0x0,
- 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x1, 0x2, 0x0},
-#else
- .pmu_domain_config = {0x1, 0x2, 0x4, 0x4,
- 0x0, 0x8, 0x8, 0x8,
- 0x0, 0x1, 0x2, 0x8},
-#endif
-};
-
-static void mali_platform_device_release(struct device *device);
-static struct platform_device mali_gpu_device =
-{
- .name = MALI_GPU_NAME_UTGARD,
- .id = 0,
- .dev.release = mali_platform_device_release,
- .dev.coherent_dma_mask = DMA_BIT_MASK(32),
- .dev.platform_data = &mali_gpu_data,
- .dev.type = &mali_pm_device, /* We should probably use the pm_domain instead of type on newer kernels */
-};
-
-int mali_pdev_pre_init(struct platform_device* ptr_plt_dev)
-{
- MALI_DEBUG_PRINT(4, ("mali_platform_device_register() called\n"));
- if (mali_gpu_data.shared_mem_size < 10) {
- MALI_DEBUG_PRINT(2, ("mali os memory didn't configered, set to default(512M)\n"));
- mali_gpu_data.shared_mem_size = 1024 * 1024 *1024;
- }
- return mali_meson_init_start(ptr_plt_dev);
-}
-
-void mali_pdev_post_init(struct platform_device* pdev)
-{
- mali_gp_reset_fail = 0;
- mali_core_timeout = 0;
-#ifdef CONFIG_PM_RUNTIME
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
- pm_runtime_set_autosuspend_delay(&(pdev->dev), 1000);
- pm_runtime_use_autosuspend(&(pdev->dev));
-#endif
- pm_runtime_enable(&(pdev->dev));
-#endif
- mali_meson_init_finish(pdev);
-}
-
-int mali_pdev_dts_init(struct platform_device* mali_gpu_device)
-{
- struct device_node *cfg_node = mali_gpu_device->dev.of_node;
- struct device_node *child;
- u32 prop_value;
- int err;
-
- for_each_child_of_node(cfg_node, child) {
- err = of_property_read_u32(child, "shared_memory", &prop_value);
- if (err == 0) {
- MALI_DEBUG_PRINT(2, ("shared_memory configurate %d\n", prop_value));
- mali_gpu_data.shared_mem_size = prop_value * 1024 * 1024;
- }
- }
-
- err = mali_pdev_pre_init(mali_gpu_device);
- if (err == 0)
- mali_pdev_post_init(mali_gpu_device);
- return err;
-}
-
-int mali_platform_device_register(void)
-{
- int err = -1;
- err = mali_pdev_pre_init(&mali_gpu_device);
- if (err == 0) {
- err = platform_device_register(&mali_gpu_device);
- if (0 == err)
- mali_pdev_post_init(&mali_gpu_device);
- }
- return err;
-}
-
-void mali_platform_device_unregister(void)
-{
- MALI_DEBUG_PRINT(4, ("mali_platform_device_unregister() called\n"));
- mali_core_scaling_term();
- platform_device_unregister(&mali_gpu_device);
- platform_device_put(&mali_gpu_device);
-}
-
-static void mali_platform_device_release(struct device *device)
-{
- MALI_DEBUG_PRINT(4, ("mali_platform_device_release() called\n"));
-}
-
-
+++ /dev/null
-/*
- * mali_platform.h
- *
- * Created on: Nov 8, 2013
- * Author: amlogic
- */
-
-#ifndef MESON_MAIN_H_
-#define MESON_MAIN_H_
-#include <linux/version.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#ifdef CONFIG_PM_RUNTIME
-#include <linux/pm_runtime.h>
-#endif
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/cpu.h>
-#endif
-
-#include "mali_scaling.h"
-#include "mali_clock.h"
-
-extern struct device_type mali_pm_device;
-extern int mali_pm_statue;
-
-u32 set_max_mali_freq(u32 idx);
-u32 get_max_mali_freq(void);
-
-int mali_meson_init_start(struct platform_device* ptr_plt_dev);
-int mali_meson_init_finish(struct platform_device* ptr_plt_dev);
-int mali_meson_uninit(struct platform_device* ptr_plt_dev);
-int mali_light_suspend(struct device *device);
-int mali_light_resume(struct device *device);
-int mali_deep_suspend(struct device *device);
-int mali_deep_resume(struct device *device);
-
-#endif /* MESON_MAIN_H_ */
+++ /dev/null
-/*******************************************************************
- *
- * Copyright C 2013 by Amlogic, Inc. All Rights Reserved.
- *
- * Description:
- *
- * Author: Amlogic Software
- * Created: 2010/4/1 19:46
- *
- *******************************************************************/
-/* Standard Linux headers */
-#include <linux/platform_device.h>
-#include <linux/version.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/string.h>
-#include <linux/slab.h>
-#include <linux/list.h>
-
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29))
-#include <mach/io.h>
-#include <plat/io.h>
-#include <asm/io.h>
-#endif
-
-#include <linux/mali/mali_utgard.h>
-#include <common/mali_kernel_common.h>
-#include <common/mali_pmu.h>
-#include "mali_pp_scheduler.h"
-#include "meson_main.h"
-
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
-static ssize_t domain_stat_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
-#if 0
- unsigned int val;
-
- val = readl((u32 *)(IO_AOBUS_BASE + 0xf0)) & 0xff;
- return sprintf(buf, "%x\n", val>>4);
-#else
- return 0;
-#endif
-}
-
-#define PREHEAT_CMD "preheat"
-#define PLL2_CMD "mpl2" /* mpl2 [11] or [0xxxxxxx] */
-#define SCMPP_CMD "scmpp" /* scmpp [number of pp your want in most of time]. */
-#define BSTGPU_CMD "bstgpu" /* bstgpu [0-256] */
-#define BSTPP_CMD "bstpp" /* bstpp [0-256] */
-#define LIMIT_CMD "lmt" /* lmt [0 or 1] */
-#define MAX_TOKEN 20
-#define FULL_UTILIZATION 256
-
-static ssize_t mpgpu_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- char *pstart, *cprt = NULL;
- u32 val = 0;
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
-
- cprt = skip_spaces(buf);
- pstart = strsep(&cprt," ");
- if (strlen(pstart) < 1)
- goto quit;
-
- if(!strncmp(pstart, PREHEAT_CMD, MAX_TOKEN)) {
- if (pmali_plat->plat_preheat) {
- pmali_plat->plat_preheat();
- }
- } else if (!strncmp(pstart, PLL2_CMD, MAX_TOKEN)) {
- int base = 10;
- if ((strlen(cprt) > 2) && (cprt[0] == '0') &&
- (cprt[1] == 'x' || cprt[1] == 'X'))
- base = 16;
- if (kstrtouint(cprt, base, &val) <0)
- goto quit;
- if (val < 11)
- pmali_plat->cfg_clock = pmali_plat->cfg_clock_bkup;
- else
- pmali_plat->cfg_clock = pmali_plat->turbo_clock;
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- set_str_src(val);
- } else if (!strncmp(pstart, SCMPP_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
- if ((val > 0) && (val < pmali_plat->cfg_pp)) {
- pmali_plat->sc_mpp = val;
- }
- } else if (!strncmp(pstart, BSTGPU_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
- if ((val > 0) && (val < FULL_UTILIZATION)) {
- pmali_plat->bst_gpu = val;
- }
- } else if (!strncmp(pstart, BSTPP_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
- if ((val > 0) && (val < FULL_UTILIZATION)) {
- pmali_plat->bst_pp = val;
- }
- } else if (!strncmp(pstart, LIMIT_CMD, MAX_TOKEN)) {
- if ((kstrtouint(cprt, 10, &val) <0) || pmali_plat == NULL)
- goto quit;
-
- if (val < 2) {
- pmali_plat->limit_on = val;
- if (val == 0) {
- pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
- pmali_plat->scale_info.maxpp = pmali_plat->cfg_pp;
- revise_mali_rt();
- }
- }
- }
-quit:
- return count;
-}
-
-static ssize_t scale_mode_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- return sprintf(buf, "%d\n", get_mali_schel_mode());
-}
-
-static ssize_t scale_mode_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
-
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- {
- return -EINVAL;
- }
-
- set_mali_schel_mode(val);
-
- return count;
-}
-
-static ssize_t max_pp_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- printk("maxpp:%d, maxpp_sysfs:%d, total=%d\n",
- pmali_plat->scale_info.maxpp, pmali_plat->maxpp_sysfs,
- mali_pp_scheduler_get_num_cores_total());
- return sprintf(buf, "%d\n", mali_pp_scheduler_get_num_cores_total());
-}
-
-static ssize_t max_pp_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pmali_plat->cfg_pp) || (val < pinfo->minpp))
- return -EINVAL;
-
- pmali_plat->maxpp_sysfs = val;
- pinfo->maxpp = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t min_pp_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- return sprintf(buf, "%d\n", pmali_plat->scale_info.minpp);
-}
-
-static ssize_t min_pp_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pinfo->maxpp) || (val < 1))
- return -EINVAL;
-
- pinfo->minpp = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t max_freq_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- printk("maxclk:%d, maxclk_sys:%d, max gpu level=%d\n",
- pmali_plat->scale_info.maxclk, pmali_plat->maxclk_sysfs, get_gpu_max_clk_level());
- return sprintf(buf, "%d\n", get_gpu_max_clk_level());
-}
-
-static ssize_t max_freq_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pmali_plat->cfg_clock) || (val < pinfo->minclk))
- return -EINVAL;
-
- pmali_plat->maxclk_sysfs = val;
- pinfo->maxclk = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t min_freq_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- mali_plat_info_t* pmali_plat = get_mali_plat_data();
- return sprintf(buf, "%d\n", pmali_plat->scale_info.minclk);
-}
-
-static ssize_t min_freq_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- mali_plat_info_t* pmali_plat;
- mali_scale_info_t* pinfo;
-
- pmali_plat = get_mali_plat_data();
- pinfo = &pmali_plat->scale_info;
-
- ret = kstrtouint(buf, 10, &val);
- if ((0 != ret) || (val > pinfo->maxclk))
- return -EINVAL;
-
- pinfo->minclk = val;
- revise_mali_rt();
-
- return count;
-}
-
-static ssize_t freq_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- return sprintf(buf, "%d\n", get_current_frequency());
-}
-
-static ssize_t freq_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- u32 clk, pp;
- get_mali_rt_clkpp(&clk, &pp);
-
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- return -EINVAL;
-
- set_mali_rt_clkpp(val, pp, 1);
-
- return count;
-}
-
-static ssize_t current_pp_read(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- u32 clk, pp;
- get_mali_rt_clkpp(&clk, &pp);
- return sprintf(buf, "%d\n", pp);
-}
-
-static ssize_t current_pp_write(struct class *class,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned int val;
- u32 clk, pp;
-
- get_mali_rt_clkpp(&clk, &pp);
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- {
- return -EINVAL;
- }
-
- ret = kstrtouint(buf, 10, &val);
- if (0 != ret)
- return -EINVAL;
-
- set_mali_rt_clkpp(clk, val, 1);
-
- return count;
-}
-
-static struct class_attribute mali_class_attrs[] = {
- __ATTR(domain_stat, 0644, domain_stat_read, NULL),
- __ATTR(mpgpucmd, 0644, NULL, mpgpu_write),
- __ATTR(scale_mode, 0644, scale_mode_read, scale_mode_write),
- __ATTR(min_freq, 0644, min_freq_read, min_freq_write),
- __ATTR(max_freq, 0644, max_freq_read, max_freq_write),
- __ATTR(min_pp, 0644, min_pp_read, min_pp_write),
- __ATTR(max_pp, 0644, max_pp_read, max_pp_write),
- __ATTR(cur_freq, 0644, freq_read, freq_write),
- __ATTR(cur_pp, 0644, current_pp_read, current_pp_write),
-};
-
-static struct class mpgpu_class = {
- .name = "mpgpu",
-};
-#endif
-
-int mpgpu_class_init(void)
-{
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
- int ret = 0;
- int i;
- int attr_num = ARRAY_SIZE(mali_class_attrs);
-
- ret = class_register(&mpgpu_class);
- if (ret) {
- printk(KERN_ERR "%s: class_register failed\n", __func__);
- return ret;
- }
- for (i = 0; i< attr_num; i++) {
- ret = class_create_file(&mpgpu_class, &mali_class_attrs[i]);
- if (ret) {
- printk(KERN_ERR "%d ST: class item failed to register\n", i);
- }
- }
- return ret;
-#else
- return 0;
-#endif
-}
-
-void mpgpu_class_exit(void)
-{
-#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
- class_unregister(&mpgpu_class);
-#endif
-}
-
projects / GitHub / LineageOS / G12 / android_hardware_amlogic_kernel-modules_mali-driver.git / commitdiff