drm/rockchip: analogix_dp: introduce the pclk for grf

For RK3399's GRF module, if we want to operate the graphic related grf
registers, we need to enable the pclk_vio_grf which supply power for VIO
GRF IOs, so it's better to introduce an optional grf clock in driver.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Tomasz Figa <tomasz.figa@chromium.com>

diff --git a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
index 726c94502a2a0b6a9ff7c154828b60c96b95aa71..0b39256c00aefb0024841accf0f33c03c774d961 100644 (file)
--- a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
@@ -28,6 +28,12 @@ Required properties:
     Port 0: contained 2 endpoints, connecting to the output of vop.
     Port 1: contained 1 endpoint, connecting to the input of panel.
 
+Optional property for different chips:
+- clocks: from common clock binding: handle to grf_vio clock.
+
+- clock-names: from common clock binding:
+              Required elements: "grf"
+
 For the below properties, please refer to Analogix DP binding document:
  * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
 - phys (required)

diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 850edc4d99c8cd1a84abb632d4b236a5a88d9070..e81e19a660adcbd10736a01ab89934c4b06e0bae 100644 (file)
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -64,6 +64,7 @@ struct rockchip_dp_device {
        struct drm_display_mode  mode;
 
        struct clk               *pclk;
+       struct clk               *grfclk;
        struct regmap            *grf;
        struct reset_control     *rst;
 
@@ -160,11 +161,17 @@ static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder)
 
        dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
 
-       ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);
-       if (ret != 0) {
-               dev_err(dp->dev, "Could not write to GRF: %d\n", ret);
+       ret = clk_prepare_enable(dp->grfclk);
+       if (ret < 0) {
+               dev_err(dp->dev, "failed to enable grfclk %d\n", ret);
                return;
        }
+
+       ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);
+       if (ret != 0)
+               dev_err(dp->dev, "Could not write to GRF: %d\n", ret);
+
+       clk_disable_unprepare(dp->grfclk);
 }
 
 static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder)
@@ -234,6 +241,16 @@ static int rockchip_dp_init(struct rockchip_dp_device *dp)
                return PTR_ERR(dp->grf);
        }
 
+       dp->grfclk = devm_clk_get(dev, "grf");
+       if (PTR_ERR(dp->grfclk) == -ENOENT) {
+               dp->grfclk = NULL;
+       } else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) {
+               return -EPROBE_DEFER;
+       } else if (IS_ERR(dp->grfclk)) {
+               dev_err(dev, "failed to get grf clock\n");
+               return PTR_ERR(dp->grfclk);
+       }
+
        dp->pclk = devm_clk_get(dev, "pclk");
        if (IS_ERR(dp->pclk)) {
                dev_err(dev, "failed to get pclk property\n");