drm/amdgpu: Fix the exported always on CU bitmap
authorFlora Cui <Flora.Cui@amd.com>
Tue, 20 Jun 2017 03:08:35 +0000 (11:08 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 29 Jun 2017 16:43:49 +0000 (12:43 -0400)
Newer asics with 4 SEs are not able to fit the entire bitmask in the
original field, use an array instead.

v2: keep cu_ao_mask for backward compatibility.

Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
include/uapi/drm/amdgpu_drm.h

index 12d61edb3597f42f338bb51f5282268b0a053ed2..ea8242e6a2f2861ca1c3d394b0a56346d578471f 100644 (file)
@@ -1028,12 +1028,15 @@ struct amdgpu_gfx_config {
 };
 
 struct amdgpu_cu_info {
-       uint32_t number; /* total active CU number */
-       uint32_t ao_cu_mask;
        uint32_t max_waves_per_simd;
        uint32_t wave_front_size;
        uint32_t max_scratch_slots_per_cu;
        uint32_t lds_size;
+
+       /* total active CU number */
+       uint32_t number;
+       uint32_t ao_cu_mask;
+       uint32_t ao_cu_bitmap[4][4];
        uint32_t bitmap[4][4];
 };
 
index 3e5d550c5bd05e85f294a57d26802cb03e1fec10..aef43b5334afa90709f0a1533211baba065ff4e0 100644 (file)
  * - 3.15.0 - Export more gpu info for gfx9
  * - 3.16.0 - Add reserved vmid support
  * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
+ * - 3.18.0 - Export gpu always on cu bitmap
  */
 #define KMS_DRIVER_MAJOR       3
-#define KMS_DRIVER_MINOR       17
+#define KMS_DRIVER_MINOR       18
 #define KMS_DRIVER_PATCHLEVEL  0
 
 int amdgpu_vram_limit = 0;
index 12497a40ef9284d0386816940dbb934b64743ef7..b0b23101d1c870ddeefc89b15818cd5b13ea13a7 100644 (file)
@@ -594,6 +594,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
                dev_info.cu_active_number = adev->gfx.cu_info.number;
                dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
                dev_info.ce_ram_size = adev->gfx.ce_ram_size;
+               memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
+                      sizeof(adev->gfx.cu_info.ao_cu_bitmap));
                memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
                       sizeof(adev->gfx.cu_info.bitmap));
                dev_info.vram_type = adev->mc.vram_type;
index 7b0b3cf163344fb833c6cdb38944f70876b38449..5173ca1fd159d19971ace8cf87bafb8749a75bbf 100644 (file)
@@ -3535,7 +3535,9 @@ static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
                                mask <<= 1;
                        }
                        active_cu_number += counter;
-                       ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
+                       if (i < 2 && j < 2)
+                               ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
+                       cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
                }
        }
 
index ec754288f1469ee845b809ce024903d7b4ada570..37b45e4403d175229855c167218ceeeaa627180b 100644 (file)
@@ -5427,7 +5427,9 @@ static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
                                mask <<= 1;
                        }
                        active_cu_number += counter;
-                       ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
+                       if (i < 2 && j < 2)
+                               ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
+                       cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
                }
        }
        gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
index 9a268272d38e6cac8a271f452093901b93d3c94b..a1ef7f6307b9105ca19aa283b2e50c3d95ddb21d 100644 (file)
@@ -7087,7 +7087,9 @@ static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev)
                                mask <<= 1;
                        }
                        active_cu_number += counter;
-                       ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
+                       if (i < 2 && j < 2)
+                               ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
+                       cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
                }
        }
        gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
index 209bf0188e06788d96ad9b997257e6fafc5cd262..2e6f203fab9eba3495e466289a3494b751af78fd 100644 (file)
@@ -4459,7 +4459,9 @@ static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
                                mask <<= 1;
                        }
                        active_cu_number += counter;
-                       ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
+                       if (i < 2 && j < 2)
+                               ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
+                       cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
                }
        }
        gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
index d9aa4a339650fafa122f14148b9f0250ecfe536f..7b8fa11c2285b628f0805916b8c46de992dbb56e 100644 (file)
@@ -764,6 +764,7 @@ struct drm_amdgpu_info_device {
        __u64 max_memory_clock;
        /* cu information */
        __u32 cu_active_number;
+       /* NOTE: cu_ao_mask is INVALID, DON'T use it */
        __u32 cu_ao_mask;
        __u32 cu_bitmap[4][4];
        /** Render backend pipe mask. One render backend is CB+DB. */
@@ -818,6 +819,8 @@ struct drm_amdgpu_info_device {
        /* max gs wavefront per vgt*/
        __u32 max_gs_waves_per_vgt;
        __u32 _pad1;
+       /* always on cu bitmap */
+       __u32 cu_ao_bitmap[4][4];
 };
 
 struct drm_amdgpu_info_hw_ip {