clk: keystone: use clkod register bits for postdiv

DDR3A/B, ARM and PA PLL controllers have clkod register bits for
configuring postdiv values. So use it instead of using fixed
post dividers for these pll controllers. Assume that if fixed-postdiv
attribute is not present, use clkod register value for pistdiv.

Also update the Documentation of bindings to reflect the same.

Cc: Mike Turquette <mturquette@linaro.org
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>

diff --git a/Documentation/devicetree/bindings/clock/keystone-pll.txt b/Documentation/devicetree/bindings/clock/keystone-pll.txt
index 12bd72605a31b10cfd44b9d46eeff65199cc7e15..225990f79b7c577f50594cec23e1abb889bc5502 100644 (file)
--- a/Documentation/devicetree/bindings/clock/keystone-pll.txt
+++ b/Documentation/devicetree/bindings/clock/keystone-pll.txt
@@ -17,13 +17,14 @@ Required properties:
 - reg - pll control0 and pll multipler registers
 - reg-names : control and multiplier. The multiplier is applicable only for
                main pll clock
-- fixed-postdiv : fixed post divider value
+- fixed-postdiv : fixed post divider value. If absent, use clkod register bits
+               for postdiv
 
 Example:
        mainpllclk: mainpllclk@2310110 {
                #clock-cells = <0>;
                compatible = "ti,keystone,main-pll-clock";
-               clocks = <&refclkmain>;
+               clocks = <&refclksys>;
                reg = <0x02620350 4>, <0x02310110 4>;
                reg-names = "control", "multiplier";
                fixed-postdiv = <2>;
@@ -32,11 +33,10 @@ Example:
        papllclk: papllclk@2620358 {
                #clock-cells = <0>;
                compatible = "ti,keystone,pll-clock";
-               clocks = <&refclkmain>;
+               clocks = <&refclkpass>;
                clock-output-names = "pa-pll-clk";
                reg = <0x02620358 4>;
                reg-names = "control";
-               fixed-postdiv = <6>;
        };
 
 Required properties:

diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c
index 47a1bd9f1726574d61fca85691d2913a7ee353b4..0dd8a4b12747b6df0ce1c88f34aaf28781fe85f8 100644 (file)
--- a/drivers/clk/keystone/pll.c
+++ b/drivers/clk/keystone/pll.c
@@ -24,6 +24,8 @@
 #define MAIN_PLLM_HIGH_MASK    0x7f000
 #define PLLM_HIGH_SHIFT                6
 #define PLLD_MASK              0x3f
+#define CLKOD_MASK             0x780000
+#define CLKOD_SHIFT            19
 
 /**
  * struct clk_pll_data - pll data structure
@@ -41,7 +43,10 @@
  * @pllm_upper_mask: multiplier upper mask
  * @pllm_upper_shift: multiplier upper shift
  * @plld_mask: divider mask
- * @postdiv: Post divider
+ * @clkod_mask: output divider mask
+ * @clkod_shift: output divider shift
+ * @plld_mask: divider mask
+ * @postdiv: Fixed post divider
  */
 struct clk_pll_data {
        bool has_pllctrl;
@@ -53,6 +58,8 @@ struct clk_pll_data {
        u32 pllm_upper_mask;
        u32 pllm_upper_shift;
        u32 plld_mask;
+       u32 clkod_mask;
+       u32 clkod_shift;
        u32 postdiv;
 };
 
@@ -90,7 +97,13 @@ static unsigned long clk_pllclk_recalc(struct clk_hw *hw,
        mult |= ((val & pll_data->pllm_upper_mask)
                        >> pll_data->pllm_upper_shift);
        prediv = (val & pll_data->plld_mask);
-       postdiv = pll_data->postdiv;
+
+       if (!pll_data->has_pllctrl)
+               /* read post divider from od bits*/
+               postdiv = ((val & pll_data->clkod_mask) >>
+                                pll_data->clkod_shift) + 1;
+       else
+               postdiv = pll_data->postdiv;
 
        rate /= (prediv + 1);
        rate = (rate * (mult + 1));
@@ -155,8 +168,11 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl)
        }
 
        parent_name = of_clk_get_parent_name(node, 0);
-       if (of_property_read_u32(node, "fixed-postdiv", &pll_data->postdiv))
-               goto out;
+       if (of_property_read_u32(node, "fixed-postdiv", &pll_data->postdiv)) {
+               /* assume the PLL has output divider register bits */
+               pll_data->clkod_mask = CLKOD_MASK;
+               pll_data->clkod_shift = CLKOD_SHIFT;
+       }
 
        i = of_property_match_string(node, "reg-names", "control");
        pll_data->pll_ctl0 = of_iomap(node, i);