ath9k: fix RF channel frequency configuration for AR9550
authorGabor Juhos <juhosg@openwrt.org>
Tue, 3 Jul 2012 17:13:28 +0000 (19:13 +0200)
committerJohn W. Linville <linville@tuxdriver.com>
Mon, 9 Jul 2012 20:36:30 +0000 (16:36 -0400)
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath/ath9k/ar9003_phy.c

index 70ada2e6c61d42d128d88ded8bc25bca93d715aa..d2346dbad6cd5cd56c76511e1ae3ed9d738aa214 100644 (file)
@@ -99,7 +99,7 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
                        channelSel = (freq * 4) / 120;
                        chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
                        channelSel = (channelSel << 17) | chan_frac;
-               } else if (AR_SREV_9340(ah)) {
+               } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
                        if (ah->is_clk_25mhz) {
                                u32 chan_frac;
 
@@ -113,7 +113,8 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
                /* Set to 2G mode */
                bMode = 1;
        } else {
-               if (AR_SREV_9340(ah) && ah->is_clk_25mhz) {
+               if ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) &&
+                   ah->is_clk_25mhz) {
                        u32 chan_frac;
 
                        channelSel = (freq * 2) / 75;