[Blackfin] serial driver: Add flow control support to bf54x
authorSonic Zhang <sonic.zhang@analog.com>
Sat, 2 Feb 2008 09:05:02 +0000 (17:05 +0800)
committerBryan Wu <cooloney@kernel.org>
Sat, 2 Feb 2008 09:05:02 +0000 (17:05 +0800)
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
drivers/serial/Kconfig
drivers/serial/bfin_5xx.c
include/asm-blackfin/mach-bf548/bfin_serial_5xx.h

index 202fb5c99b8335881d349dfcf8c277e89835ac87..cf627cd1b4c8f27e028649e97091a5b06e375e5c 100644 (file)
@@ -699,14 +699,14 @@ config BFIN_UART1_CTSRTS
 
 config UART1_CTS_PIN
        int "UART1 CTS pin"
-       depends on BFIN_UART1_CTSRTS && (BF53x || BF561)
+       depends on BFIN_UART1_CTSRTS && !BF54x
        default -1
        help
          Refer to ./include/asm-blackfin/gpio.h to see the GPIO map.
 
 config UART1_RTS_PIN
        int "UART1 RTS pin"
-       depends on BFIN_UART1_CTSRTS && (BF53x || BF561)
+       depends on BFIN_UART1_CTSRTS && !BF54x
        default -1
        help
          Refer to ./include/asm-blackfin/gpio.h to see the GPIO map.
index af866ab3f5a1611264b633abe6c60036a0aef355..69ac7007682e09a5abd797899b7200d7cd6c58a4 100644 (file)
@@ -579,7 +579,11 @@ static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
        if (uart->cts_pin < 0)
                return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
 
+# ifdef BF54x
+       if (UART_GET_MSR(uart) & CTS)
+# else
        if (gpio_get_value(uart->cts_pin))
+# endif
                return TIOCM_DSR | TIOCM_CAR;
        else
 #endif
@@ -594,9 +598,17 @@ static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
                return;
 
        if (mctrl & TIOCM_RTS)
+# ifdef BF54x
+               UART_PUT_MCR(uart, UART_GET_MCR(uart) & ~MRTS);
+# else
                gpio_set_value(uart->rts_pin, 0);
+# endif
        else
+# ifdef BF54x
+               UART_PUT_MCR(uart, UART_GET_MCR(uart) | MRTS);
+# else
                gpio_set_value(uart->rts_pin, 1);
+# endif
 #endif
 }
 
index c459c48464699690f5a996a2a207554c6eac43ee..7e6339f62a5058ae5e4226fef033c9985968f96e 100644 (file)
@@ -24,6 +24,8 @@
 #define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
 #define UART_GET_LSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LSR))
 #define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
+#define UART_GET_MSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_MSR))
+#define UART_GET_MCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_MCR))
 
 #define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
 #define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
@@ -34,6 +36,7 @@
 #define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
 #define UART_CLEAR_LSR(uart)    bfin_write16(((uart)->port.membase + OFFSET_LSR), -1)
 #define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
+#define UART_PUT_MCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_MCR),v)
 
 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
 # define CONFIG_SERIAL_BFIN_CTSRTS