cfg->val = ufshcd_readl(hba, cfg->offset);
else if (sel_api == LOG_VS_HCI_SFR)
cfg->val = hci_readl(ufs, cfg->offset);
-// else if (sel_api == LOG_FMP_SFR)
-// cfg->val = exynos_smc(SMC_CMD_FMP_DUMP, 0, 0, cfg->offset);
+ else if (sel_api == LOG_FMP_SFR)
+ cfg->val = exynos_smc(SMC_CMD_FMP_SMU_DUMP, 0, 0, cfg->offset);
else if (sel_api == LOG_UNIPRO_SFR)
cfg->val = unipro_readl(ufs, cfg->offset);
else if (sel_api == LOG_PMA_SFR)
{
struct exynos_ufs *ufs = to_exynos_ufs(hba);
-// /* secure log */
-// exynos_smc(SMC_CMD_UFS_LOG, 1, 0, hba->secure_log.paddr);
+ /* secure log */
+ exynos_smc(SMC_CMD_UFS_LOG, 1, 0, hba->secure_log.paddr);
exynos_ufs_get_sfr(hba, ufs->debug.sfr);
exynos_ufs_get_attr(hba, ufs->debug.attr);
list_add_tail(&exynos_clki->list, &ufs->debug.misc.clk_list_head);
}
-// hba->secure_log.paddr = exynos_ss_get_spare_paddr(0);
-// hba->secure_log.vaddr = (u32 *)exynos_ss_get_spare_vaddr(0);
+ hba->secure_log.paddr = exynos_ss_get_spare_paddr(0);
+ hba->secure_log.vaddr = (u32 *)exynos_ss_get_spare_vaddr(0);
return 0;
}
exynos_ufs_dev_hw_reset(hba);
/* secure log */
-// exynos_smc(SMC_CMD_LOG, 0, 0, 2);
+ exynos_smc(SMC_CMD_UFS_LOG, 0, 0, 0);
out:
return;
}
exynos_ufs_smu_resume(ufs);
/* secure log */
-// exynos_smc(SMC_CMD_LOG, 0, 0, 2);
+ exynos_smc(SMC_CMD_UFS_LOG, 0, 0, 0);
if (ufshcd_is_clkgating_allowed(hba))
clk_disable_unprepare(ufs->clk_hci);
hba = shost_priv(host);
tag = cmd->request->tag;
+ /* secure log */
+ exynos_smc(SMC_CMD_UFS_LOG, 1, 0, hba->secure_log.paddr);
+
/* Dump debugging information to system memory */
ufshcd_vops_dbg_register_dump(hba);
exynos_ufs_show_uic_info(hba);
if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN)
return ufshcd_eh_host_reset_handler(cmd);
+ /* secure log */
+ exynos_smc(SMC_CMD_UFS_LOG, 1, 0, hba->secure_log.paddr);
if (cmd->cmnd[0] == READ_10 || cmd->cmnd[0] == WRITE_10) {
unsigned long lba = (cmd->cmnd[2] << 24) |