bnx2x: Fix link for KR with swapped polarity lane
authorYaniv Rosner <yaniv.rosner@qlogic.com>
Thu, 12 Jun 2014 04:55:29 +0000 (07:55 +0300)
committerDavid S. Miller <davem@davemloft.net>
Thu, 12 Jun 2014 17:28:18 +0000 (10:28 -0700)
This avoids clearing the RX polarity setting in KR mode when polarity lane
is swapped, as otherwise this will result in failed link.

Signed-off-by: Yaniv Rosner <yaniv.rosner@qlogic.com>
Signed-off-by: Yuval Mintz <yuval.mintz@qlogic.com>
Signed-off-by: Ariel Elior <ariel.elior@qlogic.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

index 4fef1e19936648240ebffd32042149da36312dbf..592a8a4ec9c9791f903bf03287f8de003d2fa9fe 100644 (file)
@@ -3702,7 +3702,8 @@ static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy,
 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
                                        struct link_params *params,
                                        struct link_vars *vars) {
-       u16 lane, i, cl72_ctrl, an_adv = 0;
+       u16 lane, i, cl72_ctrl, an_adv = 0, val;
+       u32 wc_lane_config;
        struct bnx2x *bp = params->bp;
        static struct bnx2x_reg_set reg_set[] = {
                {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
@@ -3821,15 +3822,27 @@ static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
                /* Enable Auto-Detect to support 1G over CL37 as well */
                bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
                                 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10);
-
+               wc_lane_config = REG_RD(bp, params->shmem_base +
+                                       offsetof(struct shmem_region, dev_info.
+                                       shared_hw_config.wc_lane_config));
+               bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
+                               MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val);
                /* Force cl48 sync_status LOW to avoid getting stuck in CL73
                 * parallel-detect loop when CL73 and CL37 are enabled.
                 */
-               CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
-                                 MDIO_AER_BLOCK_AER_REG, 0);
+               val |= 1 << 11;
+
+               /* Restore Polarity settings in case it was run over by
+                * previous link owner
+                */
+               if (wc_lane_config &
+                   (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane))
+                       val |= 3 << 2;
+               else
+                       val &= ~(3 << 2);
                bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
-                                MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI, 0x0800);
-               bnx2x_set_aer_mmd(params, phy);
+                                MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4),
+                                val);
 
                bnx2x_disable_kr2(params, vars, phy);
        }