pinctrl: samsung: Move retention control from mach-s5pv210 to the pinctrl driver

This patch moves pad retention control from S5PV210 machine code to
Exynos pin controller driver. This helps to avoid possible ordering
and logical dependencies between machine and pin control code. Till
now it worked fine only because sys_ops for machine code and pin
controller were called in registration order.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
For mach-s5pv210:
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
index 21b4b13c5ab787f0707c00c5125b285f73dcdd60..7d69666de5ba2dd6b3c5c705d608ba4ad182767b 100644 (file)
--- a/arch/arm/mach-s5pv210/pm.c
+++ b/arch/arm/mach-s5pv210/pm.c
@@ -155,13 +155,6 @@ static const struct platform_suspend_ops s5pv210_suspend_ops = {
  */
 static void s5pv210_pm_resume(void)
 {
-       u32 tmp;
-
-       tmp = __raw_readl(S5P_OTHERS);
-       tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF |\
-               S5P_OTHERS_RET_MMC | S5P_OTHERS_RET_UART);
-       __raw_writel(tmp , S5P_OTHERS);
-
        s3c_pm_do_restore_core(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save));
 }
 

diff --git a/arch/arm/mach-s5pv210/regs-clock.h b/arch/arm/mach-s5pv210/regs-clock.h
index 4640f0f03c12ccaaf01b8fb5f72690a6f0eb01a9..fb3eb77412dbdf2d6321bfe278c81970631aab72 100644 (file)
--- a/arch/arm/mach-s5pv210/regs-clock.h
+++ b/arch/arm/mach-s5pv210/regs-clock.h
@@ -188,10 +188,6 @@
 #define S5P_SLEEP_CFG_USBOSC_EN                (1 << 1)
 
 /* OTHERS Resgister */
-#define S5P_OTHERS_RET_IO              (1 << 31)
-#define S5P_OTHERS_RET_CF              (1 << 30)
-#define S5P_OTHERS_RET_MMC             (1 << 29)
-#define S5P_OTHERS_RET_UART            (1 << 28)
 #define S5P_OTHERS_USB_SIG_MASK                (1 << 16)
 
 /* S5P_DAC_CONTROL */

diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index c81df3c843c3f485a26bbc48c3de6d921d08d1f4..f16f52ab4912fd92fb0110cae037589a0ab250a6 100644 (file)
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -24,6 +24,7 @@
 #include <linux/irqdomain.h>
 #include <linux/irq.h>
 #include <linux/irqchip/chained_irq.h>
+#include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/io.h>
 #include <linux/slab.h>
@@ -632,6 +633,60 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
                        exynos_pinctrl_resume_bank(drvdata, bank);
 }
 
+/* Retention control for S5PV210 are located at the end of clock controller */
+#define S5P_OTHERS 0xE000
+
+#define S5P_OTHERS_RET_IO              (1 << 31)
+#define S5P_OTHERS_RET_CF              (1 << 30)
+#define S5P_OTHERS_RET_MMC             (1 << 29)
+#define S5P_OTHERS_RET_UART            (1 << 28)
+
+static void s5pv210_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
+{
+       void *clk_base = drvdata->retention_ctrl->priv;
+       u32 tmp;
+
+       tmp = __raw_readl(clk_base + S5P_OTHERS);
+       tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF | S5P_OTHERS_RET_MMC |
+               S5P_OTHERS_RET_UART);
+       __raw_writel(tmp, clk_base + S5P_OTHERS);
+}
+
+static struct samsung_retention_ctrl *
+s5pv210_retention_init(struct samsung_pinctrl_drv_data *drvdata,
+                      const struct samsung_retention_data *data)
+{
+       struct samsung_retention_ctrl *ctrl;
+       struct device_node *np;
+       void *clk_base;
+
+       ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL);
+       if (!ctrl)
+               return ERR_PTR(-ENOMEM);
+
+       np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock");
+       if (!np) {
+               pr_err("%s: failed to find clock controller DT node\n",
+                       __func__);
+               return ERR_PTR(-ENODEV);
+       }
+
+       clk_base = of_iomap(np, 0);
+       if (!clk_base) {
+               pr_err("%s: failed to map clock registers\n", __func__);
+               return ERR_PTR(-EINVAL);
+       }
+
+       ctrl->priv = clk_base;
+       ctrl->disable = s5pv210_retention_disable;
+
+       return ctrl;
+}
+
+static const struct samsung_retention_data s5pv210_retention_data __initconst = {
+       .init    = s5pv210_retention_init,
+};
+
 /* pin banks of s5pv210 pin-controller */
 static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = {
        EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
@@ -679,6 +734,7 @@ const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = {
                .eint_wkup_init = exynos_eint_wkup_init,
                .suspend        = exynos_pinctrl_suspend,
                .resume         = exynos_pinctrl_resume,
+               .retention_data = &s5pv210_retention_data,
        },
 };