ARM: dts: r8a7794: Add DU1 clock to device tree
authorGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 28 Mar 2017 10:45:30 +0000 (12:45 +0200)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 22 Mar 2018 08:17:44 +0000 (09:17 +0100)
commit 1764f8081f1524bf629e0744b277db751281ff56 upstream.

Add the missing module clock for the second channel of the display unit.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arch/arm/boot/dts/r8a7794.dtsi
include/dt-bindings/clock/r8a7794-clock.h

index 6c0150dcf146fe33d6680addeaa4482bc2c7af1a..1d65dd0a3f939a720156bfd1ec4450d3e8904be0 100644 (file)
                        clocks = <&mp_clk>, <&hp_clk>,
                                 <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
                                 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
-                                <&zx_clk>;
+                                <&zx_clk>, <&zx_clk>;
                        #clock-cells = <1>;
                        clock-indices = <
                                R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
                                R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
                                R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
                                R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
-                               R8A7794_CLK_SCIF0 R8A7794_CLK_DU0
+                               R8A7794_CLK_SCIF0
+                               R8A7794_CLK_DU1 R8A7794_CLK_DU0
                        >;
                        clock-output-names =
                                "ehci", "hsusb",
                                "hscif2", "scif5", "scif4", "hscif1", "hscif0",
-                               "scif3", "scif2", "scif1", "scif0", "du0";
+                               "scif3", "scif2", "scif1", "scif0",
+                               "du1", "du0";
                };
                mstp8_clks: mstp8_clks@e6150990 {
                        compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
index 88e64846cf370ff4a32c8423b5d00833c8cb5a81..cdeafd9cab07c60460885297f530cf9c965aeb8c 100644 (file)
@@ -81,6 +81,7 @@
 #define R8A7794_CLK_SCIF2              19
 #define R8A7794_CLK_SCIF1              20
 #define R8A7794_CLK_SCIF0              21
+#define R8A7794_CLK_DU1                        23
 #define R8A7794_CLK_DU0                        24
 
 /* MSTP8 */