wireless: Remove unnecessary ; from while (0) macros
authorJoe Perches <joe@perches.com>
Tue, 3 Apr 2012 21:46:49 +0000 (14:46 -0700)
committerJohn W. Linville <linville@tuxdriver.com>
Wed, 11 Apr 2012 20:23:56 +0000 (16:23 -0400)
Semicolons are not necessary after macros that end in while (0).
Remove them.

Simplify the macros with tests of
do { if (foo>size) memset1; else memset2;} while (0);
to a single line memset(,,min_t(size_t, foo, size))

Signed-off-by: Joe Perches <joe@perches.com>
Acked-by: Arend van Spriel <arend@broadcom.com>
Acked-by: Larry Finger <Larry.Finger@lwfinger.net>
Acked-by: Bing Zhao <bzhao@marvell.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath/carl9170/cmd.h
drivers/net/wireless/brcm80211/brcmsmac/d11.h
drivers/net/wireless/mwifiex/sdio.h
drivers/net/wireless/rtlwifi/rtl8192ce/trx.h
drivers/net/wireless/rtlwifi/rtl8192de/trx.h
drivers/net/wireless/rtlwifi/rtl8192se/def.h
drivers/net/wireless/rtlwifi/rtl8192se/fw.h

index 885c42778b8b5817941c9c184904446cc91834fe..65919c902f55ac01d89869d6174433a6d74662e3 100644 (file)
@@ -114,7 +114,7 @@ __regwrite_out :                                                    \
 
 #define carl9170_regwrite_result()                                     \
        __err;                                                          \
-} while (0);
+} while (0)
 
 
 #define carl9170_async_regwrite_get_buf()                              \
@@ -126,7 +126,7 @@ do {                                                                        \
                __err = -ENOMEM;                                        \
                goto __async_regwrite_out;                              \
        }                                                               \
-} while (0);
+} while (0)
 
 #define carl9170_async_regwrite_begin(carl)                            \
 do {                                                                   \
@@ -169,6 +169,6 @@ __async_regwrite_out:                                                       \
 
 #define carl9170_async_regwrite_result()                               \
        __err;                                                          \
-} while (0);
+} while (0)
 
 #endif /* __CMD_H */
index 1948cb2771e9a8687b8860ba6269456215d2f07e..3f659e09f1cc3fd9656dcf9fc6a0c5ee1f4ea333 100644 (file)
@@ -733,7 +733,7 @@ struct cck_phy_hdr {
        do { \
                plcp[1] = len & 0xff; \
                plcp[2] = ((len >> 8) & 0xff); \
-       } while (0);
+       } while (0)
 
 #define BRCMS_SET_MIMO_PLCP_AMPDU(plcp) (plcp[3] |= MIMO_PLCP_AMPDU)
 #define BRCMS_CLR_MIMO_PLCP_AMPDU(plcp) (plcp[3] &= ~MIMO_PLCP_AMPDU)
index a3fb322205b0a69c295049cecb94c6522ea4b768..0ead152e3d1e344b594fa134de9a6cf3fd658590 100644 (file)
                a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+(MAX_PORT - \
                                                a->mp_end_port)));      \
        a->mpa_tx.pkt_cnt++;                                            \
-} while (0);
+} while (0)
 
 /* SDIO Tx aggregation limit ? */
 #define MP_TX_AGGR_PKT_LIMIT_REACHED(a)                                        \
        a->mpa_tx.buf_len = 0;                                          \
        a->mpa_tx.ports = 0;                                            \
        a->mpa_tx.start_port = 0;                                       \
-} while (0);
+} while (0)
 
 /* SDIO Rx aggregation limit ? */
 #define MP_RX_AGGR_PKT_LIMIT_REACHED(a)                                        \
        a->mpa_rx.skb_arr[a->mpa_rx.pkt_cnt] = skb;                     \
        a->mpa_rx.len_arr[a->mpa_rx.pkt_cnt] = skb->len;                \
        a->mpa_rx.pkt_cnt++;                                            \
-} while (0);
+} while (0)
 
 /* Reset SDIO Rx aggregation buffer parameters */
 #define MP_RX_AGGR_BUF_RESET(a) do {                                   \
        a->mpa_rx.buf_len = 0;                                          \
        a->mpa_rx.ports = 0;                                            \
        a->mpa_rx.start_port = 0;                                       \
-} while (0);
+} while (0)
 
 
 /* data structure for SDIO MPA TX */
index efb9ab270403321aec894da08569ca97eba6d11d..c4adb97773659b5353b8d1d724e6f3cfa3ff0e8f 100644 (file)
        SET_BITS_OFFSET_LE(__pdesc+28, 0, 32, __val)
 
 #define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size)      \
-do {                                                   \
-       if (_size > TX_DESC_NEXT_DESC_OFFSET)           \
-               memset(__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET);   \
-       else                                            \
-               memset(__pdesc, 0, _size);      \
-} while (0);
+       memset(__pdesc, 0, min_t(size_t, _size, TX_DESC_NEXT_DESC_OFFSET))
 
 struct rx_fwinfo_92c {
        u8 gain_trsw[4];
index 0dc736c2723b827661f973a8a9999fbd1e8f366f..057a52431b0036a9b953b9628397a851cb913995 100644 (file)
        SET_BITS_OFFSET_LE(__pdesc+28, 0, 32, __val)
 
 #define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size)      \
-do {                                                   \
-       if (_size > TX_DESC_NEXT_DESC_OFFSET)           \
-               memset((void *)__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET);   \
-       else                                            \
-               memset((void *)__pdesc, 0, _size);      \
-} while (0);
+       memset((void *)__pdesc, 0,                      \
+              min_t(size_t, _size, TX_DESC_NEXT_DESC_OFFSET))
 
 /* For 92D early mode */
 #define SET_EARLYMODE_PKTNUM(__paddr, __value)         \
index d1b0a1e1497181220146ce9eb82e7a321252ac07..20afec62ce05b2e40105d8150500bf32d5a00e24 100644 (file)
  * the desc is cleared. */
 #define        TX_DESC_NEXT_DESC_OFFSET                        36
 #define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size)              \
-do {                                                           \
-       if (_size > TX_DESC_NEXT_DESC_OFFSET)                   \
-               memset(__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET);   \
-       else                                                    \
-               memset(__pdesc, 0, _size);                      \
-} while (0);
+       memset(__pdesc, 0, min_t(size_t, _size, TX_DESC_NEXT_DESC_OFFSET))
 
 /* Rx Desc */
 #define RX_STATUS_DESC_SIZE                            24
index b4afff62643763f15db2f954d5abc6f1f59e3e3f..d53f4332464daa820ac2b909ba93e5f847e3b420 100644 (file)
@@ -345,7 +345,7 @@ enum fw_h2c_cmd {
        do {                                                    \
                udelay(1000);                                   \
                rtlpriv->rtlhal.fwcmd_iomap &= (~_Bit);         \
-       } while (0);
+       } while (0)
 
 #define FW_CMD_IO_UPDATE(rtlpriv, _val)                                \
        rtlpriv->rtlhal.fwcmd_iomap = _val;
@@ -354,13 +354,13 @@ enum fw_h2c_cmd {
        do {                                                    \
                rtl_write_word(rtlpriv, LBUS_MON_ADDR, (u16)_val);      \
                FW_CMD_IO_UPDATE(rtlpriv, _val);                \
-       } while (0);
+       } while (0)
 
 #define FW_CMD_PARA_SET(rtlpriv, _val)                         \
        do {                                                    \
                rtl_write_dword(rtlpriv, LBUS_ADDR_MASK, _val); \
                rtlpriv->rtlhal.fwcmd_ioparam = _val;           \
-       } while (0);
+       } while (0)
 
 #define FW_CMD_IO_QUERY(rtlpriv)                               \
        (u16)(rtlpriv->rtlhal.fwcmd_iomap)