ARM: shmobile: r8a7790: Add JPU clock dt and CPG define.
authorMikhail Ulyanov <mikhail.ulyanov@cogentembedded.com>
Tue, 19 Aug 2014 12:50:49 +0000 (16:50 +0400)
committerSimon Horman <horms+renesas@verge.net.au>
Fri, 22 Aug 2014 01:49:39 +0000 (10:49 +0900)
Signed-off-by: Mikhail Ulyanov <mikhail.ulyanov@cogentembedded.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm/boot/dts/r8a7790.dtsi
include/dt-bindings/clock/r8a7790-clock.h

index 2278bd0968d1c441ca8a6759d74294d4ae2e7d05..c11541d6dc25d9b71e280e436bf695eef1cf57f4 100644 (file)
                mstp1_clks: mstp1_clks@e6150134 {
                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
-                       clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
+                       clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
                                 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
                                 <&zs_clk>;
                        #clock-cells = <1>;
                        renesas,clock-indices = <
-                               R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
+                               R8A7790_CLK_JPU R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
                                R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
                                R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
                        >;
                        clock-output-names =
-                               "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
+                               "jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
                                "vsp1-du0", "vsp1-rt", "vsp1-sy";
                };
                mstp2_clks: mstp2_clks@e6150138 {
index f929a79e69987fd44a0d8bb8c2f91b40ccb3f4f2..8ea7ab0346ad9c28e248ad648401aff57a8c94bc 100644 (file)
@@ -26,6 +26,7 @@
 #define R8A7790_CLK_MSIOF0             0
 
 /* MSTP1 */
+#define R8A7790_CLK_JPU                6
 #define R8A7790_CLK_TMU1               11
 #define R8A7790_CLK_TMU3               21
 #define R8A7790_CLK_TMU2               22