platform/x86: intel_pmc_core: Fix PCH IP sts reading
authorRajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com>
Fri, 1 Feb 2019 07:32:26 +0000 (13:02 +0530)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Fri, 5 Apr 2019 20:31:35 +0000 (22:31 +0200)
[ Upstream commit 0e68eeea9894feeba2edf7ec63e4551b87f39621 ]

A previous commit "platform/x86: intel_pmc_core: Make the driver PCH
family agnostic <c977b98bbef5898ed3d30b08ea67622e9e82082a>" provided
better abstraction to this driver but has some fundamental issues.

e.g. the following condition

for (index = 0; index < pmcdev->map->ppfear_buckets &&
index < PPFEAR_MAX_NUM_ENTRIES; index++, iter++)

is wrong because for CNL, PPFEAR_MAX_NUM_ENTRIES is hardcoded as 5 which
is _wrong_ and even though ppfear_buckets is 8, the loop fails to read
all eight registers needed for CNL PCH i.e. PPFEAR0 and PPFEAR1. This
patch refactors the pfear show logic to correctly read PCH IP power
gating status for Cannonlake and beyond.

Cc: "David E. Box" <david.e.box@intel.com>
Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Fixes: c977b98bbef5 ("platform/x86: intel_pmc_core: Make the driver PCH family agnostic")
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/platform/x86/intel_pmc_core.c
drivers/platform/x86/intel_pmc_core.h

index 17e08b42b0a97f02c8120f83ed51b4e2cb18d676..aaeb0242a99d0616a58a5e0afa2aae66d32bac74 100644 (file)
@@ -222,7 +222,8 @@ static int pmc_core_ppfear_sts_show(struct seq_file *s, void *unused)
             index < PPFEAR_MAX_NUM_ENTRIES; index++, iter++)
                pf_regs[index] = pmc_core_reg_read_byte(pmcdev, iter);
 
-       for (index = 0; map[index].name; index++)
+       for (index = 0; map[index].name &&
+            index < pmcdev->map->ppfear_buckets * 8; index++)
                pmc_core_display_map(s, index, pf_regs[index / 8], map);
 
        return 0;
index 3d225a9cc09f28dc69228188c54068fff12a8da9..1f13426eb61a916fe3d77d89e9c7a1cf598e9435 100644 (file)
@@ -38,7 +38,7 @@
 #define SPT_PMC_SLP_S0_RES_COUNTER_STEP                0x64
 #define PMC_BASE_ADDR_MASK                     ~(SPT_PMC_MMIO_REG_LEN - 1)
 #define MTPMC_MASK                             0xffff0000
-#define PPFEAR_MAX_NUM_ENTRIES                 5
+#define PPFEAR_MAX_NUM_ENTRIES                 12
 #define SPT_PPFEAR_NUM_ENTRIES                 5
 #define SPT_PMC_READ_DISABLE_BIT               0x16
 #define SPT_PMC_MSG_FULL_STS_BIT               0x18