drm/i915/skl: Correcting the flushing of pipe

We were incorreectly bypassing the flush everytime which led to fifo
underrun when more than one plane is enabled.

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Satheeshakrishna M<satheeshakrishna.m@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0f7ceba2032f74af080a2de9678bb26094ced83e..8a960d19374b0a9baad87180046e64c3154f48aa 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3004,9 +3004,8 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
                    skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
                        skl_wm_flush_pipe(dev_priv, pipe, 2);
                        intel_wait_for_vblank(dev, pipe);
+                       reallocated[pipe] = true;
                }
-
-               reallocated[pipe] = true;
        }
 
        /*